JPS62142849U - - Google Patents
Info
- Publication number
- JPS62142849U JPS62142849U JP1986031010U JP3101086U JPS62142849U JP S62142849 U JPS62142849 U JP S62142849U JP 1986031010 U JP1986031010 U JP 1986031010U JP 3101086 U JP3101086 U JP 3101086U JP S62142849 U JPS62142849 U JP S62142849U
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductor pattern
- solder
- substrate
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 239000011651 chromium Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 4
- 239000010408 film Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10145—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Description
第１図は本考案の半導体集積回路素子実装用基
板構造の一実施例を示す主要断面図。第２図は従
来の半導体集積回路素子実装用基板構造を示す主
要断面図。第３図は第１図の平面図。第４図は本
考案の基板構造を用いた集積回路素子の実装構造
を示す断面図。
１…セラミツク基材、２…ニクロム薄膜、３…
金薄膜、４…クロム薄膜、５…クロム薄膜、６…
銅薄膜、７…ＩＣチツプ、８…半田バンプ。
FIG. 1 is a main cross-sectional view showing an embodiment of the substrate structure for mounting semiconductor integrated circuit elements of the present invention. FIG. 2 is a main cross-sectional view showing a conventional substrate structure for mounting semiconductor integrated circuit elements. FIG. 3 is a plan view of FIG. 1. FIG. 4 is a sectional view showing a mounting structure of an integrated circuit element using the substrate structure of the present invention. 1...Ceramic base material, 2...Nichrome thin film, 3...
Gold thin film, 4...Chromium thin film, 5...Chromium thin film, 6...
Copper thin film, 7...IC chip, 8...solder bump.
Claims (1)
ースダウンボンデイング用基板において、半田バ
ンプとの接合パツド部が、以下の構成を有するこ
とを特徴とする半導体集積回路素子実装用基板構
造。 (a) 基板の絶縁基材としてのセラミツク板 (b) 基板の導体パターン第１層であり、第２層
の金属の下地としての厚さ５００Å〜３０００Å
のニクロム薄膜 (c) 基板の導体パターン第２層であり、半田接
合表面としての厚さ１０００Å〜２００００Åの
金薄膜 (d) 基板の導体パターン第３層であり、上記導
体パターンの、接合時半田バンプと接触する部分
を除いた位置で、かつ半田バンプと接触する部分
に隣接した位置に、半田の流れ止めとして配置さ
れた、厚さ５００Å〜３０００Åのクロム薄膜。[Claims for Utility Model Registration] A substrate for face-down bonding of semiconductor integrated circuit elements having solder bumps, characterized in that a bonding pad portion with the solder bumps has the following configuration: structure. (a) Ceramic plate as the insulating base material of the board (b) First layer of the conductor pattern of the board and a metal base of the second layer with a thickness of 500 Å to 3000 Å
(c) A gold thin film with a thickness of 1,000 Å to 20,000 Å, which is the second layer of the conductor pattern on the substrate and serves as the solder joint surface. (d) A thin film of gold, which is the third layer of the conductor pattern on the substrate, and serves as the solder joint surface of the conductor pattern. A thin chromium film with a thickness of 500 Å to 3000 Å is placed as a solder flow stopper in a position excluding the part that contacts the bump and adjacent to the part that contacts the solder bump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986031010U JPS62142849U (en) | 1986-03-04 | 1986-03-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986031010U JPS62142849U (en) | 1986-03-04 | 1986-03-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62142849U true JPS62142849U (en) | 1987-09-09 |
Family
ID=30836346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986031010U Pending JPS62142849U (en) | 1986-03-04 | 1986-03-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62142849U (en) |
-
1986
- 1986-03-04 JP JP1986031010U patent/JPS62142849U/ja active Pending
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