JPS6457656U - - Google Patents

Info

Publication number
JPS6457656U
JPS6457656U JP1987150143U JP15014387U JPS6457656U JP S6457656 U JPS6457656 U JP S6457656U JP 1987150143 U JP1987150143 U JP 1987150143U JP 15014387 U JP15014387 U JP 15014387U JP S6457656 U JPS6457656 U JP S6457656U
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor
mounting
mounting structure
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987150143U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987150143U priority Critical patent/JPS6457656U/ja
Publication of JPS6457656U publication Critical patent/JPS6457656U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4918—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図から第４図までが本考案に関し、第１図
から第３図は本考案による半導体回路装置の実装
構造のそれぞれ異なる実施例を半導体回路装置の
実装後の状態を示す断面図、第４図はバンプ、バ
ンプ用パツドおよび接続線用パツドの具体構造を
例示する第１の半導体チツプと第２の半導体チツ
プの要部拡大断面図および第２の半導体チツプの
要部拡大平面図である。第５図および第６図は半
導体回路装置の実装構造のそれぞれ異なる従来例
を示す半導体チツプの実装状態の断面図である。 図において、１：半導体チツプ、１ａ：接続配
線導体、１ｂ：バンプ、２：半導体基板、３：配
線導体、４：接着層、５：ボンデイング線、１０
：第１の半導体チツプないしはフリツプチツプ、
１０ａ：半導体回路、１１：半導体基板、１１ａ
：半導体層、１２：酸化膜、１３：接続膜、１４
：下地膜、１５：窒化膜、２０：第２の半導体チ
ツプ、２０ａ：半導体回路、２０ｂ：接続手段、
２０ｃ：凹み、２１：半導体基板ないしは多結晶
シリコン、２２：酸化膜、２３：接続膜、２４：
接合膜、２５：窒化膜、３０：バンプ、４０：接
続線ないしはボンデイング線、４１：接続線とし
ての可撓性シート、５０：バンプ用パツド、６０
：接続線用パツド、７０：実装対象、７１：セラ
ミツク基板、７２：配線導体、７３：金属体、７
４：絶縁層、７５：端子、７６：プラスチツク基
板、７６ａ：窓、７７：配線導体、８０：接着層
、８１：ゴム弾性体、である。 1 to 4 relate to the present invention, and FIGS. 1 to 3 are cross-sectional views showing different embodiments of the mounting structure of a semiconductor circuit device according to the present invention, respectively, showing the state after the semiconductor circuit device is mounted. FIG. 4 is an enlarged sectional view of the main parts of the first semiconductor chip and the second semiconductor chip, and an enlarged plan view of the main parts of the second semiconductor chip, illustrating the specific structures of the bumps, bump pads, and connection line pads. . FIGS. 5 and 6 are cross-sectional views of semiconductor chips mounted, showing different conventional examples of mounting structures for semiconductor circuit devices. In the figure, 1: semiconductor chip, 1a: connection wiring conductor, 1b: bump, 2: semiconductor substrate, 3: wiring conductor, 4: adhesive layer, 5: bonding line, 10
: first semiconductor chip or flip chip,
10a: semiconductor circuit, 11: semiconductor substrate, 11a
: semiconductor layer, 12: oxide film, 13: connection film, 14
: base film, 15: nitride film, 20: second semiconductor chip, 20a: semiconductor circuit, 20b: connection means,
20c: recess, 21: semiconductor substrate or polycrystalline silicon, 22: oxide film, 23: connection film, 24:
Bonding film, 25: Nitride film, 30: Bump, 40: Connection line or bonding line, 41: Flexible sheet as connection line, 50: Bump pad, 60
: Connection wire pad, 70: Mounting target, 71: Ceramic substrate, 72: Wiring conductor, 73: Metal body, 7
4: insulating layer, 75: terminal, 76: plastic substrate, 76a: window, 77: wiring conductor, 80: adhesive layer, 81: rubber elastic body.

Claims (1)

【実用新案登録請求の範囲】 (1) 半導体回路装置を配線基板等の実装対象に
実装かつ接続するための構造であつて、半導体回
路の少なくとも一部を含み該回路に接続されたバ
ンプを備える第１の半導体チツプと、接続線用パ
ツドとバンプとの接続用のバンプ用パツドを備え
る第２の半導体チツプとからなり、第２の半導体
チツプを実装対象に固定した上でその接続線用パ
ツドの実装対象と接続線により接続し、第１の半
導体チツプをそのバンプを第２の半導体チツプの
バンプ用パツドに接合することにより第２の半導
体チツプ上に固定かつ接続するようにしたことを
特徴とする半導体回路装置の実装構造。 (2) 実用新案登録請求の範囲第１項に記載の実
装構造において、第１の半導体チツプのバンプと
してはんだバンプが用いられることを特徴とする
半導体回路装置の実装構造。 (3) 実用新案登録請求の範囲第１項に記載の実
装構造において、第２の半導体チツプに半導体回
路の一部が組み込まれることを特徴とする半導体
回路装置の実装構造。 (4) 実用新案登録請求の範囲第３項に記載の実
装構造において、第１の半導体チツプにＭＯＳ回
路が組み込まれ、第２の半導体チツプにバイポー
ラ回路が組み込まれることを特徴とする半導体回
路装置の実装構造。 (5) 実用新案登録請求の範囲第３項に記載の実
装構造において、第２の半導体チツプがその中央
部を実装対象に固着することにより実装対象に固
定されることを特徴とする半導体回路装置の実装
構造。 (6) 実用新案登録請求の範囲第１項に記載の実
装構造において、第２の半導体チツプに接続線用
パツド、バンプ用パツドおよび両者間の接続手段
のみが組み込まれることを特徴とする半導体回路
装置の実装構造。 (7) 実用新案登録請求の範囲第６項に記載の実
装構造において、第２の半導体チツプの基板とし
て多結晶シリコンが用いられることを特徴とする
半導体回路装置の実装構造。[Claims for Utility Model Registration] (1) A structure for mounting and connecting a semiconductor circuit device to a mounting target such as a wiring board, which includes bumps that include at least a portion of a semiconductor circuit and are connected to the circuit. It consists of a first semiconductor chip and a second semiconductor chip equipped with a bump pad for connecting a connection line pad and a bump, and after fixing the second semiconductor chip to a mounting object, the connection line pad is The first semiconductor chip is fixed and connected to the second semiconductor chip by connecting the first semiconductor chip to the mounting target by a connection line, and bonding the bumps to the bump pads of the second semiconductor chip. Mounting structure of semiconductor circuit device. (2) Utility Model Registration A mounting structure for a semiconductor circuit device according to claim 1, characterized in that solder bumps are used as bumps on the first semiconductor chip. (3) Utility Model Registration Scope of Claim 1. A mounting structure for a semiconductor circuit device, characterized in that a part of the semiconductor circuit is incorporated in the second semiconductor chip. (4) A semiconductor circuit device characterized in that in the mounting structure according to claim 3 of the utility model registration claim, a MOS circuit is incorporated in the first semiconductor chip, and a bipolar circuit is incorporated in the second semiconductor chip. implementation structure. (5) A semiconductor circuit device in the mounting structure according to claim 3 of the utility model registration, characterized in that the second semiconductor chip is fixed to the mounting object by fixing its center portion to the mounting object. implementation structure. (6) A semiconductor circuit characterized in that, in the mounting structure described in claim 1 of the utility model registration claim, only a connection line pad, a bump pad, and connection means between the two are incorporated in the second semiconductor chip. Device mounting structure. (7) A mounting structure for a semiconductor circuit device according to claim 6, wherein polycrystalline silicon is used as the substrate of the second semiconductor chip.
JP1987150143U 1987-09-30 1987-09-30 Pending JPS6457656U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987150143U JPS6457656U (en) 1987-09-30 1987-09-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987150143U JPS6457656U (en) 1987-09-30 1987-09-30

Publications (1)

Publication Number Publication Date
JPS6457656U true JPS6457656U (en) 1989-04-10

Family

ID=31423017

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987150143U Pending JPS6457656U (en) 1987-09-30 1987-09-30

Country Status (1)

Country Link
JP (1) JPS6457656U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000022074A (en) * 1998-07-03 2000-01-21 Rohm Co Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000022074A (en) * 1998-07-03 2000-01-21 Rohm Co Ltd Semiconductor device

Similar Documents

Publication Publication Date Title
EP0847088A3 (en) Semiconductor device, method for manufacturing the same, and method for mounting the same
JPH0238446Y2 (en)
JP3496569B2 (en) Semiconductor device, its manufacturing method and its mounting structure
JPS6457656U (en)
JP2982182B2 (en) Resin-sealed semiconductor device
JPS58218130A (en) Hybrid integrated circuit
JP2880817B2 (en) Semiconductor integrated circuit device
KR930007920Y1 (en) Double package structure having both side thin film
JPH0396243A (en) Semiconductor integrated circuit device
JPS63276237A (en) Method for bonding integrated circuit to substrate
JPH054279Y2 (en)
JPS6389280U (en)
JPS6232550U (en)
JPS6338328U (en)
JPS646041U (en)
JPS63187330U (en)
JPS62180738U (en)
JPS6310571U (en)
JPS5883150U (en) Semiconductor integrated circuit device
JPH0189752U (en)
JPS61153374U (en)
JPS614435U (en) integrated circuit device
JPS6416636U (en)
JPS62285434A (en) Semiconductor device
JPS62192642U (en)