JPS58218130A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS58218130A
JPS58218130A JP57101013A JP10101382A JPS58218130A JP S58218130 A JPS58218130 A JP S58218130A JP 57101013 A JP57101013 A JP 57101013A JP 10101382 A JP10101382 A JP 10101382A JP S58218130 A JPS58218130 A JP S58218130A
Authority
JP
Japan
Prior art keywords
chip
wiring
integrated circuit
substrate
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57101013A
Other languages
Japanese (ja)
Inventor
Kenichi Takahira
高比良　賢一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57101013A priority Critical patent/JPS58218130A/en
Publication of JPS58218130A publication Critical patent/JPS58218130A/en
Pending legal-status Critical Current

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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Abstract

PURPOSE:To utilize a semiconductor wafer effectively, and to increase the degree of integration without augmenting an area of a substrate by mounting circuits on both surfaces of the wafer, forming a metallic pad for bonding to the surface of the wafer, and holding an IC chip on the substrate of the hybrid integrated circuit in the back while forming a solder bump for electrical connection with wiring on the substrate. CONSTITUTION:With the hybrid integrated circuit, the circuits are mounted to both surfaces of the semiconductor wafer chip 6 mounted to the substrate 5, and the metallic pads 6a are formed to the surface side and the solder bumps 6c to the back side for several electric connection. The IC chip 6 is arranged to the hybrid integrated circuit substrate 5, to both surfaces thereof wiring 7, 8 are executed, while directing the metallic pads 6a upward. The surface side of the IC chip 6 is connected to wiring 7 on the surface side of the substrate 5 through wire bonding, and the bumps 6c on the back side fix the IC chip 6 while being connected to wiring 7a on the surface side of the substrate 2. The wiring 7a are connected to wiring 8 on the back side of the substrate 5 through through-holes 8a.

Description

【発明の詳細な説明】 本発明は、混成集積回路、特に該混成集積回路基板上に
実装するＩＣチップ構造の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit, and particularly to an improvement in the structure of an IC chip mounted on the hybrid integrated circuit board.

従来、この種の装置として第１図に示すものがあった。Conventionally, there has been a device of this type as shown in FIG.

図において、（１）は混成集積回路基板、（２）μ半導
体ウェハ上に回路を実装したＩＣチップ、（３ａ）は該
チップ（２）上に形成された金属パッド、（３ｂ）はポ
ンディング用ワイヤ、（４）は基板（１）上の配線であ
る。In the figure, (1) is a hybrid integrated circuit board, (2) an IC chip with a circuit mounted on a μ semiconductor wafer, (3a) is a metal pad formed on the chip (2), and (3b) is a bonding pad. The wire (4) is the wiring on the substrate (1).

従来の混成集積′回路用ＩＣチップ（２）を混成回路基
板（１）上に配置する場合、該基板（１）上にＩＣチッ
プ（２）を直接搭載し、該チップ（２）上の金属パッド
（３りと基板（１）上の配線（４）とをワイヤボンドし
、金属ワイヤ（３ｂ）によシｌＣチップ（２）と配線（
４）とを接続するようにしている。このため該チップ（
２）の構造は第１図から理解できるようにウェハに片面
しか回路を実装できず、ウェハを有効利用していない。When placing an IC chip (2) for a conventional hybrid integrated circuit on a hybrid circuit board (1), the IC chip (2) is directly mounted on the board (1), and the metal on the chip (2) is mounted directly on the board (1). Wire bond the pad (3) and the wiring (4) on the board (1), and connect the IC chip (2) and the wiring (2) to the metal wire (3b).
4). Therefore, the chip (
As can be understood from FIG. 1, the structure 2) allows circuits to be mounted on only one side of the wafer, and does not make effective use of the wafer.

またこのことが基板（１）の面積を増大させる原因にも
なっている。This also causes an increase in the area of the substrate (1).

この発明は、上記のような従来のものの欠点を除去する
ためになされたもので、半導体ウェハの両面に回路を実
装し、該ウェハの表面にはホンディング用の金属パッド
を形成し、裏面には混成集積回路基板上にＩＣチップを
保持するとともに該基板上の配線と電気的に接続するた
めのハンダバンプを形成することによシ、ウェハを有効
利用でき、基板の面積を増大させずに高集積度化を達成
できる混成集積回路を提供することを目的としている。This invention was made in order to eliminate the drawbacks of the conventional ones as described above. Circuits are mounted on both sides of a semiconductor wafer, metal pads for bonding are formed on the front side of the wafer, and metal pads for bonding are formed on the back side of the wafer. By holding IC chips on a hybrid integrated circuit board and forming solder bumps for electrical connection with the wiring on the board, the wafer can be used effectively, and the area of the board can be increased without increasing the area. The purpose of this invention is to provide a hybrid integrated circuit that can achieve higher integration.

以下、この発明の一実施例を図について説明する。An embodiment of the present invention will be described below with reference to the drawings.

第２図は本発明の一実施例による混成集積回路の断面図
である。FIG. 2 is a cross-sectional view of a hybrid integrated circuit according to an embodiment of the present invention.

本発明による混成集積回路は、基板（５）に実装する半
導体ウニハチラグ（６）の両面に回路を実装し、それぞ
れの電気的接続のために表側に金属バット（６ａ）　、
裏側にハンダバンプ（６ｃ）を形成したものである。The hybrid integrated circuit according to the present invention has circuits mounted on both sides of a semiconductor sea urchin lugs (6) mounted on a substrate (5), and metal bats (6a) on the front side for electrical connection.
A solder bump (6c) is formed on the back side.

両面に配＆　（７１＋８１を施した混成集積回路基板（
５）に上記の構造のＩＣチップ（６）が金属パッド（６
ａ）を上にして配置されている。ｌＪチップ（６）の表
側はワイヤボンディングにより基板（５）の底側の配線
（７）に接続され、裏側のバンプ（６Ｃ）ｌはＩｃチッ
プ（６）を固′１ 定するとともに、基板（２）の表側の配線（７りに接続
されている。なおこの配！　（７ａ）はスルーホール（
８ａ）を介して基板（５）の裏側の配線（８）につなが
っているものである。Hybrid integrated circuit board with 71+81 on both sides (
5), an IC chip (6) with the above structure is attached to a metal pad (6).
It is placed with a) facing up. The front side of the lJ chip (6) is connected to the wiring (7) on the bottom side of the board (5) by wire bonding, and the bumps (6C) on the back side fix the Ic chip (6) and connect the board ( It is connected to the wiring (7) on the front side of 2). Note that this wiring! (7a) is connected to the through hole (7a).
8a) to the wiring (8) on the back side of the board (5).

なお、第２図に示す例では単層の基板を用いているが、
勿論多層の基板にも利用でき、この場合、よシ高集積度
な混成集積回路を実現できる。Although the example shown in Figure 2 uses a single layer substrate,
Of course, it can also be used for multilayer substrates, and in this case, a hybrid integrated circuit with a higher degree of integration can be realized.

第３図は上記の様なＩＣチップを重畳して用いる例を示
す。図において、（１０）は基板（５）上に配置された
ＩＣチップである。チップ００）の表側の回路はワイヤ
（１０ｂ）によシ基板（５）の表側の配線（７）と接続
され、裏側の回路はノ・ンダバンプ（ＩＯＣ）により、
基板（５）の裏側の配線（８）につながっている配線（
７ａ）に接続されている。またＩＣチップ（９）はチッ
プ叫の上に配置されておシ、両チップ＋９１　（１０の
表側の回路は金属パッド（９ａＸｔｏａ）およびワイヤ
（９ｂ）を介して接続され、チップ’　＋９１の裏側の
回路は・・・ダ・・・プ（９Ｃ）および金属７配線（１
０ｄ）によシチツプ００の表側の回路と接続され゛てい
る。このようにすれば立体的にＩＣチップを□実装でき
、さらに高集積度な混成集積回路が実現可能となる。FIG. 3 shows an example in which the above-mentioned IC chips are used in a superimposed manner. In the figure, (10) is an IC chip placed on a substrate (5). The circuit on the front side of the chip 00) is connected to the wiring (7) on the front side of the board (5) through a wire (10b), and the circuit on the back side is connected to the wiring (7) on the front side of the board (5) by a wire (10b).
The wiring (
7a). Also, the IC chip (9) is placed on top of the chip, and the circuits on the front side of both chips +91 (10) are connected via metal pads (9aXtoa) and wires (9b), and the circuits on the back side of the chip '+91 The circuit is...dap (9C) and metal 7 wiring (1
0d) is connected to the circuit on the front side of the chip 00. In this way, IC chips can be mounted three-dimensionally, and a hybrid integrated circuit with a higher degree of integration can be realized.

以上のように、この発明によれば半導体ウエノ・の両面
に回路を実装し、該ウエノ・の表面にはポンディング用
の金属パッドを形成し、裏面には混成集積回路基板にＩ
Ｃチップを保持するとともに該基板上の配線と電気的に
接続するためのノ・ンダノ（ンプを形成するようにした
ので、従来の片面しか利用しなかったＩＣチップよシ、
チップをよシ効果的に利用でき、高集積度の混成集積回
路を小型化して得ることができる効果がある０As described above, according to the present invention, circuits are mounted on both sides of a semiconductor wafer, metal pads for bonding are formed on the front surface of the wafer, and an I/O circuit is mounted on a hybrid integrated circuit board on the back surface of the wafer.
By forming a non-conductor to hold the C chip and electrically connect it to the wiring on the board, it is much easier to use than the conventional IC chip, which only uses one side.
Chips can be used more effectively, and high-density hybrid integrated circuits can be miniaturized.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、従来のＩＣチップを用いた混成集積回路の断
面図、第２図は本発明の一実施例による混成集積回路の
断面図、第３図は本発明の他の実施例による混成集積回
路の断面図である。 （６１＋９１　（１０）−Ｉ　Ｃチップ、（６ａＸ９ａ
Ｘ１０ａ）−・・金楓ノ＜ラド（６ＣＸ９ｃＸｌＯｃ）
・・・ノ・ンダバンプ、（５）・・・基板、（７＋　＋
８１・・・配線０ なお図中同一符号は同−又は相当部分を示す。 代　理　人　　　　葛　　野　　信　　−第１図 第２図 第３図FIG. 1 is a cross-sectional view of a hybrid integrated circuit using a conventional IC chip, FIG. 2 is a cross-sectional view of a hybrid integrated circuit according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of a hybrid integrated circuit according to another embodiment of the present invention. 1 is a cross-sectional view of an integrated circuit. (61+91 (10)-IC chip, (6aX9a
X10a) - Golden Kaede < Rad (6CX9cXlOc)
...No.bump, (5)...Substrate, (7+ +
81...Wiring 0 Note that the same reference numerals in the drawings indicate the same or corresponding parts. Agent Makoto Kuzuno - Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] （１）混成集積回路基板と、半導体ウェハの両面に回路
が実装されたＩＣチップと、このＩＣチップの表面側に
形成された上記混成集積回路基板上の配線との間でワイ
ヤボンディングするための金属パッドと、上記ＩＣチッ
プの裏・面側に形成され該ＩＣチップを上記混成集積回
路基板上で保持するとともに該回路基板上の配線との間
で電気的接続を行なうだめのハンダバンプとを備えたこ
とを特徴とする混成集積回路。(1) For wire bonding between a hybrid integrated circuit board, an IC chip with circuits mounted on both sides of a semiconductor wafer, and wiring on the hybrid integrated circuit board formed on the front side of this IC chip. A metal pad, and solder bumps formed on the back and front sides of the IC chip to hold the IC chip on the hybrid integrated circuit board and to make electrical connection with the wiring on the circuit board. A hybrid integrated circuit characterized by:
JP57101013A 1982-06-11 1982-06-11 Hybrid integrated circuit Pending JPS58218130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57101013A JPS58218130A (en) 1982-06-11 1982-06-11 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57101013A JPS58218130A (en) 1982-06-11 1982-06-11 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS58218130A true JPS58218130A (en) 1983-12-19

Family

ID=14289335

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57101013A Pending JPS58218130A (en) 1982-06-11 1982-06-11 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS58218130A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
US6340845B1 (en) * 1999-01-22 2002-01-22 Nec Corporation Memory package implementing two-fold memory capacity and two different memory functions
US6472738B2 (en) 2000-09-08 2002-10-29 Fujitsu Quantum Devices Limited Compound semiconductor device
US6706557B2 (en) 2001-09-21 2004-03-16 Micron Technology, Inc. Method of fabricating stacked die configurations utilizing redistribution bond pads
US8102038B2 (en) * 2009-09-18 2012-01-24 Texas Instruments Incorporated Semiconductor chip attach configuration having improved thermal characteristics

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
US6340845B1 (en) * 1999-01-22 2002-01-22 Nec Corporation Memory package implementing two-fold memory capacity and two different memory functions
US6472738B2 (en) 2000-09-08 2002-10-29 Fujitsu Quantum Devices Limited Compound semiconductor device
US6706557B2 (en) 2001-09-21 2004-03-16 Micron Technology, Inc. Method of fabricating stacked die configurations utilizing redistribution bond pads
US6847105B2 (en) * 2001-09-21 2005-01-25 Micron Technology, Inc. Bumping technology in stacked die configurations
US8102038B2 (en) * 2009-09-18 2012-01-24 Texas Instruments Incorporated Semiconductor chip attach configuration having improved thermal characteristics

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