JPS6076149A - Chip carrier - Google Patents

Chip carrier

Info

Publication number
JPS6076149A
JPS6076149A JP58184777A JP18477783A JPS6076149A JP S6076149 A JPS6076149 A JP S6076149A JP 58184777 A JP58184777 A JP 58184777A JP 18477783 A JP18477783 A JP 18477783A JP S6076149 A JPS6076149 A JP S6076149A
Authority
JP
Japan
Prior art keywords
conductor circuits
carrier
chip
lsi chip
fitted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58184777A
Other languages
Japanese (ja)
Inventor
Yukio Yamaguchi
幸雄 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58184777A priority Critical patent/JPS6076149A/en
Publication of JPS6076149A publication Critical patent/JPS6076149A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To improve the characteristics of heat dissipation remarkably, and to mount parts with high density by dissipating heat generated from an LSI chip through a heat dissipating body fitted to a chip carrier. CONSTITUTION:A heat dissipating body 17 is fitted to an upper section and conductor circuits 12 are fitted to a side surface in a carrier proper 11, and conductor circuits 14 are mounted to a terminal board 13, and connected electrically to said conductor circuits 12 by a cementing material 15, such as solder, adhesives, etc. The heat dissipating body 17 penetrates the carrier proper 11, the conductor circuits 12 are connected to the inside, side surface and lower surface of the carrier proper 11, and have a space, the inside thereof loads an LSI chip 16, and the conductor circuits 14 are connected to both surfaces of the terminal board 13. Leads 19 for the LSI chip 16 are connected to the conductor circuits 12, the conductor circuits 12 are connected to the conductor circuits 14 for the terminal board 13 by the cementing material 15, such as solder, adhesives, etc., the lower surface sections of the conductor circuits 14 are fitted to a printed substrate through soldering, etc. and the carrier is used. A space 20 is buried with a resin or lower melting-point glass in order to protect the LSI chip 16.

Description

【発明の詳細な説明】 〔発明の属する技術公平ｔ〕 本発明は電子装置などに使用される配線基板へＬＳＩチ
ップを実装するだめのチックキャリヤに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical fairness to which the invention pertains] The present invention relates to a tick carrier for mounting an LSI chip on a wiring board used in an electronic device or the like.

〔従来波４ｈｊ　） １．８１チツプを実装する１県に使用する従来のチップ
キャリヤでは、ＬＳＩチップで発生する熱はチップキャ
リヤを介して外部へ放熱している。第１図は従来のチッ
プキャリヤの斜視図、第２図はｔの部分切断側面図であ
る。第１図および第２図に示すように、ＬＳＩチップ６
をキャリヤ本体１の導体パッド７に半田や接着剤等の接
合材８で取シ付け、ＬＳＩチッ゛プロのリード９を側面
および下面にっｒｊがる導体回路２に電気的接続を行い
、端子板３の両面につりがる導体回路４に前記キャリヤ
本体１の導体回路２を半田や接着剤等の接合材５により
電気的接続が行われ、ＬＳＩチップ６の保護のために樹
脂や低融点ガラスで空間１０を埋め込まれる。[Conventional wave 4hj] In the conventional chip carrier used in one prefecture where a 1.81 chip is mounted, the heat generated in the LSI chip is radiated to the outside via the chip carrier. FIG. 1 is a perspective view of a conventional chip carrier, and FIG. 2 is a partially cutaway side view at t. As shown in FIGS. 1 and 2, the LSI chip 6
are attached to the conductor pads 7 of the carrier body 1 with a bonding material 8 such as solder or adhesive, electrically connect the leads 9 of the LSI chip pro to the conductor circuits 2 that run on the side and bottom surfaces, and connect the terminals. The conductor circuits 2 of the carrier body 1 are electrically connected to the conductor circuits 4 suspended on both sides of the plate 3 by a bonding material 5 such as solder or adhesive. Space 10 is filled with glass.

このとき、ＬＳＩチップ６の熱はキャリヤ本体１を介し
てその上に設けられる所のヒートシンク、ヒートパイプ
（図示されていなｉ）等の放熱材へ伝えられる。At this time, the heat of the LSI chip 6 is transferred via the carrier body 1 to a heat dissipating material such as a heat sink or a heat pipe (i, not shown) provided thereon.

このような構造においては、ＬＳＩチップから発生する
熱量が少ない場合は十分であるが、キャリヤ本体１の熱
抵抗が大きいために、発熱量の多い場合にはかかるＬＩ
Ｉチップを搭載できないという欠点がある。In such a structure, it is sufficient when the amount of heat generated from the LSI chip is small, but because the thermal resistance of the carrier body 1 is large, when the amount of heat generated is large, the LI
The drawback is that it cannot be equipped with an I-chip.

〔発明の目的〕[Purpose of the invention]

本発明の目的は上述の従来のＬＳＩチップ実装上の欠点
を解決し放熱特性を格段に向上したチップキャリヤを提
供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a chip carrier that solves the above-mentioned drawbacks of conventional LSI chip mounting and has significantly improved heat dissipation characteristics.

〔発明の構成〕[Structure of the invention]

本発明のチップキャリヤは、ＬＳＩチップを搭載する放
熱体を上面に有し前記ＬＳＩチップのリードを接続され
る導体回路を側面及び下面に有するキャリヤ本体と、 前記キャリヤ本体の導体回路と接続して外部回路と前記
ＬＳＩチップとの接続をする端子板とを含んで構成され
る。The chip carrier of the present invention has a carrier body having a heat dissipating body for mounting an LSI chip on the upper surface and a conductor circuit connected to the leads of the LSI chip on the side and lower surfaces, and a carrier body connected to the conductor circuit of the carrier body. It is configured to include an external circuit and a terminal board for connecting with the LSI chip.

〔実施例の説明〕[Explanation of Examples]

次に図面を参照して本発明の詳細な説明する。 Next, the present invention will be described in detail with reference to the drawings.

第３図は本発明の一実施例を示す斜視図である。FIG. 3 is a perspective view showing an embodiment of the present invention.

第３図において、キャリヤ本体１１には、上部に放熱体
１７を、側面に導体回路１２．が設けられている。端子
板１３には導体回路１４が設けられれていて、半田や接
着剤等の接合材１５により前記導体回路１２に電気的に
接続されている。In FIG. 3, the carrier body 11 has a heat sink 17 on the top and a conductor circuit 12 on the side. is provided. A conductor circuit 14 is provided on the terminal board 13 and electrically connected to the conductor circuit 12 by a bonding material 15 such as solder or adhesive.

第４図は本発明の一実施例の部分断面を示す側面図であ
る。FIG. 4 is a side view showing a partial cross section of an embodiment of the present invention.

第４図において、放熱体１７はキャリヤ本体Ｕを貫通し
ていて、導体回路１２は、キャリヤ本体１１の内部と、
側面および下面につｒｊがっていて、Ｌ、８Ｉチツプ１
６を内部に搭載するスペースを有している。導体回路１
４は端子板１３の両面につｔがっている。In FIG. 4, the heat sink 17 passes through the carrier body U, and the conductor circuit 12 is connected to the inside of the carrier body 11,
Connected to the side and bottom surface, L, 8I chip 1
It has space to mount 6 inside. Conductor circuit 1
4 is connected to both sides of the terminal board 13.

ＬＳＩチップ１６は放熱体１７に半日または接着剤等の
接合台１８により接続される。The LSI chip 16 is connected to the heat radiator 17 by a bonding table 18 made of adhesive or the like.

ＬＳＩチップ１６のリード１９は導体回路１２に接続さ
れ、前記導体回路１２は半田または接着剤等の接合材１
５によシ端子板１３の導体回路１４に接続され、前記導
体回路１４の下面部分が印刷基板に半田付は等によシ取
シ付けられ使用される。The leads 19 of the LSI chip 16 are connected to a conductor circuit 12, and the conductor circuit 12 is coated with a bonding material 1 such as solder or adhesive.
5 is connected to the conductor circuit 14 of the terminal board 13, and the lower surface portion of the conductor circuit 14 is attached to a printed circuit board by soldering or the like for use.

ＬＳＩチップ１６の保龜のために樹脂や低融点ガラスで
空間２０を埋め込む。The space 20 is filled with resin or low melting point glass to hold the LSI chip 16 in place.

このようにして本実施例のチップキャリヤは、キャリヤ
本体１１の材質、たとえばアルミナセラミック（熱伝導
率約０．０４　ｃａｌｌ、／ａｄ・ｓｅｃ・句に比べて
、低い熱抵抗の導体、ンｔとえば用タングステン合金（
熱伝導率約０．６　ｃａｌＡｔ／ｌ−５ｅｅ−℃）に熱
を伝え、その上に設けられるヒートシンク等ヲζ伝見ら
れるので、熱の放散性がよくなシ発熱量の大きいＬＳＩ
チップも搭載できることになる。In this way, the chip carrier of this embodiment is made of a conductor having a lower thermal resistance than the material of the carrier body 11, such as alumina ceramic (thermal conductivity of about 0.04 call, /ad・sec・phrase). For example, tungsten alloy (
It conducts heat with a thermal conductivity of approximately 0.6 calAt/l-5ee-℃), and has a heat sink installed above it, so it has good heat dissipation and is used for LSIs with a large amount of heat.
It will also be possible to mount a chip.

〔発明の効果〕〔Effect of the invention〕

本発明にＦｉＬｓＩチップからの発熱をチップキャリヤ
に設けた放熱体を介して放散でき放熱特性を格段に向上
できるので、従来のチップキャリヤに比し発熱黛の多い
ＬＳＩチップでもＭ載でき、従来よシ高密度な実装がで
きるという効果がある。In the present invention, the heat generated from the FiLsI chip can be dissipated through the heat dissipation body provided on the chip carrier, and the heat dissipation characteristics can be significantly improved. This has the effect of allowing high-density implementation.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のチップキャリヤの斜視図、第２図は第１
図の部分切断側面図、第３図は本発明の一実施例の斜視
図、第４図は第３図の部分切断側面図である。 １．１１・・・・・・キャリヤ本体、２．１２・・・・
・・導体回路、３．１３・・・・・・端子板、４．１４
・・・・・・導体回路、５．１５・・・・・・接合材、
６．１６・・・・・・ＬＳＩチップ、７・・・・・・感
体パッド、８，１８・・・・・・接合材、９、１９・・
・・・・リード、１０．２０・・・・・・空間、１７・
・・・・・放熱体。Figure 1 is a perspective view of a conventional chip carrier, and Figure 2 is a perspective view of a conventional chip carrier.
3 is a perspective view of one embodiment of the present invention, and FIG. 4 is a partially cutaway side view of FIG. 3. 1.11... Carrier body, 2.12...
...Conductor circuit, 3.13...Terminal board, 4.14
...Conductor circuit, 5.15... Bonding material,
6.16... LSI chip, 7... Sensor pad, 8, 18... Bonding material, 9, 19...
・・・Lead, 10.20・・・Space, 17・
... Heat sink.

Claims (1)

【特許請求の範囲】[Claims] ＬＳＩチップを搭載する放熱体を上面に有し前記ＬＳＩ
チップのリードと接続されるζ導体回路を側面および下
面に有するキャリヤ本体と、前記キャリヤ本体の４１一
体回路と接続して外部回路と前記ＬＳＩチップとの接続
をする部子板とを含むことをｌ￥４ｆＭとするチップキ
ャリヤ。The LSI has a heat dissipation body on the top surface on which the LSI chip is mounted.
The carrier body has a ζ conductor circuit on the side and bottom surfaces to be connected to the leads of the chip, and a component board that connects to the 41 integrated circuit of the carrier body to connect an external circuit and the LSI chip. Chip carrier priced at ¥4fM.
JP58184777A 1983-10-03 1983-10-03 Chip carrier Pending JPS6076149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58184777A JPS6076149A (en) 1983-10-03 1983-10-03 Chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58184777A JPS6076149A (en) 1983-10-03 1983-10-03 Chip carrier

Publications (1)

Publication Number Publication Date
JPS6076149A true JPS6076149A (en) 1985-04-30

Family

ID=16159120

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58184777A Pending JPS6076149A (en) 1983-10-03 1983-10-03 Chip carrier

Country Status (1)

Country Link
JP (1) JPS6076149A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6262545A (en) * 1985-09-12 1987-03-19 Nec Corp Chip carrier and manufacture thereof
EP0674814A1 (en) * 1993-09-20 1995-10-04 Tessera, Inc. Method of forming interface between die and chip carrier
US6756666B2 (en) * 1999-12-24 2004-06-29 Nec Corporation Surface mount package including terminal on its side

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6262545A (en) * 1985-09-12 1987-03-19 Nec Corp Chip carrier and manufacture thereof
EP0674814A1 (en) * 1993-09-20 1995-10-04 Tessera, Inc. Method of forming interface between die and chip carrier
EP0674814A4 (en) * 1993-09-20 1998-02-25 Tessera Inc Method of forming interface between die and chip carrier.
US6756666B2 (en) * 1999-12-24 2004-06-29 Nec Corporation Surface mount package including terminal on its side

Similar Documents

Publication Publication Date Title
CA2075593A1 (en) Semiconductor chip module and method for manufacturing the same
JPS5875859A (en) Semiconductor device
JPS6076149A (en) Chip carrier
JPH03195053A (en) Inverter device
JP2590521B2 (en) Chip carrier
JPS59219942A (en) Chip carrier
JP2745786B2 (en) TAB semiconductor device
JPS59198739A (en) Chipcarrier
JPS58218130A (en) Hybrid integrated circuit
JPS61137349A (en) Semiconductor device
KR950006441Y1 (en) High heat semiconductor package
JPS63136655A (en) Chip carrier
JPS6076148A (en) Chip carrier
US6265769B1 (en) Double-sided chip mount package
JPH10107091A (en) Mounting structure of electronic component and manufacture thereof
JPS5559746A (en) Semiconductor device and its mounting circuit device
JPS61147554A (en) Hybrid ic module
JP3462591B2 (en) Hybrid integrated circuit device
MY127468A (en) Metal substrate having an ic chip and carrier mounting
JPS5923531A (en) Semiconductor device
JPH0878616A (en) Multi-chip module
JPS6125222B2 (en)
JPH04124860A (en) Semiconductor package
JPS60250655A (en) Integrated circuit package
JPS59165446A (en) Integrated circuit structure