JPS63167733U - - Google Patents

Info

Publication number
JPS63167733U
JPS63167733U JP1987060505U JP6050587U JPS63167733U JP S63167733 U JPS63167733 U JP S63167733U JP 1987060505 U JP1987060505 U JP 1987060505U JP 6050587 U JP6050587 U JP 6050587U JP S63167733 U JPS63167733 U JP S63167733U
Authority
JP
Japan
Prior art keywords
electrode portion
substrate
electrically connected
mounting structure
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987060505U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987060505U priority Critical patent/JPS63167733U/ja
Publication of JPS63167733U publication Critical patent/JPS63167733U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａ〜ｅ及び第２図ａ〜ｃは本考案の一実
施例を製造するプロセスを示す断面図、第３図は
従来例を示す断面図である。 １，１５：硬質プリント基板、２：導体、３：
ベアチツプＩＣ、４：パツド、５：金属細線、６
，１４：モールド樹脂、７：キヤピラリ、８：ト
ーチ電極、９：微小ボール、１０：ＦＰＣ、１１
：第１の接合電極、１２：第２の接合電極、１３
，１７；：はんだパターン、１６：第３の接合電
極、１８：スルーホール。 1A to 1E and 2A to 2C are cross-sectional views showing a process for manufacturing an embodiment of the present invention, and FIG. 3 is a cross-sectional view showing a conventional example. 1, 15: Rigid printed circuit board, 2: Conductor, 3:
Bare chip IC, 4: Padded, 5: Fine metal wire, 6
, 14: mold resin, 7: capillary, 8: torch electrode, 9: minute ball, 10: FPC, 11
: first bonding electrode, 12: second bonding electrode, 13
, 17;: solder pattern, 16: third bonding electrode, 18: through hole.

Claims (1)

【実用新案登録請求の範囲】 １ 半導体素子表面の電極部を、保持基板に形成
した電極部と電気的に接続する半導体素子の実装
構造において、 第１の基板の一主面上に形成され、且つ半導体
素子表面の電極部と電気的に接続された第１の電
極部と、 前記第１の基板の裏面上に形成され、且つ前記
第１の基板に設けられたスルーホールを用いて前
記第１の電極部と電気的接続された第２の電極部
と、 第２の基板の一主面上に形成され、且つ前記第
２の電極部と電気的に接続された第３の電極部と
を備えてなることを特徴とする半導体素子の実装
構造。 ２ 上記第１の基板はフレキシブルプリント基板
であることを特徴とする実用新案登録請求の範囲
第１項記載の半導体素子の実装構造。[Claims for Utility Model Registration] 1. In a mounting structure for a semiconductor device in which an electrode portion on the surface of the semiconductor device is electrically connected to an electrode portion formed on a holding substrate, the semiconductor device is formed on one main surface of a first substrate, and a first electrode portion electrically connected to an electrode portion on a surface of the semiconductor element; and a through hole formed on the back surface of the first substrate and provided in the first substrate to a second electrode portion electrically connected to the first electrode portion; and a third electrode portion formed on one main surface of the second substrate and electrically connected to the second electrode portion. A semiconductor element mounting structure characterized by comprising: 2. The semiconductor element mounting structure according to claim 1, wherein the first substrate is a flexible printed circuit board.
JP1987060505U 1987-04-20 1987-04-20 Pending JPS63167733U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987060505U JPS63167733U (en) 1987-04-20 1987-04-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987060505U JPS63167733U (en) 1987-04-20 1987-04-20

Publications (1)

Publication Number Publication Date
JPS63167733U true JPS63167733U (en) 1988-11-01

Family

ID=30892972

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987060505U Pending JPS63167733U (en) 1987-04-20 1987-04-20

Country Status (1)

Country Link
JP (1) JPS63167733U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0311646A (en) * 1989-06-08 1991-01-18 Shinko Electric Ind Co Ltd Film carrier for tab use
JPH08124967A (en) * 1994-10-21 1996-05-17 Nec Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0311646A (en) * 1989-06-08 1991-01-18 Shinko Electric Ind Co Ltd Film carrier for tab use
JPH08124967A (en) * 1994-10-21 1996-05-17 Nec Corp Semiconductor device

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