JPS62134261U - - Google Patents
Info
- Publication number
- JPS62134261U JPS62134261U JP1387786U JP1387786U JPS62134261U JP S62134261 U JPS62134261 U JP S62134261U JP 1387786 U JP1387786 U JP 1387786U JP 1387786 U JP1387786 U JP 1387786U JP S62134261 U JPS62134261 U JP S62134261U
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- active layer
- sides
- semiconductor active
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000605 extraction Methods 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 5
- 241000270730 Alligator mississippiensis Species 0.000 claims 1
- 230000009977 dual effect Effects 0.000 claims 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Description
第１図はデユアルゲート電界効果トランジスタ
の基本構造図、第２図ａおよびｂは本考案の一実
施例を示すそれぞれ平面図およびＡ―Ａ′方向の
断面図、第３図ａおよびｂは本考案の他の実施例
を示すそれぞれ平面図およびＡ―Ａ′方向の断面
図である。
１，１′……半絶縁性ガリウムヒ素基板、２，
２′……ｎ型ガリウムヒ素活性層、３，３′，３
″……ソース電極パターン、４，４′，４″……
ドレイン電極パターン、５０……第一ゲート電極
パターン、６０……第二ゲート電極パターン、５
，６′……ゲート電極取り出し部、５″，６″…
…ゲート電極部。
Fig. 1 is a basic structural diagram of a dual-gate field effect transistor, Fig. 2 a and b are a plan view and a cross-sectional view taken along the line A-A', respectively, showing an embodiment of the present invention, and Fig. 3 a and b are main views of the present invention. FIG. 7 is a plan view and a sectional view taken along the line A-A', respectively, showing other embodiments of the invention. 1,1'...Semi-insulating gallium arsenide substrate, 2,
2'...n-type gallium arsenide active layer, 3, 3', 3
″... Source electrode pattern, 4, 4', 4″...
Drain electrode pattern, 50...first gate electrode pattern, 60...second gate electrode pattern, 5
, 6'...Gate electrode extraction part, 5'', 6''...
...Gate electrode section.
Claims (1)
と、この活性層の内部に形成され第１および第２
の幅広部とこれら幅広部を連結する幅狭部を有す
る開孔と、この開孔の前記幅狭部を横切つて前記
半導体活性層に接しかつ互いに平行して延びる二
つの独立したゲート電極部と、一方のゲート電極
部の中央部から導出され前記開孔の前記第１の幅
広部内に形成された第１のゲート電極取り出し部
と、他方のゲート電極部の中央部から前記第１の
ゲート電極取り出し部とは反対方向に導出され前
記開孔の前記第２の幅広部内に形成された第２の
ゲート電極取り出し部と、前記第１のゲート電極
取り出し部の両側において前記一方のゲート電極
部に対向するように前記半導体活性層上に設けら
れたソース電極と、前記第２のゲート電極取り出
し部の両側において前記他方のゲート電極部に対
向するよう前記半導体活性層上に設けられたドレ
イン電極とを有することを特徴とするデユアルゲ
ート電界効果トランジスタ。 (2) 前記第１のゲート電極取り出し部の両側に
おいて前記一方のゲート電極部に対向するように
設けられたソース電極は互いに連続し、前記第２
のゲート電極取り出し部の両側において前記他方
のゲート電極部に対向するように設けられたドレ
イン電極は互いに連続することを特徴とする実用
新案登録請求の範囲第１項記載のデユアルゲート
電界効果トランジスタ。 (3) 前記第１のゲート電極取り出し部の両側に
おいて前記一方のゲート電極部に対向するように
設けられたソース電極は互いに独立し、前記第２
のゲート電極取り出し部の両側において前記他方
のゲート電極部に対向するように設けられたドレ
イン電極は互いに独立していることを特徴とする
実用新案登録請求の範囲第１項記載のデユアルゲ
ータ電界効果トランジスタ。[Claims for Utility Model Registration] (1) A semiconductor active layer formed on a semi-insulating substrate, and a first and second semiconductor active layer formed inside this active layer.
an opening having a wide part and a narrow part connecting the wide parts, and two independent gate electrode parts extending parallel to each other and in contact with the semiconductor active layer across the narrow part of the opening. and a first gate electrode lead-out portion led out from the central portion of one gate electrode portion and formed within the first wide portion of the opening, and a first gate electrode lead-out portion led out from the central portion of the other gate electrode portion a second gate electrode lead-out part led out in the opposite direction to the electrode lead-out part and formed in the second wide part of the opening; and the one gate electrode part on both sides of the first gate electrode lead-out part. a source electrode provided on the semiconductor active layer to face the second gate electrode, and a drain electrode provided on the semiconductor active layer to face the other gate electrode portion on both sides of the second gate electrode extraction portion. A dual-gate field effect transistor comprising: (2) The source electrodes provided on both sides of the first gate electrode extraction portion so as to face the one gate electrode portion are continuous with each other, and
2. The dual-gate field effect transistor according to claim 1, wherein the drain electrodes provided opposite the other gate electrode portion on both sides of the gate electrode lead-out portion are continuous with each other. (3) The source electrodes provided on both sides of the first gate electrode extraction portion so as to face the one gate electrode portion are independent from each other, and
The dual gator field effect transistor according to claim 1, wherein the drain electrodes provided opposite to the other gate electrode portion on both sides of the gate electrode extraction portion are independent from each other. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1387786U JPS62134261U (en) | 1986-01-31 | 1986-01-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1387786U JPS62134261U (en) | 1986-01-31 | 1986-01-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62134261U true JPS62134261U (en) | 1987-08-24 |
Family
ID=30803345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1387786U Pending JPS62134261U (en) | 1986-01-31 | 1986-01-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62134261U (en) |
-
1986
- 1986-01-31 JP JP1387786U patent/JPS62134261U/ja active Pending