JPS6178132A - 集積回路装置 - Google Patents

集積回路装置

Info

Publication number
JPS6178132A
JPS6178132A JP59200109A JP20010984A JPS6178132A JP S6178132 A JPS6178132 A JP S6178132A JP 59200109 A JP59200109 A JP 59200109A JP 20010984 A JP20010984 A JP 20010984A JP S6178132 A JPS6178132 A JP S6178132A
Authority
JP
Japan
Prior art keywords
chip
substrate
input
wiring patterns
coating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59200109A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0363813B2 (cg-RX-API-DMAC10.html
Inventor
Takeshi Miyagi
武史 宮城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59200109A priority Critical patent/JPS6178132A/ja
Publication of JPS6178132A publication Critical patent/JPS6178132A/ja
Publication of JPH0363813B2 publication Critical patent/JPH0363813B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10W70/093—
    • H10W70/60—
    • H10W70/6523—
    • H10W70/654—
    • H10W90/00—

Landscapes

  • Wire Bonding (AREA)
JP59200109A 1984-09-25 1984-09-25 集積回路装置 Granted JPS6178132A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59200109A JPS6178132A (ja) 1984-09-25 1984-09-25 集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59200109A JPS6178132A (ja) 1984-09-25 1984-09-25 集積回路装置

Publications (2)

Publication Number Publication Date
JPS6178132A true JPS6178132A (ja) 1986-04-21
JPH0363813B2 JPH0363813B2 (cg-RX-API-DMAC10.html) 1991-10-02

Family

ID=16418975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59200109A Granted JPS6178132A (ja) 1984-09-25 1984-09-25 集積回路装置

Country Status (1)

Country Link
JP (1) JPS6178132A (cg-RX-API-DMAC10.html)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008124476A (ja) * 2006-11-14 2008-05-29 Samsung Electronics Co Ltd 半導体パッケージ及び該製造方法
WO2010087336A1 (ja) * 2009-01-27 2010-08-05 パナソニック電工株式会社 半導体チップの実装方法、該方法を用いて得られた半導体装置及び半導体チップの接続方法、並びに、表面に配線が設けられた立体構造物及びその製法
JP2011512691A (ja) * 2008-02-19 2011-04-21 ヴァーティカル・サーキツツ・インコーポレーテッド 平坦なリードレス・パッケージおよび積み重ねられたリードレス・パッケージ・アセンブリ
US9070393B2 (en) 2009-01-27 2015-06-30 Panasonic Corporation Three-dimensional structure in which wiring is provided on its surface
US9082438B2 (en) 2008-12-02 2015-07-14 Panasonic Corporation Three-dimensional structure for wiring formation

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008124476A (ja) * 2006-11-14 2008-05-29 Samsung Electronics Co Ltd 半導体パッケージ及び該製造方法
JP2011512691A (ja) * 2008-02-19 2011-04-21 ヴァーティカル・サーキツツ・インコーポレーテッド 平坦なリードレス・パッケージおよび積み重ねられたリードレス・パッケージ・アセンブリ
US9082438B2 (en) 2008-12-02 2015-07-14 Panasonic Corporation Three-dimensional structure for wiring formation
WO2010087336A1 (ja) * 2009-01-27 2010-08-05 パナソニック電工株式会社 半導体チップの実装方法、該方法を用いて得られた半導体装置及び半導体チップの接続方法、並びに、表面に配線が設けられた立体構造物及びその製法
JPWO2010087336A1 (ja) * 2009-01-27 2012-08-02 パナソニック株式会社 半導体チップの実装方法、該方法を用いて得られた半導体装置及び半導体チップの接続方法、並びに、表面に配線が設けられた立体構造物及びその製法
US8482137B2 (en) 2009-01-27 2013-07-09 Panasonic Corporation Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same
US8759148B2 (en) 2009-01-27 2014-06-24 Panasonic Corporation Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same
US8901728B2 (en) 2009-01-27 2014-12-02 Panasonic Corporation Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same
US9070393B2 (en) 2009-01-27 2015-06-30 Panasonic Corporation Three-dimensional structure in which wiring is provided on its surface
US9795033B2 (en) 2009-01-27 2017-10-17 Panasonic Corporation Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same

Also Published As

Publication number Publication date
JPH0363813B2 (cg-RX-API-DMAC10.html) 1991-10-02

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