JPS617648A - 集積回路用容器 - Google Patents

集積回路用容器

Info

Publication number
JPS617648A
JPS617648A JP59128706A JP12870684A JPS617648A JP S617648 A JPS617648 A JP S617648A JP 59128706 A JP59128706 A JP 59128706A JP 12870684 A JP12870684 A JP 12870684A JP S617648 A JPS617648 A JP S617648A
Authority
JP
Japan
Prior art keywords
bonding
height
container
vessel
lead wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59128706A
Other languages
English (en)
Inventor
Hiroyuki Sato
博幸 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59128706A priority Critical patent/JPS617648A/ja
Publication of JPS617648A publication Critical patent/JPS617648A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4801—Structure
    • H01L2224/48011—Length
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 周波数が高周波の領域においては半導体素子の配線に使
用されるボンディング線も等測的にインダクターとなり
、半導体素子の特性に影響を与える。本発明はこのボン
ディング線の長さが短かくてすむような容器構造とした
もめで、不要インダクタンスを減少させることができ、
マイクロ波集積回路用容器として利用できる。また、こ
の容器平面部に突起部を有し、半導体素子を取り付ける
ときの位置付けとしても利用できる。
〔従愈丘術〕
従来は第２図に示すように、半導体素子１のポンティン
グパッド面と半導体素子が取り付けられる容器の平面部
３．外部リード線端子のボンディングが接続される面２
の高さが異なっていたために、ボンディング線４の長さ
が必要以上に長くなり、インダクタンスを不要に増やし
ていた欠点を持っている。また、半導体素子を取り付け
る際。
容器の平面部３ＶＣはっきシとした位置付けとなる目印
がないので、均一に素子の取り付けをすることができな
いという欠点がある。
〔発明が解決しようとする問題点〕
本発明の目的は従来の容器構造よりボンディング線の長
さを短かくすることができ、不要インダクタンスを減少
させたマイクロ波集積回路用容器を提供することにある
。
〔問題を解決するための手段〕
本発明のマイクロ波集積回路用容器は不要インダクタン
スの原因となるボンディング線の長さを短かくするため
に、半導体素子のボンディングパッド面と半導体素子が
取り付けられる容器の平面部の高さが同一になるように
突起部を設け、かつ外部リード線端子のボンディングが
される面の高さも半導体素子のボンディングパッド面の
高さと同一になるようにして各ボンディング線接続面間
の実効的な距離を短かくしている。
〔作用〕
本発明の集積回路用容器はボンディング線は全て同じ高
さでボンディングがなされるので、従来の容器構造よシ
ポンディング線を短かくすることができ、不要なインダ
クタンスを減少できる。また容器底面の突起が半導体素
子数シ付けの時の目印ともなるので同じ位置に取り付け
できる。
〔実施例〕 次に５図面を参照して本発明をよシ詳細に説明する。
第１１Ｃ本発明の１実施例として、マイクロ波集積回路
用容器の断面図を示す。これは半導体素子１のボンディ
ングパッド面と半導体素子が取り付けられる容器の平面
部３の高さが同一になるように突起部５を設け、かつ外
部リード線端子のボンディングが接続される面２の高さ
も半導体素子のボンディングパッド面の高さと同一にな
るようにして各ボンディング線接続面間の実効的な距離
を短かくした構造である。突起部５は半導体素子を取り
付ける際の位置付けとな９半導体素子の正確な取り付け
が可能となる。更に容器接地の場合。
ボンディング線のボンディングすべき部分は同一平面に
あるのでボンディング線長を短かくできる。
このように、外部リード線端子の接続面２も半導体素子
のポンディジグパッド面と同一にしであるので、多少な
シともポンディン／″線長を短かくできる。
〔発明の効果〕
本発明のマイクロ波集積回路用容器は従来の容器構造よ
シボンディング線の長さを短かくすることができ、不要
インダクタンスを減少させられるとともに素子数シ付け
の位置決めが容易になる効果がある。
【図面の簡単な説明】
第１図は本発明の一実施例による容器の構造を示す断面
図である。 第２図は従来の容器の構造を示す断面図である。 １・・・・・・半導体素子、２・・・・・・外部リード
線端子面。 ３・・・・・・容器平面部、４・・・・・・ボンディン
グ線、５・・・・・・突起部。 叉　　　・ 竿　２　図 挙　ｌｒｌ！Ｊ

Claims (1)

    【特許請求の範囲】
  1. 半導体素子を収容する容器の底面に半導体素子のボンデ
    ィングパッド面と高さが同一になるような突起部を有し
    、かつ該容器に取り付けられた外部リード線端子のボン
    ディングがなされる面の高さも前記半導体素子のボンデ
    ィングパッド面の高さと同一となっていることを特徴と
    する集積回路用容器。
JP59128706A 1984-06-22 1984-06-22 集積回路用容器 Pending JPS617648A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59128706A JPS617648A (ja) 1984-06-22 1984-06-22 集積回路用容器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59128706A JPS617648A (ja) 1984-06-22 1984-06-22 集積回路用容器

Publications (1)

Publication Number Publication Date
JPS617648A true JPS617648A (ja) 1986-01-14

Family

ID=14991411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59128706A Pending JPS617648A (ja) 1984-06-22 1984-06-22 集積回路用容器

Country Status (1)

Country Link
JP (1) JPS617648A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03386A (ja) * 1989-05-25 1991-01-07 Fukuda:Kk 電磁弁
WO2009063721A1 (ja) * 2007-11-16 2009-05-22 Toyota Jidosha Kabushiki Kaisha 半導体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03386A (ja) * 1989-05-25 1991-01-07 Fukuda:Kk 電磁弁
WO2009063721A1 (ja) * 2007-11-16 2009-05-22 Toyota Jidosha Kabushiki Kaisha 半導体装置
JP2009124048A (ja) * 2007-11-16 2009-06-04 Toyota Motor Corp 半導体装置
US8674511B2 (en) 2007-11-16 2014-03-18 Toyota Jidosha Kabushiki Kaisha Method of forming a semiconductor device with a contact pad on a sloped silicon dioxide surface

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