JPS617646A - ハイブリツドｉｃの変更方法 - Google Patents

ハイブリツドｉｃの変更方法

Info

Publication number
JPS617646A
JPS617646A JP12826184A JP12826184A JPS617646A JP S617646 A JPS617646 A JP S617646A JP 12826184 A JP12826184 A JP 12826184A JP 12826184 A JP12826184 A JP 12826184A JP S617646 A JPS617646 A JP S617646A
Authority
JP
Japan
Prior art keywords
chip
potential
pad
die pad
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12826184A
Other languages
English (en)
Japanese (ja)
Other versions
JPH022291B2 (cs
Inventor
Yoshitaka Fukuoka
義孝 福岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP12826184A priority Critical patent/JPS617646A/ja
Publication of JPS617646A publication Critical patent/JPS617646A/ja
Publication of JPH022291B2 publication Critical patent/JPH022291B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5382—Adaptable interconnections, e.g. for engineering changes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/4827—Materials
    • H01L23/4828—Conductive organic material or pastes, e.g. conductive adhesives, inks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Die Bonding (AREA)
JP12826184A 1984-06-21 1984-06-21 ハイブリツドｉｃの変更方法 Granted JPS617646A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12826184A JPS617646A (ja) 1984-06-21 1984-06-21 ハイブリツドｉｃの変更方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12826184A JPS617646A (ja) 1984-06-21 1984-06-21 ハイブリツドｉｃの変更方法

Publications (2)

Publication Number Publication Date
JPS617646A true JPS617646A (ja) 1986-01-14
JPH022291B2 JPH022291B2 (cs) 1990-01-17

Family

ID=14980470

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12826184A Granted JPS617646A (ja) 1984-06-21 1984-06-21 ハイブリツドｉｃの変更方法

Country Status (1)

Country Link
JP (1) JPS617646A (cs)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6906411B1 (en) 2000-06-29 2005-06-14 Mitsubishi Denki Kabushiki Kaisha Multilayer substrate module and portable wireless terminal
JP2011099505A (ja) * 2009-11-05 2011-05-19 Tsubakimoto Chain Co 噛合チェーン

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0558354A (ja) * 1991-08-29 1993-03-09 Iseki & Co Ltd クロ−ラ式走行装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6906411B1 (en) 2000-06-29 2005-06-14 Mitsubishi Denki Kabushiki Kaisha Multilayer substrate module and portable wireless terminal
JP2011099505A (ja) * 2009-11-05 2011-05-19 Tsubakimoto Chain Co 噛合チェーン

Also Published As

Publication number Publication date
JPH022291B2 (cs) 1990-01-17

Similar Documents

Publication Publication Date Title
CA1143862A (en) High performance semiconductor package assembly
US20040140559A1 (en) Electronic device configured as a multichip module, leadframe, panel with leadframe positions, and method for producing the electronic device
US4466181A (en) Method for mounting conjoined devices
JPH0227838B2 (cs)
JP2001168233A (ja) 多重回線グリッド・アレイ・パッケージ
US6101098A (en) Structure and method for mounting an electric part
JPS617646A (ja) ハイブリツドｉｃの変更方法
JPS60105269A (ja) ハイブリツド回路の製造方法
JPH0365662B2 (cs)
JPS617657A (ja) マルチチツプパツケ−ジ
US6020631A (en) Method and apparatus for connecting a bondwire to a bondring near a via
JP2837521B2 (ja) 半導体集積回路装置およびその配線変更方法
JPH0517709B2 (cs)
KR19980063740A (ko) 몰딩된 패키지용 다층 리드프레임
JPH06268012A (ja) 半導体集積回路装置
JPS617658A (ja) ハイブリツドｉｃの接続変更方法
JPS62134939A (ja) 混成集積回路
JPH01150332A (ja) プリント回路基板
JPS60218864A (ja) 電子部品パツケ−ジの実装方法、及び、電子部品パツケ−ジの構造
JP2592869Y2 (ja) 混成ｉｃ装置
JPH08186196A (ja) 半導体装置の実装構造
JPH05343604A (ja) ハイブリッドｉｃとその製造方法
JP3182943B2 (ja) ハイブリッドｉｃ
JPH07111306A (ja) 半導体装置
JPH04359464A (ja) 半導体装置