JPS6152509B2 - - Google Patents

Info

Publication number
JPS6152509B2
JPS6152509B2 JP19592681A JP19592681A JPS6152509B2 JP S6152509 B2 JPS6152509 B2 JP S6152509B2 JP 19592681 A JP19592681 A JP 19592681A JP 19592681 A JP19592681 A JP 19592681A JP S6152509 B2 JPS6152509 B2 JP S6152509B2
Authority
JP
Japan
Prior art keywords
processor
transaction
common bus
buffer
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP19592681A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5897761A (ja
Inventor
Atsushi Sugano
Kenichi Ueda
Kunio Pponda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56195926A priority Critical patent/JPS5897761A/ja
Publication of JPS5897761A publication Critical patent/JPS5897761A/ja
Publication of JPS6152509B2 publication Critical patent/JPS6152509B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP56195926A 1981-12-04 1981-12-04 仮想プロセツサ方式 Granted JPS5897761A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56195926A JPS5897761A (ja) 1981-12-04 1981-12-04 仮想プロセツサ方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56195926A JPS5897761A (ja) 1981-12-04 1981-12-04 仮想プロセツサ方式

Publications (2)

Publication Number Publication Date
JPS5897761A JPS5897761A (ja) 1983-06-10
JPS6152509B2 true JPS6152509B2 (enExample) 1986-11-13

Family

ID=16349272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56195926A Granted JPS5897761A (ja) 1981-12-04 1981-12-04 仮想プロセツサ方式

Country Status (1)

Country Link
JP (1) JPS5897761A (enExample)

Also Published As

Publication number Publication date
JPS5897761A (ja) 1983-06-10

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