JPS6150334B2 - - Google Patents

Info

Publication number
JPS6150334B2
JPS6150334B2 JP20298481A JP20298481A JPS6150334B2 JP S6150334 B2 JPS6150334 B2 JP S6150334B2 JP 20298481 A JP20298481 A JP 20298481A JP 20298481 A JP20298481 A JP 20298481A JP S6150334 B2 JPS6150334 B2 JP S6150334B2
Authority
JP
Japan
Prior art keywords
bit
addition
data
bits
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP20298481A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58105349A (ja
Inventor
Yasuhiro Kuroda
Toshiro Nakazuru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20298481A priority Critical patent/JPS58105349A/ja
Publication of JPS58105349A publication Critical patent/JPS58105349A/ja
Publication of JPS6150334B2 publication Critical patent/JPS6150334B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
JP20298481A 1981-12-16 1981-12-16 信号処理用加減算回路 Granted JPS58105349A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20298481A JPS58105349A (ja) 1981-12-16 1981-12-16 信号処理用加減算回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20298481A JPS58105349A (ja) 1981-12-16 1981-12-16 信号処理用加減算回路

Publications (2)

Publication Number Publication Date
JPS58105349A JPS58105349A (ja) 1983-06-23
JPS6150334B2 true JPS6150334B2 (enExample) 1986-11-04

Family

ID=16466400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20298481A Granted JPS58105349A (ja) 1981-12-16 1981-12-16 信号処理用加減算回路

Country Status (1)

Country Link
JP (1) JPS58105349A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59151236A (ja) * 1983-02-17 1984-08-29 Sanyo Electric Co Ltd デイジタル加減算回路

Also Published As

Publication number Publication date
JPS58105349A (ja) 1983-06-23

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