JPS6150334B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an addition/subtraction circuit for signal processing that is suitable for cases in which data series are accumulated but there is a limit to the output data width. If you want to know the average trend of time series data,
Sometimes a method is used in which data that is input sequentially is simply added. If the time series data changes between positive and negative, the sum will fall within a certain range even when added, and the sum will indicate the average fluctuation tendency of the time series data. By the way, it is normal for addition and subtraction circuits to have a limit on the width of data that they can handle.
If the sum is within a certain range and exceeds the data width, it is necessary to compress the output data width to a predetermined width by scaling or the like. This is the sum S of signed n-bit inputs A and B (this is n+
(which can be 1 bit) is shifted to the right by 1 bit, thereby discarding the least significant bit.
This result is (A+B)/2 or (A-B)/2
However, the data width returns to n bits. (A+
B)/2, that is, it is averaged, so the next data C, D, ... are not simply added to this, but are also (C
+D)/2 and add it to (A+B)/2. However, if such addition and subtraction are performed simply by adding and subtracting ordinary signed n bits, followed by a 1-bit shift to the right, correct results will not be obtained if an overflow occurs in the addition or subtraction. For example, signed binary data A = 1110 is -2 in decimal, B = 0111 is
This is 7 in decimal, but when these are added, the result S is S=10101, and with a 1-bit right shift, it becomes 1010, which is -6 in decimal and does not give the correct result 5. Therefore, it is necessary to expand the input n bits to (n+1) bits, add them, and shift the result to the right by 1 bit as shown below.

[Table] Here, A ₀ and B ₀ are sign bits and extended bits, A ₁ to A _o and B ₁ to B _o are each digit of A and B, and S ₀ and S ₁ to _{S o} are the sum. Of the sign bits and digits of S, the least significant digit S _o is discarded by scaling. In the above example, A=1110
is 11110, B=0111 is transformed to 00111, and the sum S=
Find 00101 and shift it to the right by 1 bit to make it 0010.
This is decimal 2, which is approximately 1/2 of the correct answer of 5. However, in this method, it is necessary to increase both the addend and the summand by 1 bit, which increases the amount of hardware.
The present invention aims to improve this point, and is characterized by a signal processing addition/subtraction circuit that performs addition and subtraction of signed n-bit input data A and B and generates the same n-bit output data S by scaling. A circuit for inverting the sign bits of input data A and B, a circuit for adding the n-bit input data A and B with the sign bits inverted, and a circuit for inverting the sign bits and extracting the upper n bits from the addition result. The goal is to prepare for In the present invention, signed n-bit input data A, B
The sign bit of is inverted and added. That is,

[Table] _-
S ₀ S ₁ S ₂ S ₃ ......S _o-1 S _o
shall be. This result is the same as equation (1) except for the sign bit, but the sign bit ₀ is inverted. Therefore, it is further inverted and returned to its original state. That is, the formula is as follows.

[Table] The method of equation (3) was born from the idea of converting the input into an offset binary form, converting signed values to unsigned values, adding them, and outputting the inversely converted result. . To explain these in terms of hardware, FIG. 1 shows the conventional system, and FIG. 2 shows the system of the present invention. The same applies to the full adders, both of which use 4-bit adders. In these figures, 10 is a 4-bit adder,
12 and 14 are addends and 4-bit registers in which the summands are stored; 16 and 18 are exclusive OR circuits; 20 and 2
2 and 24 are inverter or knot circuits, C' is a carry input from the lower stage of the 4-bit adder, and C is a carry output to the upper stage of the 4-bit adder.
In FIG. 1, exclusive OR circuits 16 and 18 perform the function of 1-bit expansion. To explain with a specific example, if the above A=1110 and B=0111, the adder output C, S ₁ ,
S ₂ , S ₃ , S ₃ = 10101, EXOR16 output is 1,
The output of EXOR18 is 0, so the addition outputs S ₀ , S ₁ ,
S ₂ , S ₃ , S ₄ =0010, that is, +5 in decimal. In this example, A=-2 and B=7, so S=A+B=5
is correct. The upper 4 bits S ₀ to _{S 3} are extracted. In FIG. 2, sign bits A ₁ and B ₁ are inverted by inverters 20 and 22, and the carry output C of the sum is inverted to perform "1" extension, and the calculation of equation (3) is performed. Note circuits 20 and 22 in FIG. 2 can be omitted by using the outputs of the registers 12 and 14 when they are comprised of a group of flip-flop circuits. An example of this is shown in FIG. As is clear from a comparison with FIG. 1, the system of the present invention can save hardware. Since subtraction is 2's complement addition, the process is the same as addition. Note that addition of a sign bit of 1, that is, a negative number, is subtraction, but here it is assumed that data B is a positive number and is subtracted. FIG. 4 shows a conventional example in which the B digits _B1 to _B4 are inverted by an inverter 26 and "1" is input to the carry terminal C'.
is added to form a two's complement number. In other words, these inverter 26 and carry "1" create signed data indicating -B. Once such data is created, the rest is the same as in Figure 1. FIG. 5 shows the case of the present invention, in which digits A ₁ ,
B ₁ and C are inverted, but since B ₁ cancels out the inversion for two's complement conversion, no inverter is used. In the cases of FIGS. 4 and 5 as well, when the input register is composed of a group of flip-flops, the inverter can be omitted by using the output thereof. Note that the signal processing addition/subtraction circuit may perform overflow processing instead of scaling. This is something like this: That is, if the addition result S of n-bit data A and B is set to n bits, overflow may occur. In this case, if the correct addition result is positive, it outputs the maximum number that can be represented, 01111111 if it is an 8-bit output, and if it is negative, it outputs the minimum number that can be represented, in this example, 10000000. In the present invention, overflow can be detected as follows. That is, the result of addition of (n+1) bits is obtained and the following judgment is made using _S0 and _S1 .

[Table] When S ₀ =S ₁ , the above processing is performed, and when S ₀ =S ₁ , the lower n bits S ₁ to _{S o} are output as they are. As explained above, according to the present invention, signed n
There is an advantage that the hardware of the adder/subtracter circuit that adds bit input data and outputs the same n-bit data can be saved.

[Brief explanation of the drawing]

1 and 4 are block diagrams showing a conventional example, and FIGS. 2, 3, and 5 are block diagrams showing an embodiment of the present invention. In the drawing, 12 and 14 are registers that store input data A and B, 20 and 22 are not circuits that invert the sign bits, 10 is a 4-bit adder, and 24
is a not circuit that inverts the sign bit of the addition result.

Claims (1)

[Claims] 1. In a signal processing addition/subtraction circuit that performs addition and subtraction on signed n-bit input data A and B and generates the same n-bit output data S by scaling, the sign bits of input data A and B are inverted. A signal processing device comprising: a circuit for adding n-bit input data A and B with sign bits inverted; and a circuit for inverting the sign bits and extracting the upper n bits from the addition result. Addition/subtraction circuit.