JP2870018B2 - Product-sum operation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a product-sum operation circuit used for digital processing of images and sounds, and more particularly, to a method suitable for LSI implementation.

[Summary of the Invention] The present invention relates to a multiply-accumulate operation circuit, by performing an operation using (x _nm −1/2) for a value x _{nm of} each digit, thereby simplifying the configuration and achieving a good operation result. Is obtained.

[Conventional technology]

For example, N-sum product operation When Cn is a coefficient and Xn is data, Xn is an M-bit binary number Xn = ( _xnM , _xnM-1 ‥‥ _xn1 ) ‥‥ (2) x is 0 or 1 _xnM : MSB _xn1 : Assuming LSB, if Xn is represented by 2's complement, the value of Y is Or It can be expressed as.

Here, when Cn is a fixed coefficient, the equation (3 ′) is
As shown in the figure, hardware can be used. That is, in the figure, N pieces of data (X ₁ , X ₂ ‥‥ X _N ) are respectively supplied to M-bit input terminals (1 ₁ ) to (1 _N ). The data supplied to these input terminals (1 ₁ ) to (1 _N ) are supplied to parallel-to-serial conversion circuits (2 ₁ ) to (2 _N ), respectively, and the serially converted data is extracted for each digit. Is done.

The fetched data (N bits) is a read-only memory (ROM) having an N-bit input (address).
It is supplied to (3). N input to this ROM (3)
For each digit of data, Is written. That is, this value is a value obtained by adding only the coefficient (Cn) of the term whose bit data (x _nm ) of the N term is “1”. The number of bits of this value is an arbitrary number of bits (N ') according to the calculation accuracy and the like.

The output (N 'bit) of the ROM (3) is supplied to an adder / subtracter (4) of N' bits, for example, a 2's complement. The output of the adder / subtractor (4) is supplied to the adder / subtractor (4) via a data shift circuit (5) (÷ 2: one digit down), a one-clock delay circuit (6) and an AND circuit (7). Thus, the cumulative addition in which the digits are sequentially shifted is performed.

And in this circuit, the other signals S ₁ of the AND circuit (7) is the input of ROM (3) is the only all "0" when the LSB (m = 1). The operation control signal S ₂ of the adder-subtracter (4) is adapted input of ROM (3) is subtracted only when the MSB (m = M).

As a result, the above equation (3 ') is executed in this circuit, and when the input data of the ROM (3) is MSB (m = M), the operation result (Y) is taken out to the output terminal (8).

Note as an example of calculations, when performing product-sum operation, for example, four paragraphs, when _{C 1 = 0.25 C 2 = 0.125} C 3 = -0.375 C 4 = -0.5, the following table contents of ROM (3) It becomes as shown in.

Then, the actual calculation is performed as follows.

Here, ^x is a sign extension in the calculation of the 2's complement, and the same as the sign bit of the calculation result is added to the higher order.

Therefore, this circuit is particularly effective when the coefficient is fixed. The influence of the data word length on the hardware scale is small, and the input of long word length data can be easily handled. It is also easy to perform a highly accurate calculation by increasing the coefficient word length. Since there is only one ROM and one adder / subtractor in the critical path, high-speed operation is possible. This is extremely effective for applications where N is relatively small (approximately 4 to 12), in particular, cosine transform for compressing image data, matrix calculation in fast Fourier transform that can calculate by dividing input, and the like.

[Problems to be solved by the invention]

However, in the above-described circuit, since only one subtraction is required in M cumulative additions, there is a circuit that is effective only once in M when the data word length is large, that is, when M is large. There are hardware inefficiencies. This inefficiency is further increased when the coefficient word length is increased. There is also a slight disadvantage in the critical path. In particular, in the case of a special LSI design or the like where extremely high calculation accuracy is required, there is a possibility that both the hardware size and the operation speed may become obstacles.

The present application has been made in view of such points.

[Means for solving the problem]

The present invention N is the number of terms. Cn is a coefficient. Xn is a product-sum operation circuit for obtaining data. In an input means (input terminals (1 ₁ ) to (1 ₁ ) to (1 ₁ ) to (X ₁ ) to which a code Xn = [X _nm ] obtained by binarizing the above Xn by offset binary is input. _N ) and
The above code for each digit Code conversion means (ROM (3)) for converting the converted code into Accumulator (4X) for sequentially shifting the digit and performing the operation with the initial value (switch (7X)) and output means (output terminal (8)) for outputting the result of the accumulation. It is.

[Action]

According to this, the input data is set as an offset binary code, and for each digit value x _nm (x _nm −1/2)
, The exceptional processing during the calculation is eliminated, and the circuit configuration can be simplified to obtain a good calculation result.

〔Example〕

In FIG. 1, in this case, N data (X ₁ , X ₂
{X _N ) is a code X _n = [x _nm ] _{m = 1} to M binarized by M-bit offset binary, and supplied to the input terminals (1 ₁ ) to (1 _N) .

The contents of the ROM (3) correspond to the input N-bit data of each digit. It is said. That is, this value is the coefficient (Cn) of the term in which the bit data (x _nm ) of the digit in the N term is “1”.
Is multiplied by 、, and the value obtained by multiplying the coefficient (Cn) of the term whose data (x _nm ) is “0” by −1/2 is summed. The number of bits of this value is an arbitrary number of bits (N ') according to the calculation accuracy and the like.

Further, an adder (4X) is provided instead of the conventional adder / subtractor (4), and a signal S ₁ is provided instead of the AND circuit (7).
Is provided with a switch (7X) that is switched only when the input of the ROM (3) is LSB (m = 1), and the initial value is set through this switch (7X). Is supplied. Others are the same as the circuits described in the prior art.

That is, in this circuit, if the binary number of the equation (2) described in the above-mentioned conventional technique is an offset binary code, the equation (3 ') is It is expressed as Therefore, when this equation (4) is transformed, Becomes

Therefore, in the above-described circuit, the expression (5) is realized, and the product-sum operation of the N term shown in the expression (1) Is executed.

In this circuit, when performing the same calculation as described in the above conventional example, first, the contents of the ROM (3) are as shown in the following table.

The actual calculation is performed as follows.

That is, in this circuit, it is possible to obtain the same accurate operation result as described in the conventional art.

Therefore, in the above-mentioned circuit, the same accurate calculation result as the conventional one is obtained, and the conventional adder / subtracter is replaced with an adder. Becomes It is also advantageous in terms of operating speed. Further, the exceptional processing in the above-described circuit is only the setting of the initial value, and the control circuit and the like when performing the operation can be simplified.

Here, the set of initial values is specifically, for example, the second
As shown in the figure, a signal "1" which becomes "1" only when the input of the ROM (3) is LSB (m = 1) is used, and the bit whose initial value is "1" is shown in FIG. The signal ▼ is supplied to the feedback signal via the OR circuit as described above, and the bit having the initial value “0” is added to the signal よ う as shown in FIG.
The signal obtained by inverting ▼ by the inverter is supplied to the feedback signal via the AND circuit. This allows ROM
When the input of (3) is LSB, an arbitrary initial value is added to the adder (4
X).

Alternatively, the initial value set is set to all "0" by using the AND circuit as in the past, and all "0" data is supplied to the input before the LSB input is supplied to the ROM (3).
The output of the ROM (3) may be supplied to the adder (4X).

Thus, according to the above-described circuit, the input data is set as the offset binary code, and the operation is performed using (x _nm −1/2) for the value x _{nm of} each digit, so that the exceptional value during the operation is obtained. The processing is eliminated, and the circuit configuration can be simplified to obtain a good calculation result.

Therefore, the above-described circuit is effective in performing high-speed and high-accuracy calculations, and is particularly effective when performing cosine transform / inverse transform by matrix calculation in image data compression or the like.

In the above circuit, by using (x _{nm − −} ) for the value x _{nm of} each digit as an offset binary code, for example, a binary number Where x _m is the inverse of x _m Becomes This means that the value can be inverted by inverting all the bits of the binary number in the above calculation.

Here, in general, when performing a matrix calculation such as cosine transform, there is a set of rows in which the absolute value is equal but the sign is inverted only in the contents of the counting matrix, and in that case, the sign of the input data is calculated in the product-sum operation. Is equivalent to inverting the sign of the count. Therefore, by providing a function of inverting input data, the ROM can be shared, and the size of the ROM can be reduced. The input data is inverted by ROM
This can be easily performed by providing an exclusive OR circuit or the like at the input of.

In the above circuit, the difference from the conventional offset binary code is , And is always a constant value of 1/2 regardless of the word length.

Therefore, when a so-called rounding operation is performed on an intermediate result by multiplication of data having a long word length or the like in this circuit, good rounding can be performed by simply truncating the lower order. This is particularly effective when high precision calculation is required in an application in which is input to the same arithmetic circuit again.

〔The invention's effect〕

According to the present invention, the input data is set to the offset binary code, and the value of each digit x _{nm is} (x _nm −1 /
By performing the calculation using 2), exceptional processing during the calculation is eliminated, and the circuit configuration can be simplified, and a good calculation result can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of the present invention, FIG. 2 is a diagram for explaining the same, and FIG. 3 is a diagram for explaining a conventional technique. (1 ₁ ) to (1 _N ) are input terminals, (3) is a ROM, (4X) is an adder, (7X) is a switch, and (8) is an output terminal.

Claims (1)

(57) [Claims] (1) N is a term. Cn is a coefficient. Xn is a product-sum operation circuit for obtaining data. Xn = [X _nm ], a code obtained by binarizing the above Xn into an offset binary. A sequential code converting means for converting the converted code into A product-sum operation circuit comprising: a cumulative adder that sequentially performs a calculation by shifting digits by using the initial value as an initial value; and an output unit that outputs the result of the cumulative addition.