JPS6148778B2 - - Google Patents

Info

Publication number
JPS6148778B2
JPS6148778B2 JP53149111A JP14911178A JPS6148778B2 JP S6148778 B2 JPS6148778 B2 JP S6148778B2 JP 53149111 A JP53149111 A JP 53149111A JP 14911178 A JP14911178 A JP 14911178A JP S6148778 B2 JPS6148778 B2 JP S6148778B2
Authority
JP
Japan
Prior art keywords
film
wiring
layer
polycrystalline silicon
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53149111A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5575243A (en
Inventor
Ken Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14911178A priority Critical patent/JPS5575243A/ja
Publication of JPS5575243A publication Critical patent/JPS5575243A/ja
Publication of JPS6148778B2 publication Critical patent/JPS6148778B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP14911178A 1978-12-04 1978-12-04 Method of fabricating mis semiconductor device having two-layer polycrystalline silicon wired layer Granted JPS5575243A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14911178A JPS5575243A (en) 1978-12-04 1978-12-04 Method of fabricating mis semiconductor device having two-layer polycrystalline silicon wired layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14911178A JPS5575243A (en) 1978-12-04 1978-12-04 Method of fabricating mis semiconductor device having two-layer polycrystalline silicon wired layer

Publications (2)

Publication Number Publication Date
JPS5575243A JPS5575243A (en) 1980-06-06
JPS6148778B2 true JPS6148778B2 (enExample) 1986-10-25

Family

ID=15467937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14911178A Granted JPS5575243A (en) 1978-12-04 1978-12-04 Method of fabricating mis semiconductor device having two-layer polycrystalline silicon wired layer

Country Status (1)

Country Link
JP (1) JPS5575243A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0296179U (enExample) * 1989-01-19 1990-07-31

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5821355A (ja) * 1981-07-29 1983-02-08 Nec Corp 半導体装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS583380B2 (ja) * 1977-03-04 1983-01-21 株式会社日立製作所 半導体装置とその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0296179U (enExample) * 1989-01-19 1990-07-31

Also Published As

Publication number Publication date
JPS5575243A (en) 1980-06-06

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