JPS5575243A - Method of fabricating mis semiconductor device having two-layer polycrystalline silicon wired layer - Google Patents

Method of fabricating mis semiconductor device having two-layer polycrystalline silicon wired layer

Info

Publication number
JPS5575243A
JPS5575243A JP14911178A JP14911178A JPS5575243A JP S5575243 A JPS5575243 A JP S5575243A JP 14911178 A JP14911178 A JP 14911178A JP 14911178 A JP14911178 A JP 14911178A JP S5575243 A JPS5575243 A JP S5575243A
Authority
JP
Japan
Prior art keywords
layer
electrode
polycrystalline silicon
film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14911178A
Other languages
English (en)
Other versions
JPS6148778B2 (ja
Inventor
Ken Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14911178A priority Critical patent/JPS5575243A/ja
Publication of JPS5575243A publication Critical patent/JPS5575243A/ja
Publication of JPS6148778B2 publication Critical patent/JPS6148778B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP14911178A 1978-12-04 1978-12-04 Method of fabricating mis semiconductor device having two-layer polycrystalline silicon wired layer Granted JPS5575243A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14911178A JPS5575243A (en) 1978-12-04 1978-12-04 Method of fabricating mis semiconductor device having two-layer polycrystalline silicon wired layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14911178A JPS5575243A (en) 1978-12-04 1978-12-04 Method of fabricating mis semiconductor device having two-layer polycrystalline silicon wired layer

Publications (2)

Publication Number Publication Date
JPS5575243A true JPS5575243A (en) 1980-06-06
JPS6148778B2 JPS6148778B2 (ja) 1986-10-25

Family

ID=15467937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14911178A Granted JPS5575243A (en) 1978-12-04 1978-12-04 Method of fabricating mis semiconductor device having two-layer polycrystalline silicon wired layer

Country Status (1)

Country Link
JP (1) JPS5575243A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5821355A (ja) * 1981-07-29 1983-02-08 Nec Corp 半導体装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0296179U (ja) * 1989-01-19 1990-07-31

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108390A (en) * 1977-03-04 1978-09-21 Hitachi Ltd Semiconductor device and its manufacture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108390A (en) * 1977-03-04 1978-09-21 Hitachi Ltd Semiconductor device and its manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5821355A (ja) * 1981-07-29 1983-02-08 Nec Corp 半導体装置

Also Published As

Publication number Publication date
JPS6148778B2 (ja) 1986-10-25

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