JPS6148185B2 - - Google Patents

Info

Publication number
JPS6148185B2
JPS6148185B2 JP56101493A JP10149381A JPS6148185B2 JP S6148185 B2 JPS6148185 B2 JP S6148185B2 JP 56101493 A JP56101493 A JP 56101493A JP 10149381 A JP10149381 A JP 10149381A JP S6148185 B2 JPS6148185 B2 JP S6148185B2
Authority
JP
Japan
Prior art keywords
input
channel
output
interrupt
system reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56101493A
Other languages
English (en)
Japanese (ja)
Other versions
JPS583013A (ja
Inventor
Masato Tsuru
Yoshiaki Matsubara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56101493A priority Critical patent/JPS583013A/ja
Publication of JPS583013A publication Critical patent/JPS583013A/ja
Publication of JPS6148185B2 publication Critical patent/JPS6148185B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
JP56101493A 1981-06-30 1981-06-30 チヤネル制御方式 Granted JPS583013A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56101493A JPS583013A (ja) 1981-06-30 1981-06-30 チヤネル制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56101493A JPS583013A (ja) 1981-06-30 1981-06-30 チヤネル制御方式

Publications (2)

Publication Number Publication Date
JPS583013A JPS583013A (ja) 1983-01-08
JPS6148185B2 true JPS6148185B2 (enrdf_load_stackoverflow) 1986-10-23

Family

ID=14302187

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56101493A Granted JPS583013A (ja) 1981-06-30 1981-06-30 チヤネル制御方式

Country Status (1)

Country Link
JP (1) JPS583013A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61202257A (ja) * 1985-03-05 1986-09-08 Fujitsu Ltd チヤネル初期化制御方式
JPS6273913U (enrdf_load_stackoverflow) * 1985-10-25 1987-05-12

Also Published As

Publication number Publication date
JPS583013A (ja) 1983-01-08

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