JPS6146061B2 - - Google Patents

Info

Publication number
JPS6146061B2
JPS6146061B2 JP56194698A JP19469881A JPS6146061B2 JP S6146061 B2 JPS6146061 B2 JP S6146061B2 JP 56194698 A JP56194698 A JP 56194698A JP 19469881 A JP19469881 A JP 19469881A JP S6146061 B2 JPS6146061 B2 JP S6146061B2
Authority
JP
Japan
Prior art keywords
outer container
plate
semiconductor chip
brazed
hard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56194698A
Other languages
English (en)
Other versions
JPS5893358A (ja
Inventor
Shinobu Takahama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56194698A priority Critical patent/JPS5893358A/ja
Priority to GB08233407A priority patent/GB2111746B/en
Priority to DE19823243689 priority patent/DE3243689A1/de
Publication of JPS5893358A publication Critical patent/JPS5893358A/ja
Priority to US06/884,293 priority patent/US4677741A/en
Publication of JPS6146061B2 publication Critical patent/JPS6146061B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49149—Assembling terminal to base by metal fusion bonding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 この発明は、大電力半導体モジユールに使用す
る半導体チツプを外装容器内に装着し、外部電極
を引出し樹脂封止した半導体装置に関する。
大電力用半導体モジユールは半導体チツプの表
面保護や樹脂封止技術の進歩により、小形簡素
化、絶縁の向上、機能の複合集積化及び低価格が
可能となり、このようにされた製品が出現するよ
うになつてからまだ２年程度しかたつていない
が、最近広範囲の分野で急速に利用されるように
なつた。
従来のこの種の半導体装置は第１図に大電力パ
ワーモジユールを縦断面図で示すようになつてい
た。１は放熱金属板、２は四角筒をなしこの放熱
金属板上に接着剤又は接着テープなど接着材３に
より接着された外装容器で、比較的耐熱性の低い
射出成型用樹脂（例えばPBT系樹脂、PPS系樹
脂、フエノール系樹脂などが使用される）を使用
している。４は絶縁材からなり放熱金属板１上に
接着剤３により接着された外部電極用架台、５は
この架台上にはんだ材６により接合された外部電
極、７は電力用半導体チツプ、８はこの半導体チ
ツプ側を絶縁し、かつ、放熱金属板１へ効率よく
熱伝達するためのアルミナセラミツク板で、両面
にメタライズ層９が印刷されていてはんだ材６に
より放熱金属板１に接合されている。１０はアル
ミナセラミツク板８上にはんだ材６により接合さ
れたヒートシンク板で、上面に半導体チツプ７を
はんだ材６により接合している。１１は半導体チ
ツプ７と外部電極５とを接続するアルミ線、１２
は外装容器２内に充てんされ、半導体チツプ７部
を絶縁封止し、かつ、アルミ線１１に機械的応力
が加わるのを軽減するようにした封止樹脂で、軟
質のシリコーン系樹脂を用いている。１３は封止
樹脂１２上に充てんされ、外部電極５の固定及び
外部からの機械的作用に対し保護する保護樹脂
で、比較的硬質のエポキシ系樹脂を用いている。
上記従来の装置は、外装容器２、外部電極用架
台４がそれぞれ別個に放熱金属板１に接着あるい
ははんだ付けされており、それぞれの部品の位置
決め及び取付けに手間がかかり、また、それぞれ
の接着やはんだ付けにも問題が生じていた。特
に、外装容器２は合成樹脂からなり、放熱金属板
１にろう付け接合はできなく、接着材で接着され
ているが、外形寸法が比較的大きく、複雑な形状
となつていて熱処縮による変形が生じやすく、こ
のため、外部からの水分がこの接着部から浸入す
ることが多かつた。例えば、水の浸入に対する加
速試験の一つである125℃２Kg/cm2の水中に浸漬す
る試験では、半導体チツプ７の劣化及び絶縁耐力
の低下が50〜100時間程度で発生するという欠点
があつた。
この発明は、セラミツクからなる外装容器を上
部が開口した箱形に形成し、内壁に段付面を設
け、外部電極をフレーム状に形成し、この外部電
極の底辺部を上記段付面上に硬ろう付け接合し、
外装容器の底下面に放熱金属板を硬ろう付け接合
し、組立部品数を少なくし、部品の位置決め及び
取付け作業の工程数を削減し、水分の浸入を防止
し、半導体チツプの劣化及び絶縁耐力の低下を防
止した半導体装置を提供することを目的としてい
る。
第２図及び第３図はこの発明の一実施例による
半導体装置を示す大電力パワーモジユールの平面
図及び縦断面図であり、６，７，１０〜１２は上
記従来装置と同一のものである。２１はアルミナ
セラミツク材からなるセラミツク外装容器で、底
部を有し上部が開口しており、内壁には中間高さ
位置に段付面２１ａが形成され、これより上方は
内壁面が四周に広げられている。２２は外装容器
２１の段付面２１ａ、底部上面と下面とに施され
たメタライズ層、２３〜２５は底辺部が段付面２
１ａにメタライズ層２２を介し銀ろう２６でろう
付けされた複数の各極外部電極で、ニツケルメツ
キ銅板からなるフレーム状に形成されている。こ
のフレームは鎖線で示すように連続して多数個分
がプレス打抜き成形された後、鎖線の縁部が切落
され１組宛の半導体装置分が分離される。なお、
外部電極２３〜２５の先端部は図では水平に折曲
げているが、上方に垂直に立上げられる場合もあ
る。外装容器２１の底上面にメタライズ層２２を
介し、ニツケルメツキ銅板からなる金属共通基板
２７が銀ろう２６付けされ、この金属共通基板に
ヒートシンク板１０がはんだ材６を介し載せら
れ、このヒートシンク板１０上にはんだ材６を介
し電力半導体チツプ７及び還流用ダイオードチツ
プ２８が載せられ、外部電極２５の底辺部上には
んだ材６を介しスピードアツプ用ダイオードチツ
プ２９が載せられ、加熱処理により上記各部品が
はんだ付けされている。各半導体チツプ７、２８
及び２９を対応する部品にそれぞれアルミ線１１
によりワイヤボンドしている。セラミツク外装容
器２１の底下面には、メタライズ層２２を介して
ニツケルメツキ銅板からなる金属当板３０が銀ろ
う２６付けされてあり、他の放熱板や放熱フイン
に容易にはんだ付け固着されるようにしてある。
ワイヤボンド後、外装容器２１内に封止樹脂１２
を充てんし封止している。
上記のように構成された一実施例の半導体装置
は、従来の装置の欠点を除去したもので、次のよ
うな多くの特長をもつている。
１ 外部電極に導体板フレームを用いたので、セ
ラミツク外装容器との位置決めが簡単で容易に
でき、かつ、このセラミツク外装容器に銀ろう
付けしたので、組立工程中における半導体チツ
プのはんだ付け時において再溶融するおそれが
なく、外装容器に完全に固定される。
２ 上部が開口し有底の箱形の外装容器を用いた
ので、水分の浸入が全くなくなり、したがつ
て、PCT試験における評価が大幅に改善され
る。
３ 外装容器の内壁に段付面を設けたので、この
段付面に底辺部が銀ろう付け固着され、大電流
が流される外部電極に、直接アルミ線を超音波
ボンデイングすることができ、かつ、アルミ線
の機械的保護用の軟質のシリコーン樹脂充てん
のみでよく、しかも、側面および外部電極から
伝わる機械的ストレスに対しても十分保護する
ことが可能となり、従来のように、充てんした
軟質のシリコーン樹脂の上に、硬いエポキシ系
の樹脂の充てんが不用となる。
４ 箱形のセラミツク外装容器の中ですべての部
品が組立てられるので、他の部品との相互位置
合せ作業が簡単になり、量産化が容易となる。
５ 箱形外装容器の底部の下面及び内面とに同時
に金属当板及び共通基板を硬ろう付けしたの
で、ろう付け時外装容器にかかる機械的ストレ
ス（主として熱膨張差による）が軽減される。
６ 外装容器の内壁に段付面を設けたので、半導
体チツプと外部電極間の絶縁距離が垂直方向に
も増されるので、小形化することができる。
以上のように、この発明の半導体装置によれ
ば、セラミツク外装容器を上部が開口して有底に
し、内壁に中間高さ位置に段付面を設け、導体板
フレームからなる外部電極の底辺部を上記段付面
に硬ろう付けしたので、組立作業が容易で簡略化
され、低価格になり、量産化が可能となり、外部
からの水分の浸入が防止され、信頼性が向上され
る。さらに外装容器の底部下面に金属当板を硬ろ
う付けしたので、他の放熱板などに容易に軟ろう
付け固着ができる。
【図面の簡単な説明】
第１図は従来の半導体装置を示す大電力パワー
モジユールの要部の縦断面図、第２図はこの発明
の一実施例による半導体装置を示す大電力パワー
モジユールの要部の平面図、第３図は第２図の
線における断面図である。 ６……はんだ材、７……半導体チツプ、１０…
…ヒートシンク板、１２……封止樹脂、２１……
セラミツク外装容器、２１ａ……段付面、２２…
…メタライズ層、２３〜２５……外部電極、２６
……銀ろう、２７……金属共通基板、２８，２９
……ダイオードチツプ、３０……金属当板。な
お、図中同一符号は同一又は相当部分を示す。

Claims (1)

    【特許請求の範囲】
  1. １ 上方が開口し底部を有する箱形にされ、内壁
    に中間高さ位置に段付面が設けられ、上記底部の
    上面及び下面と段付面とにメタライズ層が施され
    たセラミツク外装容器、導体板フレーム状をな
    し、底辺部が上記段付面に硬ろう付けされ端部が
    上方に引出された複数の外部電極、上記外装容器
    の底部上面に硬ろう付けされた金属共通基板、こ
    の共通基板上に軟ろう付けされ上面に半導体チツ
    プを軟ろう付けしたヒートシンク板、上記外装容
    器の底部下面に硬ろう付けされた金属当板、及び
    上記外装容器に充てんされ封止する軟質系の封止
    樹脂を備えた半導体装置。
JP56194698A 1981-11-30 1981-11-30 半導体装置 Granted JPS5893358A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP56194698A JPS5893358A (ja) 1981-11-30 1981-11-30 半導体装置
GB08233407A GB2111746B (en) 1981-11-30 1982-11-23 Semiconductor package
DE19823243689 DE3243689A1 (de) 1981-11-30 1982-11-25 Halbleitervorrichtung
US06/884,293 US4677741A (en) 1981-11-30 1986-07-10 Method of manufacturing package for high power integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56194698A JPS5893358A (ja) 1981-11-30 1981-11-30 半導体装置

Publications (2)

Publication Number Publication Date
JPS5893358A JPS5893358A (ja) 1983-06-03
JPS6146061B2 true JPS6146061B2 (ja) 1986-10-11

Family

ID=16328778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56194698A Granted JPS5893358A (ja) 1981-11-30 1981-11-30 半導体装置

Country Status (4)

Country Link
US (1) US4677741A (ja)
JP (1) JPS5893358A (ja)
DE (1) DE3243689A1 (ja)
GB (1) GB2111746B (ja)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6235658A (ja) * 1985-08-09 1987-02-16 Fuji Electric Co Ltd 半導体装置
US4931906A (en) * 1988-03-25 1990-06-05 Unitrode Corporation Hermetically sealed, surface mountable component and carrier for semiconductor devices
US5182628A (en) * 1989-06-28 1993-01-26 Hitachi, Ltd. Semiconductor device having particular solder interconnection arrangement
US5285690A (en) * 1992-01-24 1994-02-15 The Foxboro Company Pressure sensor having a laminated substrate
US5313091A (en) * 1992-09-28 1994-05-17 Sundstrand Corporation Package for a high power electrical component
US5297001A (en) * 1992-10-08 1994-03-22 Sundstrand Corporation High power semiconductor assembly
KR100322177B1 (ko) 1993-12-27 2002-05-13 이누이 도모지 내연기관용점화장치
DE10221857A1 (de) * 2002-05-16 2003-11-27 Osram Opto Semiconductors Gmbh Verfahren zum Befestigen eines Halbleiterchips in einem Kunststoffgehäusekörper, optoelektronisches Halbleiterbauelement und Verfahren zu dessen Herstellung
US7209366B2 (en) * 2004-03-19 2007-04-24 Intel Corporation Delivery regions for power, ground and I/O signal paths in an IC package
DE102006022254B4 (de) * 2006-05-11 2008-12-11 Infineon Technologies Ag Halbleiterbauteil mit in Kunststoffgehäusemasse eingebetteten Halbleiterbauteilkomponenten, Anordnung für eine Mehrzahl von Halbleiterbauteilen und Verfahren zur Herstellung von Halbleiterbauteilen
US8049323B2 (en) * 2007-02-16 2011-11-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip holder with wafer level redistribution layer
CN103094129B (zh) * 2011-10-28 2016-04-06 无锡华润安盛科技有限公司 一种半导体器件封装工艺
CN103311133B (zh) * 2013-05-20 2015-11-04 临海市志鼎电子科技有限公司 一种功率半导体模块焊接前倒装工艺

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2921245A (en) * 1958-10-08 1960-01-12 Int Rectifier Corp Hermetically sealed junction means
US3223903A (en) * 1961-02-24 1965-12-14 Hughes Aircraft Co Point contact semiconductor device with a lead having low effective ratio of length to diameter
US3141226A (en) * 1961-09-27 1964-07-21 Hughes Aircraft Co Semiconductor electrode attachment
DE1231811B (de) * 1962-04-06 1967-01-05 Bosch Gmbh Robert Halbleiteranordnung
US3241011A (en) * 1962-12-26 1966-03-15 Hughes Aircraft Co Silicon bonding technology
GB1163785A (en) * 1965-12-22 1969-09-10 Texas Instruments Inc Composite Header for a Semiconductor Device
JPS4810904B1 (ja) * 1969-03-12 1973-04-09
US3681513A (en) * 1971-01-26 1972-08-01 American Lava Corp Hermetic power package
US3793064A (en) * 1971-11-15 1974-02-19 Du Pont Product and process for cavity metallization of semiconductor packages
US3964155A (en) * 1972-02-23 1976-06-22 The United States Of America As Represented By The Secretary Of The Navy Method of planar mounting of silicon solar cells
DE2230863C2 (de) * 1972-06-23 1981-10-08 Intersil Inc., Cupertino, Calif. Gehäuse für ein Halbleiterelement
US3908185A (en) * 1974-03-06 1975-09-23 Rca Corp High frequency semiconductor device having improved metallized patterns
JPS5272170A (en) * 1975-12-12 1977-06-16 Nec Corp Package for semiconductor elements
JPS5336468A (en) * 1976-09-17 1978-04-04 Hitachi Ltd Package for integrated circuit
US4176443A (en) * 1977-03-08 1979-12-04 Sgs-Ates Componenti Elettronici S.P.A. Method of connecting semiconductor structure to external circuits
US4117508A (en) * 1977-03-21 1978-09-26 General Electric Company Pressurizable semiconductor pellet assembly
JPS5450269A (en) * 1977-09-28 1979-04-20 Nec Home Electronics Ltd Semiconductor device
US4445274A (en) * 1977-12-23 1984-05-01 Ngk Insulators, Ltd. Method of manufacturing a ceramic structural body
JPS54140468A (en) * 1978-04-24 1979-10-31 Hitachi Ltd Glass sealing package type device and its manufacture
JPS5568661A (en) * 1978-11-17 1980-05-23 Hitachi Ltd Structure for mounting power transistor
DE3030763A1 (de) * 1979-08-17 1981-03-26 Amdahl Corp., Sunnyvale, Calif. Packung fuer eine integrierte schaltung in plaettchenform
DE3028178C2 (de) * 1980-07-25 1985-05-09 Brown, Boveri & Cie Ag, 6800 Mannheim Leistungshalbleiter-Modul

Also Published As

Publication number Publication date
GB2111746A (en) 1983-07-06
US4677741A (en) 1987-07-07
DE3243689A1 (de) 1983-06-30
JPS5893358A (ja) 1983-06-03
DE3243689C2 (ja) 1987-12-23
GB2111746B (en) 1985-09-25

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