CN103094129B - 一种半导体器件封装工艺 - Google Patents

一种半导体器件封装工艺 Download PDF

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CN103094129B
CN103094129B CN201110347310.7A CN201110347310A CN103094129B CN 103094129 B CN103094129 B CN 103094129B CN 201110347310 A CN201110347310 A CN 201110347310A CN 103094129 B CN103094129 B CN 103094129B
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CN103094129A (zh
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龚平
孙宏伟
王建新
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Wuxi China Resources Micro Assembly Tech Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

本发明提供了一种半导体器件封装工艺,它包含:将元件安装到基板上指定的位置处;采用专用治具,将框架凸点连接到基板上;键合元件之间以及元件与框架之间的金属连接线;以及将基板塑封起来。采用本发明的半导体器件封装工艺,可以降低材料成本,大大减少人工污染,并提高模块的可靠性。

Description

一种半导体器件封装工艺
技术领域
本发明涉及半导体器件,本发明尤其涉及一种半导体器件的封装工艺。
背景技术
半导体器件模块在制造工艺的最后阶段,通常需要将整个模块密封起来,形成一个完整的模块封装结构。
现有技术的封装工艺中,通常在将元件接插到覆铜陶瓷基板(DBC基板)上以后,需要采用特殊的治具,将元件的针脚连接到DBC基板上的锡膏处,并在基板上加上外壳,最后在加了外壳的模块内部注入胶水后烘烤,使之固化。
但是,这种现有技术的封装工艺,效率低、费时、费力。由于采用的是外壳封装,使得整个模块体积较大。而且由于灌封模块时采用灌胶固化的方式来保护模块和引线,即,在模块外壳内注入硅橡胶,通过烘烤固化硅橡胶来保护模块内部元件和连线的连接,因而可靠性较低。
另外,由于外壳通常是陶瓷材料,因此,材料成本较高。
图4中示出现有技术采用灌封技术得到的模块的外形。
发明内容
本发明的目的是提供一种封装工艺。这种工艺可以使得封装无需外壳,并且可以大大减小模块的体积,提高模块连接的可靠性。
本发明提供了一种半导体模块封装工艺,包含:将元件安装到基板上指定的位置处;将框架凸点连接到基板上;键合元件之间以及元件与框架之间的金属连接线;以及将基板塑封起来。
本发明的半导体模块封装工艺,还可以包含在将元件安装到基板上指定的位置处之前,在指定位置以及基板与框架凸点连接处涂抹锡膏。
本发明的半导体模块封装工艺中,将框架凸点连接到基板上是连接到涂抹了锡膏处。
本发明的半导体模块封装工艺,还可以包含在键合元件之间以及元件与框架之间的金属连接线之前,使锡膏固化。
本发明的半导体模块封装工艺中,使锡膏固化是通过高温回流焊技术或真空焊技术来实现的。
本发明的半导体模块封装工艺,还可以包含在使锡膏固化之后,清洗掉基板和框架上残留的助焊剂。
本发明的半导体模块封装工艺中,塑封所采用的材料是环氧树脂。
本发明的半导体模块封装工艺中,在塑封完成以后,对引脚部位进行镀锡。
本发明的半导体模块封装工艺中,在完成镀锡之后,可以将引脚弯曲成一定的角度。
附图说明
图1是本发明一种实施例的半导体模块塑封工艺流程图;
图2是本发明实施例中塑封型模块的外形示意图;
图3是本发明一种实施例中所采用的塑封型框架结构示意图;而
图4是现有技术中灌封型模块的外形示意图。
具体实施方式
下面参照附图,说明本发明一种实施例的半导体模块塑封工艺流程。
如图1所示。
首先,在基板上需要接插元件的位置处,以及基板与框架需凸点连接处涂抹锡膏;本实施例中,所述基板采用DBC基板;
将元件安装到基板上指定的位置处,这里的元件可以是芯片,也可以是无源器件;
采用专用治具,将框架凸点连接到基板上已经涂抹了锡膏处;
使锡膏固化;
键合元件之间以及元件与框架之间的金属连接线;以及
将基板塑封起来。
采用上述步骤,即可完成对模块的塑封。
框架的形状以及引脚的分布是按照具体模块的技术要求设计的。图3中示出了一种框架结构的示意图。从图3中可以看出,这种框架结构含有引脚和连接凸点,但不含小岛。
通常,为了使得塑封模块具有更可靠的性能,在进行键合元件之间以及元件与框架之间的金属连接线之前,还可以包含清洗掉基板和框架上残留的助焊剂的步骤。而且,为了使得塑封后的模块与外部元件具有更好的连接性,还可以对塑封后露出的引脚进行镀锡。
为了便于模块的接插,也可以在进行了引脚镀锡后,将引脚弯曲成型。成型的角度通常是90度。
使锡膏固化通常是采用高温回流焊接技术或者真空焊接技术来进行的,而密封框架和基板所采用的材料可以是环氧树脂。
本发明工艺中,采用的是引脚框架型结构,框架与基板之间的连接代替了原有的针式引脚。框架的每一单元包含了一个模块的所有引脚。而每个框架含有多个单元。因此,与现有技术中采用人工插接引脚相比,本发明大大提高了效率,从而降低了人工成本。
同时,由于采用环氧树脂对模块进行封装,代替了现有技术中采用陶瓷外壳,从而大大降低了材料成本,并且使得塑封型模块的设计更加紧凑,外形尺寸更小。
另一方面,由于采用环氧树脂来包封元件和引线,代替了现有技术中采用灌胶固化的保护方式,使得模块的可靠性更高。
图2中示出了采用本发明实施例的工艺得到的塑封型模块的外形。
上文中,参照附图描述了本发明的具体实施例。但是,本领域中的普通技术人员能够理解,在不偏离本发明的原理和精神的情况下,还可以对本发明的上述实施例作某些修改和变更。实施例的描述仅仅是为了使本领域中的普通技术人员能够理解、实施本发明,不应当将本发明理解为仅仅限于所描述的实施例。本发明的保护范围由权利要求书所限定。

Claims (4)

1.一种半导体模块封装工艺,包含:
在指定位置处以及基板与框架凸点连接处涂抹锡膏;
将元件安装到基板上所述指定位置处;
将框架凸点连接到基板上的涂抹了锡膏处;
使锡膏固化;
清洗掉基板和框架上残留的助焊剂;
键合元件之间以及元件与框架之间的金属连接线;将基板塑封起来;以及
对引脚部位进行镀锡。
2.如权利要求1所述的半导体模块封装工艺,使锡膏固化是通过高温回流焊技术或真空焊技术来实现的。
3.如权利要求1所述的半导体模块封装工艺,所述塑封所采用的材料是环氧树脂。
4.如权利要求1所述的半导体模块封装工艺,在完成镀锡之后,将引脚弯曲成一定的角度。
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