CN101740536B - 半导体封装 - Google Patents

半导体封装 Download PDF

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CN101740536B
CN101740536B CN2009100002468A CN200910000246A CN101740536B CN 101740536 B CN101740536 B CN 101740536B CN 2009100002468 A CN2009100002468 A CN 2009100002468A CN 200910000246 A CN200910000246 A CN 200910000246A CN 101740536 B CN101740536 B CN 101740536B
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chip carrier
earth
chip
semiconductor packages
earth brace
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CN101740536A (zh
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陈南璋
王有伟
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明提供一种半导体封装，包括：芯片座；半导体芯片，设置于所述芯片座上；多个引脚，位于沿着所述芯片座外围边缘的第一平面；接地杆，从所述第一平面下移安置至位于所述多个引脚和所述芯片座之间的第二平面；多个下移安置杆，连接所述接地杆和所述芯片座；多个接地线，接合至所述接地杆和所述芯片座；以及塑模材料，至少部分封装所述芯片座、所述多个引脚的内部端，藉此所述芯片座的底部表面可曝露于所述塑模材料外。利用本发明可降低模拟接地信号与数字接地信号的噪声耦合，消除水波纹效应。

Description

半导体封装
技术领域
本发明涉及半导体封装，尤其涉及一种导线架半导体封装(leadframesemiconductor package)。
背景技术
导线架半导体封装在半导体封装领域内为大家所习知。传统的导线架包括多个金属引脚(metal lead)，该多个金属引脚在封装制造中，由一矩形框(rectangular frame)暂时保持在中心区域附近的一平面上。芯片座(die pad)在中心区域由附接于矩形框的多个系杆(tie bar)支持。引脚从与矩形框成一体的第一端延伸至反向的第二端(opposite second end)，该第二端有间隔地相邻于所述的芯片座。
在封装制造中，半导体芯片附接于芯片座，然后芯片上的引线接合焊盘(wire-bonding pad)藉由精细导电的接合引线与所选的引脚内部端相连接，以在芯片和引脚间传送电源、接地或信号。环氧树脂(epoxy resin)保护体成型于该组合体(assembly)上，将芯片、引脚的内部端(inner end)和接合引线封闭与密封起来，以与外部环境的有害元素隔离。矩形框和引脚的外部端(outer end)位于环氧树脂保护体外部，并且，在环氧树脂保护体成型后，矩形框从引脚处被去除，引脚的外部端则用于封装和外部印刷电路板的互连。
外露型芯片座(Exposed die pad，E-pad)导线架封装是一种已知的导线架半导体封装，该外露型芯片座导线架封装是外露芯片座的底部表面于封装体(encapsulation body)的外部。外露的芯片座相当于一散热片(heat sink)，可改进芯片座的散热效率。该外露的芯片座电连接于外部印刷电路板的一接地面。
研究发现，外露型芯片座受湿度(moisture)影响较大。为了避免由于湿度侵袭和塑料-金属(plastic body-metal)接口的脱层(delamination)等可靠性问题，从半导体芯片接地焊盘(ground pad)引出的接地线并不直接接合至芯片座的表面，而是连接至矩形环状的地桥杆(ground bridge bar)，该地桥杆在不同的下移安置面(downset plane)围绕该芯片座。连接于芯片座的多个系杆可支持该地桥杆。
然而，带有如此地桥杆配置的导线架封装有一个缺点，即一同连接至地桥杆的模拟和数字接地线可能会产生噪声或地耦合(ground coupling)，这在电视系统中被称为水波纹效应(water wave effect)。这种导线架封装的另一个缺点是地桥杆容易扭曲和变形，会减弱接合强度。因此，有待于提出一种可消除如前所述的数字和模拟间的地耦合与电视系统中水波纹效应的改进型导线架封装结构。
发明内容
由于在现有技术中模拟和数字接地线可能会产生噪声或地耦合以及地桥杆容易扭曲和变形，有鉴于此，本发明的目的之一是提供一种半导体封装。
本发明提供一种半导体封装，包括：芯片座；半导体芯片，设置于所述芯片座上；多个引脚，位于沿着所述芯片座外围边缘的第一平面；接地杆，从所述第一平面下移安置至位于所述多个引脚和所述芯片座之间的第二平面；多个下移安置杆，连接所述接地杆和所述芯片座；多个接地线，接合至所述接地杆和所述芯片座；以及塑模材料，至少部分封装所述芯片座、所述多个引脚的内部端，藉此所述芯片座的底部表面可曝露于所述塑模材料外。
本发明另提供一种半导体封装，包括：芯片座；半导体芯片，设置于所述芯片座上；多个引脚，位于沿着所述芯片座外围边缘的第一平面；第一接地杆，从所述第一平面下移安置至第二平面；第二接地杆，与所述多个引脚齐平；第一下移安置杆，连接所述第一接地杆和所述芯片座；第二下移安置杆，连接所述第二接地杆和所述第一接地杆；多个第一接合引线，接合至所述第一接地杆，传送数字接地；多个第二接合引线，接合至所述延伸接地杆，传送模拟接地；以及塑模材料，至少部分封装所述芯片座、所述多个引脚的内部端，藉此所述芯片座的底部表面可曝露于所述塑模材料外。
本发明另提供一种半导体封装，包括：芯片座；半导体芯片，设置于所述芯片座上；多个引脚，位于沿着所述芯片座外围边缘的第一平面；接地杆，从所述第一平面下移安置至位于所述多个引脚和所述芯片座之间的第二平面；多个下移安置杆，连接所述接地杆和所述芯片座；多个第一接地线和第二接地线，接合至所述接地杆，其中在所述接地杆中存在至少一个不连续处，以将所述第一接地线与所述第二接地线分离；以及塑模材料，至少部分封装所述芯片座、所述多个引脚的内部端，藉此所述芯片座的底部表面可曝露于所述塑模材料外。
本发明另提供一种半导体封装，包括：芯片座；半导体芯片，设置于所述芯片座上；多个引脚，位于沿着所述芯片座外围边缘的第一平面；接地杆，从所述第一平面下移安置至位于所述多个引脚和所述芯片座之间的第二平面；多个下移安置杆，连接所述接地杆和所述芯片座；多个接合引线，连接于所述接地杆和所述芯片座之间；以及塑模材料，至少部分封装所述芯片座、所述多个引脚的内部端，藉此所述芯片座的底部表面可曝露于所述塑模材料外。
本发明通过数字接地路径与模拟接地路径分离，可降低模拟接地信号与数字接地信号的噪声耦合，消除水波纹效应。
附图说明
图1为跟据本发明一实施例半导体封装的俯视示意图。
图2为图1所示半导体封装的截面示意图。
图3显示了根据本发明分离的接地杆片段的多个实施结构示意图。
图4为本发明另一实施例的半导体封装的截面示意图。
图5为图4所示半导体封装的部分平面示意图。
具体实施方式
消费电子的技术趋势为以低成本在更小的体积上实现更多的功能。外露型芯片座薄型四面扁平封装(Low-profile Quad Flat Package，LQFP)对多媒体芯片是一种低成本解决方案，但是其缺点在于其接脚数目(pin count)受限和较差的电气特性。
如前所述，导线架组件(leadframe component)与塑料封装(plastic package)体的脱层(delamination)会导致湿度对该封装的渗透。特别地，当温度改变时，由于不同材料(例如金属、环氧树脂和硅)热膨胀系数的差异很大，半导体封装不同部分的热膨胀与热收缩会有很大差异。因此，在制造或运行过程中，随着封装的温度循环改变，导线架组件变得与封装体脱层。
脱层发生在封装体的边缘，就会产生湿气对封装渗透的微裂缝(microscopiccrack)。湿气可侵蚀金属，会导致沿着湿气侵蚀路径的电流泄漏。为避免由于湿度侵袭和脱层等可靠性问题，接地线并不直接连接至芯片座的表面，相反地，接地线(数字接地线或模拟接地线)连接至一地桥杆(ground bridge bar)，地桥杆在不同的下移安置面(downset plane)围绕芯片座。然而，这种配置会导致接地信号耦合噪声。本发明则用于解决该问题。
下面描述本发明的一个或多个实施方式及其附图，其中全篇中同样的数字代表同样的组件，图标的结构不一定是完全按照尺寸比例绘制。
图1为根据本发明第一实施例之半导体封装的俯视示意图(top view)。图2为图1所示半导体封装的截面示意图。如图1和图2所示，根据本发明的第一实施例，半导体封装10包括半导体芯片20、多个引脚120、接地杆(groundbar)130、四个连接杆(connecting bar)142、多个下移安置(downset)杆144，其中，半导体芯片20设置于芯片座110的第一表面110a，多个引脚120位于沿着芯片座110外围边缘的第一平面，接地杆130从第一平面下移安置至位于引脚120的内部端(inner end)120a和芯片座110之间的第二平面，连接杆142从芯片座110的四个角向外延伸，下移安置杆144连接接地杆130和芯片座110。塑模材料(molding compound)30至少部分封装芯片座110、引脚120的内部端120a，藉此芯片座110的底部表面110b可曝露于塑模材料30外。
根据本实施例，外围凹槽(peripheral groove)112蚀刻于芯片座110的第一表面110a，且围绕半导体芯片20。镀层(plating layer)114，比如镀银或贵金属，形成于外围凹槽112内，以进行引线接合。外围凹槽112可增加耦合强度。为安全地将导线架组件锁在封装的塑料(plastic)上，以有效的减少导线架与塑料的脱层和湿气对封装的渗透，芯片座110的底部表面110b可部分的沿着芯片座110的外围蚀刻，以形成台阶(step)116。
半导体芯片20在其活动面(active surface)20a上包括多个接合焊盘(bondingpad)202，接合焊盘202进一步包括多个第一接地焊盘(ground pad)202a和多个第二接地焊盘202b和多个接合焊盘(例如信号或电源焊盘)202c。根据本实施例，第一接地焊盘202a为比较敏感的模拟接地焊盘，第二接地焊盘202b为数字接地焊盘。在本发明的另一实施例中，第一接地焊盘202a为数字接地焊盘，第二接地焊盘202b为比较敏感的模拟接地焊盘。
多个第一接合引线(bonding wire)212分别连接第一接地焊盘202a与接地杆130，多个第二接合引线214分别连接第二接地焊盘202b与外围凹槽112的镀层114上表面(plated top surface)，多个第三接合引线216连接结合焊盘202c(例如信号或电源焊盘)与引脚120，第三接合引线216即信号或电源线。根据本实施例，多个第四接合引线218连接芯片座110与接地杆130，使得接地电感(groundinductance)减少。因此，比较敏感的模拟接地焊盘202a通过第一接合引线212连接至接地杆130，形成模拟接地路径，而数字接地焊盘202b通过第二接合引线214连接至芯片座110之外围凹槽112的镀层114上表面，形成数字接地路径。藉由将数字接地路径与模拟接地路径分离，在运行中比较敏感的模拟接地信号不再受数字接地信号的干扰，水波纹效应可得到消除。
接地杆130可以是连续环形状，但本发明并不仅限于此。在接地杆130中可存在不连续处(discontinuity)132，形成分离的接地杆片段(segment)130a和130b。每一个接地杆片段130a和130b均分别由下移安置杆144支撑。多个第五接合引线220连接第二接地焊盘202b与接地杆片段130b，多个第六接合引线222连接第一接地焊盘202a与接地杆片段130a。藉由引线接合数字接地路径与模拟接地路径相分离，使得接地杆片段130a与接地杆片段130b分离，因此比较敏感的模拟接地信号可不受数字接地信号的干扰。
其中，第一接合引线212连接第一接地焊盘202a与接地杆130，第六接合引线222连接第一接地焊盘202a与片段130a，形成模拟接地路径。第一接合引线212和第六接合引线222均用于传送模拟接地，为第一接地线。其中，第二接合引线214连接第二接地焊盘202b与镀层114上表面，第五接合引线220连接第二接地焊盘202b与接地杆片段130b，形成数字接地路径。第二接合引线214和第五接合引线220均用于传送数字接地，为第二接地线。
分离的接地杆片段可具有各种形状，例如T型、U型、∏型、L型、蛇型或不规则型。图3显示了根据本发明分离的接地杆片段的多个实施结构示意图。在本发明中，用于传送数字接地信号的接合引线接合于其中一个分离的接地杆片段，用于传送模拟接地信号的接合引线接合于其中另一个分离的接地杆片段。藉此，数字接地信号和模拟接地信号之间的干扰得以避免。
图4为本发明另一实施例的半导体封装10a的截面示意图，图5为图4中半导体封装的部分平面示意图。如图4和图5所示，同样地，半导体封装10a包括半导体芯片20、多个引脚120、接地杆(ground bar)320、多个下移安置杆144a，其中，半导体芯片20设置于芯片座110的第一表面110a，多个引脚120位于沿着芯片座110外围边缘的第一平面，接地杆320从第一平面下移安置(downset)至位于引脚120的内部端(inner end)120a和芯片座110之间的一第二平面，下移安置杆144a连接接地杆320和芯片座110。
在引脚120的内部端120a和接地杆320之间提供一个延伸(extended)接地杆330，也就是说提供一个与第一平面中的多个引脚120齐平的接地杆，延伸接地杆330由连接于接地杆320的下移安置杆144b支持。塑模材料(moldingcompound)30至少部分封装芯片座110、引脚120的内部端120a，藉此芯片座110的底部表面110b可曝露于塑模材料30外。在本实施例中，提供接地杆320和延伸接地杆330，其中接地杆320为第一接地杆，延伸接地杆330为第二接地杆。
为安全地将导线架组件锁在封装的塑料上，以有效的减少导线架与塑料的脱层和湿气对封装的渗透，芯片座110的底部表面110b可部分的沿着芯片座110的外围蚀刻，以形成台阶116。并且，外围凹槽(peripheral groove)112可蚀刻于芯片座110的第一表面110a内，以增强塑模材料30和芯片座110的互锁(interlock)。
半导体芯片20在其活动面20a上包括多个接合焊盘202，接合焊盘202进一步包括多个第一接地焊盘202a，多个第二接地焊盘202b和多个接合焊盘(例如信号或电源焊盘)202c。根据本实施例，第一接地焊盘202a为数字接地焊盘，第二接地焊盘202b为比较敏感的模拟接地焊盘。多个第一接合引线312分别连接第一接地焊盘202a与接地杆320，多个第二接合引线314分别连接第二接地焊盘202b与延伸接地杆330，多个第三接合引线316连接接合焊盘202c(例如信号或电源焊盘)与引脚120。选择性的，多个第四接合引线318连接芯片座110与芯片20。藉由将数字接地路径与模拟接地路径分离，在运行中比较敏感的模拟接地信号不再受数字接地信号的干扰，水波纹效应可得到消除。
以上所述仅为本发明的较佳实施例，凡依本发明申请专利范围所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (17)

1.一种半导体封装，其特征在于包括：
芯片座；
半导体芯片，设置于所述芯片座上；
多个引脚，位于沿着所述芯片座外围边缘的第一平面；
接地杆，从所述第一平面下移安置至位于所述多个引脚和所述芯片座之间的第二平面；
多个下移安置杆，连接所述接地杆和所述芯片座；
多个第一接地线，连接所述半导体芯片以及所述接地杆；
多个第二接地线，连接所述半导体芯片以及所述芯片座；以及
塑模材料，至少部分封装所述芯片座、所述多个引脚的内部端，藉此所述芯片座的底部表面可曝露于所述塑模材料外。
2.根据权利要求1所述的半导体封装，其特征在于，所述多个第一接地线用于传送模拟接地，所述多个第二接地线用于传送数字接地。
3.根据权利要求2所述的半导体封装，其特征在于，所述第一接地线直接接合于所述接地杆，所述第二接地线直接接合于所述芯片座。
4.根据权利要求3所述的半导体封装，其特征在于，所述第二接地线接合至部分蚀刻于所述芯片座的外围凹槽。
5.根据权利要求2所述的半导体封装，其特征在于，所述第一接地线和所述第二接地线均接合于所述接地杆，并且在所述接地杆中存在至少一个不连续处，以将所述第一接地线与所述第二接地线分离。
6.根据权利要求1所述的半导体封装，其特征在于，所述半导体封装还包含多个信号线以连接所述半导体芯片上的信号焊盘与所述引脚。
7.根据权利要求1所述的半导体封装，其特征在于，所述半导体封装还包含多个电源线以连接所述半导体芯片上的电源焊盘与所述引脚。
8.根据权利要求1所述的半导体封装，其特征在于，所述接地杆可以是T型、U型、∏型、L型、蛇型或不规则型。
9.根据权利要求1所述的半导体封装，其特征在于，所述半导体封装还包含多个接合引线，用于连接所述芯片座和所述接地杆。
10.一种半导体封装，其特征在于包括：
芯片座；
半导体芯片，设置于所述芯片座上；
多个引脚，位于沿着所述芯片座外围边缘的第一平面；
第一接地杆，从所述第一平面下移安置至第二平面；
第二接地杆，与所述多个引脚齐平；
第一下移安置杆，连接所述第一接地杆和所述芯片座；
第二下移安置杆，连接所述第二接地杆和所述第一接地杆；
多个第一接合引线，接合所述半导体芯片至所述第一接地杆，传送数字接地；
多个第二接合引线，接合所述半导体芯片至所述第二接地杆，传送模拟接地；以及塑模材料，至少部分封装所述芯片座、所述多个引脚的内部端，藉此所述芯片座的底部表面可曝露于所述塑模材料外。
11.根据权利要求10所述的半导体封装，其特征在于，其中包含多个第三接合引线，连接信号或电源焊盘与所述多个引脚。
12.根据权利要求10所述的半导体封装，所述半导体封装包含多个第四接合引线，连接所述半导体芯片与所述芯片座。
13.一种半导体封装，其特征在于包括：
芯片座；
半导体芯片，设置于所述芯片座上；
多个引脚，位于沿着所述芯片座外围边缘的第一平面；
接地杆，从所述第一平面下移安置至位于所述多个引脚和所述芯片座之间的第二平面；
多个下移安置杆，连接所述接地杆和所述芯片座；
多个数字接地线和模拟接地线，接合所述半导体芯片至所述接地杆，其中在所述接地杆中存在至少一个不连续处，以将所述数字接地线与所述模拟接地线分离，其中该不连续处和形成的接地杆在同一边；以及
塑模材料，至少部分封装所述芯片座、所述多个引脚的内部端，藉此所述芯片座的底部表面可曝露于所述塑模材料外。
14.根据权利要求13所述的半导体封装，其特征在于，所述半导体封装包含多个接合引线，连接所述芯片座和所述接地杆。
15.根据权利要求14所述的半导体封装，其特征在于，所述接合引线接合至部分蚀刻于所述芯片座的外围凹槽。
16.一种半导体封装，其特征在于包括：
芯片座；
半导体芯片，设置于所述芯片座上；
多个引脚，位于沿着所述芯片座外围边缘的第一平面；
接地杆，从所述第一平面下移安置至位于所述多个引脚和所述芯片座之间的第二平面；
多个下移安置杆，连接所述接地杆和所述芯片座；
多个第一接地线，连接所述半导体芯片以及所述接地杆；
多个第二接地线，电性连接于所述接地杆和所述芯片座之间；以及
塑模材料，至少部分封装所述芯片座、所述多个引脚的内部端，藉此所述芯片座的底部表面可曝露于所述塑模材料外。
17.根据权利要求16所述的半导体封装，其特征在于，所述半导体封装还包含多个电源或信号线，连接所述半导体芯片的电源或信号焊盘与所述引脚。
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