JPS6129024B2 - - Google Patents

Info

Publication number
JPS6129024B2
JPS6129024B2 JP53127609A JP12760978A JPS6129024B2 JP S6129024 B2 JPS6129024 B2 JP S6129024B2 JP 53127609 A JP53127609 A JP 53127609A JP 12760978 A JP12760978 A JP 12760978A JP S6129024 B2 JPS6129024 B2 JP S6129024B2
Authority
JP
Japan
Prior art keywords
error
address
register
circuit
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53127609A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5555499A (en
Inventor
Hiroyuki Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP12760978A priority Critical patent/JPS5555499A/ja
Publication of JPS5555499A publication Critical patent/JPS5555499A/ja
Publication of JPS6129024B2 publication Critical patent/JPS6129024B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
JP12760978A 1978-10-16 1978-10-16 Memory control unit Granted JPS5555499A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12760978A JPS5555499A (en) 1978-10-16 1978-10-16 Memory control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12760978A JPS5555499A (en) 1978-10-16 1978-10-16 Memory control unit

Publications (2)

Publication Number Publication Date
JPS5555499A JPS5555499A (en) 1980-04-23
JPS6129024B2 true JPS6129024B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1986-07-03

Family

ID=14964310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12760978A Granted JPS5555499A (en) 1978-10-16 1978-10-16 Memory control unit

Country Status (1)

Country Link
JP (1) JPS5555499A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07113905B2 (ja) * 1986-05-07 1995-12-06 三菱電機株式会社 主記憶制御装置
JPH02202655A (ja) * 1989-01-31 1990-08-10 Nec Corp 記憶装置
GB2289779B (en) * 1994-05-24 1999-04-28 Intel Corp Method and apparatus for automatically scrubbing ECC errors in memory via hardware
US7051264B2 (en) 2001-11-14 2006-05-23 Monolithic System Technology, Inc. Error correcting memory and method of operating same
US7392456B2 (en) 2004-11-23 2008-06-24 Mosys, Inc. Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory
FR2879337A1 (fr) * 2004-12-15 2006-06-16 St Microelectronics Sa Circuit memoire, tel que dram, comportant un mecanisme correcteur d'erreur
JP5843804B2 (ja) * 2013-03-25 2016-01-13 株式会社東芝 演算装置およびエラー処理方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5528158B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1973-01-17 1980-07-25

Also Published As

Publication number Publication date
JPS5555499A (en) 1980-04-23

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