JPS6127680A - Manufacture of semiconductor memory - Google Patents
Manufacture of semiconductor memoryInfo
- Publication number
- JPS6127680A JPS6127680A JP14917984A JP14917984A JPS6127680A JP S6127680 A JPS6127680 A JP S6127680A JP 14917984 A JP14917984 A JP 14917984A JP 14917984 A JP14917984 A JP 14917984A JP S6127680 A JPS6127680 A JP S6127680A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- silicon film
- oxygen
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000007789 gas Substances 0.000 claims abstract description 29
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 24
- 239000001301 oxygen Substances 0.000 claims abstract description 24
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 24
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 19
- 239000011261 inert gas Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 230000001590 oxidative effect Effects 0.000 claims description 10
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 20
- 230000003647 oxidation Effects 0.000 abstract description 18
- 238000001704 evaporation Methods 0.000 abstract description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract description 2
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体記憶装置の製造方法の改良に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to an improvement in a method of manufacturing a semiconductor memory device.
従来第1図図示のE P ROM (E 1ectri
callyp rogrammable Read Q
nly n+cmory)は例えば以下のようにして
製造されている。Conventionally, the E P ROM (E 1ectri) shown in FIG.
callyp programmable Read Q
nly n+cmory) is manufactured, for example, as follows.
まず、例えばP−型シリコン基板1の図示しないフィー
ルド酸化膜によって囲まれた島状の素子領域表面に第1
の酸化膜を形成した後、全面にフローティングゲ−1〜
となる第1の多結晶シリコン膜を堆積する。次に、この
第1の多結晶シリコン膜に例えばPOCj2qを拡n(
源としてリンをトープした後、その一部を選択的にエツ
チングする。First, a first layer is formed on the surface of an island-shaped element region surrounded by a field oxide film (not shown) of a P-type silicon substrate 1, for example.
After forming an oxide film, floating gates 1 to 1 are formed on the entire surface.
A first polycrystalline silicon film is deposited. Next, for example, POCj2q is expanded n(
After toping phosphorus as a source, a portion of it is selectively etched.
つづいて、例えは酸化性ガスどして酸素又は水蒸気を用
いて1000℃以下の低温酸化を行ない、第1の多結晶
シリコン膜の表面に第2の熱酸化膜を形成した後、全面
にコントロールゲートとなる第2の多結晶シリコン膜を
堆積し、不純物をドープする。次いで、写真蝕刻法によ
り第2の多結晶シリコン膜、第2の熱酸化膜、第1の多
結晶シリコン膜及び第1の熱酸化膜を順次エツチングし
て、第1のゲート酸化gI2、フローティングゲート3
、第2のゲート潴化膜4及びコントロールゲート5を形
成する。つづいて、これらをマスクとして利用し、N型
不純物、例えばAsをイオン注入する。Next, a second thermal oxide film is formed on the surface of the first polycrystalline silicon film by performing low-temperature oxidation at 1000°C or less using, for example, oxygen or water vapor as an oxidizing gas, and then controlling the entire surface. A second polycrystalline silicon film that will become a gate is deposited and doped with impurities. Next, the second polycrystalline silicon film, the second thermal oxide film, the first polycrystalline silicon film, and the first thermal oxide film are sequentially etched by photolithography to form the first gate oxide gI2 and the floating gate. 3
, a second gate barrier film 4 and a control gate 5 are formed. Next, using these as a mask, N-type impurities such as As are ion-implanted.
つづいて、熱酸化を行ない、前記コントロールゲート5
の表面、フローティングゲート3の側面及び露出した基
板1の表面に後酸化膜6を形成するとともに、前記AS
イオン注入層を活性化してN++ソース、ドレイン領域
7.8を形成する。Subsequently, thermal oxidation is performed, and the control gate 5 is
A post-oxidation film 6 is formed on the surface of the AS, the side surface of the floating gate 3, and the exposed surface of the substrate 1.
Activate the ion implantation layer to form N++ source and drain regions 7.8.
次いで、全面にパッシベーション膜としてPSG膜9を
堆積した後、このP S G 119! 9及び前記後
酸化膜6の一部を選択的にエツチングしてコンタクトホ
ール10.10を開孔し、更に全面にA1−81膜を蒸
着した後、パターニングしてソース電極11及びドレイ
ン電極12を形成してEPROMセルを製造する。Next, after depositing a PSG film 9 as a passivation film on the entire surface, this PSG 119! 9 and a part of the post-oxidized film 6 are selectively etched to form a contact hole 10.10, and then an A1-81 film is deposited on the entire surface, and then patterned to form a source electrode 11 and a drain electrode 12. forming an EPROM cell.
上述したE P ROMセルはセル1ヘランジスタのN
+型トドレイン領域8コントロールゲート5とに正の高
電圧を印加してフローティングゲート3へ電子を注入し
、書込みを行なうデバイスである。The E P ROM cell described above is
This device performs writing by applying a high positive voltage to the +-type drain region 8 and control gate 5 to inject electrons into the floating gate 3.
しかしながら、書込み後コントロールゲート5に正の高
電圧を印加すると、フローティングゲート3への注入電
子がコン1−ロールゲート5へ抜け、記憶が保持されな
い場合があるという欠点がある。However, if a high positive voltage is applied to the control gate 5 after writing, there is a drawback that the electrons injected into the floating gate 3 escape to the control gate 5 and the memory may not be retained.
これは第2のゲート酸化膜4の耐圧劣化のためであり、
その原因は以下のように考えられる。すなわち、70−
ティングゲ−1・どなる第1の多結晶シリコン膜は種々
の面方位を有するグレインから構成されているため、表
面に凹凸(surfaseaspQritV)がある。This is due to the breakdown voltage deterioration of the second gate oxide film 4.
The reason for this is thought to be as follows. That is, 70-
Since the first polycrystalline silicon film is composed of grains having various plane orientations, the surface is uneven.
これを1000℃以下の低温酸化により酸化し、第2の
ゲート酸化If! 4を形成すると、フローティングゲ
−1−3と第2のゲート酸化膜4との界面に凹凸が生し
る。これが第2のゲート酸化膜4の耐圧劣化を招くもの
である。This is oxidized by low-temperature oxidation of 1000° C. or less, and the second gate oxidation If! 4, the interface between the floating gate 1-3 and the second gate oxide film 4 becomes uneven. This causes deterioration of the breakdown voltage of the second gate oxide film 4.
このような現象は1100℃以上の高温プロセスによっ
て緩和されるが、高温プロセスは予め形成された接合の
位置を変えたり、ウェハの反りをもたらす等のため、デ
バイスの性能を劣化させ、歩留りを低下させることにな
るので有効な対策とはなりえない。This phenomenon can be alleviated by high-temperature processes of 1,100°C or higher, but high-temperature processes change the position of pre-formed bonds and cause wafer warping, which deteriorates device performance and reduces yield. This cannot be an effective countermeasure because it will cause
本発明は上記事情に鑑みてなされたものであり、デバイ
スの歩留りを低下することなく、第2のゲート酸化膜の
耐圧を向上し、記憶保持特性の良好な半導体記1g装置
を製造し得る方法を提供しようとするものである。The present invention has been made in view of the above circumstances, and provides a method for manufacturing a semiconductor memory device with good memory retention characteristics by improving the withstand voltage of the second gate oxide film without reducing the yield of the device. This is what we are trying to provide.
本発明の半導体記憶装置の製造方法は、第1導電型の半
導体基板の素子領域表面に第1の絶縁膜を形成し、全面
に不純物をドープした第1の非単結晶シリコン膜を堆積
した後、微量の酸素を含む不活性ガス中゛C熱処理し、
更に微量の酸素を含む不活性ガスを酸化性ガスに変えて
熱処理を行ない、第1の非単結晶シリコン膜の表面に第
2の絶縁膜(熱酸化膜)を形成、次いで第2の非単結晶
シリコン膜の堆積、パターニングおよび第2導電型のソ
ース、ドレイン形成を行なうことを骨子とするものであ
る。The method for manufacturing a semiconductor memory device of the present invention includes forming a first insulating film on the surface of an element region of a semiconductor substrate of a first conductivity type, and depositing a first non-monocrystalline silicon film doped with impurities over the entire surface. , C heat treatment in an inert gas containing a trace amount of oxygen,
Furthermore, heat treatment is performed by changing the inert gas containing a trace amount of oxygen to an oxidizing gas to form a second insulating film (thermal oxide film) on the surface of the first non-single crystal silicon film, and then the second non-single crystal silicon film is formed. The main points of this method are to deposit a crystalline silicon film, pattern it, and form a second conductivity type source and drain.
上述したように微量の酸素を含む不活性ガス中で熱処理
を行なうことにより、第1の非単結晶シリコン膜にドー
プされた不純物の濃度を均一にするとともに第1の非単
結晶シリコン膜中に予め存在している応力を緩和するこ
とができる。この状態を保ったまま微量の酸素を含む不
活性ガスを酸化性ガスに変えて熱処理を行なうと第1の
非単結晶シリコン膜の表面は均等に酸化され、第2の絶
縁Bl(熱酸化膜)の膜厚が均一となる。また、微量の
酸素を含む不活性カス中ての熱処理により第1の非単結
晶シリコン膜中のグレインの成長も同時に起り、この結
果表面の凹凸が少なくなっているため、酸化性ガスを用
いた低温酸化により第2の絶縁膜を形成した場合、第2
の絶縁膜と第1の非単結晶シリコン膜との界面における
凹凸を低減することができる。微量の酸素を含む不活性
ガス中での熱処理により第1の非単結晶シリコン膜の表
面に数十人の酸化膜が形成され、第1の非単結晶シリコ
ン膜の表面が荒れるのを防止するとともに第1の非単結
晶シリコン膜から不純物が蒸発するのを防止する保護膜
どなるため、第2の絶縁膜の耐圧のバラツキを低減する
ことができる。しかも、この酸化膜は極めて薄゛いため
、上述したような耐圧を改善する効果には同等悪影響を
与えない。As described above, by performing heat treatment in an inert gas containing a trace amount of oxygen, the concentration of impurities doped in the first non-single crystal silicon film is made uniform, and the concentration of impurities doped in the first non-single crystal silicon film is made uniform. Pre-existing stress can be alleviated. When heat treatment is performed by changing the inert gas containing a trace amount of oxygen to an oxidizing gas while maintaining this state, the surface of the first non-single crystal silicon film is uniformly oxidized, and the second insulating Bl (thermal oxide film ) becomes uniform in film thickness. Furthermore, grain growth in the first non-single-crystal silicon film also occurs at the same time due to the heat treatment in the inert scum containing a trace amount of oxygen, and as a result, the surface unevenness is reduced. When the second insulating film is formed by low-temperature oxidation, the second insulating film
The unevenness at the interface between the insulating film and the first non-single crystal silicon film can be reduced. Several tens of oxide films are formed on the surface of the first non-single crystal silicon film by heat treatment in an inert gas containing a trace amount of oxygen, thereby preventing the surface of the first non-single crystal silicon film from becoming rough. At the same time, since a protective film is formed to prevent impurities from evaporating from the first non-single-crystal silicon film, variations in breakdown voltage of the second insulating film can be reduced. Furthermore, since this oxide film is extremely thin, it does not have the same adverse effect on the above-mentioned effect of improving breakdown voltage.
なお、本発明において、酸化性ガスをアルゴンもしくは
窒素又はこれらの混合カスと、酸素もしくは水蒸気又は
これらの混合ガスとの混合ガスとし、酸素を微量に含む
不活性ガス中て熱処理したときの温度を維持したまま更
に酸素を微量に含む不活性ガスを酸化性ガスに変えて熱
処理を行ない、第1の非単結晶シリコン膜の表面に第2
の絶縁膜(熱酸化膜)を形成するようにすれば、酸素又
は水蒸気の分圧により第2の絶縁膜の膜厚を制御するこ
とができる。In addition, in the present invention, the oxidizing gas is a mixture of argon, nitrogen, or a mixture thereof, and oxygen, water vapor, or a mixture thereof, and the temperature when heat-treated in an inert gas containing a trace amount of oxygen is While maintaining the temperature, a heat treatment is performed by changing the inert gas containing a small amount of oxygen to an oxidizing gas, and a second layer is formed on the surface of the first non-single crystal silicon film.
If an insulating film (thermal oxide film) is formed, the thickness of the second insulating film can be controlled by the partial pressure of oxygen or water vapor.
〔発明の実施例)
以下、本発明の実施例を第2図(a)〜(f)を参照し
て説明する。[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described with reference to FIGS. 2(a) to 2(f).
まず、比抵抗10〜20Ω−cm、面方位(911)の
P−型シリコン基板21表面に通常の選択酸化技術を用
いて、膜厚1.2μmのフィールド酸化膜22を形成し
た(第2図(a)図示)。次に、熱酸化を行ない、前記
フィールド酸化膜22によって凹まれた島状の素子領域
表面に膜厚500シの第1の熱酸化膜23を形成した。First, a field oxide film 22 with a thickness of 1.2 μm was formed on the surface of a P-type silicon substrate 21 with a resistivity of 10 to 20 Ω-cm and a plane orientation (911) using a conventional selective oxidation technique (see FIG. (a) As shown). Next, thermal oxidation was performed to form a first thermal oxide film 23 with a thickness of 500 mm on the surface of the island-shaped element region recessed by the field oxide film 22.
つづいて、CVD法により全面にフローティングゲート
となる膜厚3500人の第1の多結晶シリコン膜24を
堆積した。つづいて、POC12aを拡散源として第1
の多結晶シリコン膜24にリンをドープし、ρB =
150./ロトシタ。つツイテ、1000℃、02濃度
0.’005%のArカス中において10分間アニール
を行ない、更に1000℃の温度を保ったまま前記ガス
をΔr:02−1;1の混合ガスに変えて熱酸化を行な
い、第1の多結晶シリコン膜24の表面に膜厚500人
の第2の熱酸化膜25を形成した(同図(b)図示)。Subsequently, a first polycrystalline silicon film 24 having a thickness of 3,500 wafers was deposited over the entire surface by CVD to serve as a floating gate. Next, the first
The polycrystalline silicon film 24 of is doped with phosphorus, and ρB =
150. / Rotoshita. Tweet, 1000℃, 02 concentration 0. Annealing was performed for 10 minutes in Ar gas of 0.005%, and thermal oxidation was performed by changing the gas to a mixed gas of Δr:02-1;1 while maintaining the temperature of 1000°C. A second thermal oxide film 25 having a thickness of 500 ml was formed on the surface of the film 24 (as shown in FIG. 2(b)).
次いで、全面に膜Jf 3500大1,03=20Ω/
口のコントロールゲートとなる第2の多結晶シリコン膜
26を1fflfaした。つづいて、この第2の多結晶
シリコンI]126上に写真館剣法により部分的にホト
レジストパターン27を形成した(同図(C)図示)。Next, a film Jf 3500 large 1,03 = 20Ω/
The second polycrystalline silicon film 26 serving as the control gate of the opening was 1fflfa. Subsequently, a photoresist pattern 27 was partially formed on this second polycrystalline silicon I] 126 by a photo studio technique (as shown in FIG. 1C).
次いで、このホトレジストパターン27をマスクとして
前記第2の多結晶シリコン膜26、第2の熱酸化膜25
、第1の多結晶シリコン膜24及び第1の熱酸化膜23
を順次パターニングして第1のグー1〜酸化膜28、フ
ローティングゲート29、第2のゲート酸化膜30及び
コントロールゲート31を形成した。つづいて、これら
をマスクとしてA S +をエネルギー60keV、ド
ーズ量2.5 X 10 ” ctn’の条件でイオン
注入した(同図(d)図示)。Next, using this photoresist pattern 27 as a mask, the second polycrystalline silicon film 26 and the second thermal oxide film 25 are formed.
, first polycrystalline silicon film 24 and first thermal oxide film 23
were sequentially patterned to form the first goo 1 to oxide film 28, floating gate 29, second gate oxide film 30, and control gate 31. Subsequently, using these as a mask, ions of A S + were implanted under the conditions of an energy of 60 keV and a dose of 2.5×10 ” ctn' (as shown in FIG. 4(d)).
次いで、前記ホトレジストパターン27を除去した後、
1000 ”Cて熱酸化を行ない、膜厚500人の後酸
化膜32を形成した。この際、前記Asイオン注入層が
活性化してρS −30〜40Ω/口、X j = 0
.41nrrのN+型ソース、ドレイン領域33.34
が形成された。つづいて、パッシベーション膜どして膜
厚0.8pmのPSG膜35を堆積した(同図(e)図
示)。次いて、前記PSGff!35及び後酸化Fl!
32の一部を選択的にエツチングしてコンタクトホール
36.36を開孔し、更に全面に膜厚1.0μz2?の
A℃−8i膜を堆積した後、パターニングしてソース電
極37、ドレイン電極38を形成し、EPROMセルを
製造した(同図(f)図示)。Next, after removing the photoresist pattern 27,
Thermal oxidation was carried out at 1000"C to form a post-oxide film 32 with a thickness of 500".At this time, the As ion-implanted layer was activated and ρS -30 to 40Ω/gate, X j = 0.
.. 41nrr N+ type source and drain regions 33.34
was formed. Subsequently, a PSG film 35 having a thickness of 0.8 pm was deposited as a passivation film (as shown in FIG. 2(e)). Next, the PSGff! 35 and post-oxidation Fl!
Contact holes 36 and 36 are formed by selectively etching a part of 32, and then a film thickness of 1.0 μz2? is applied to the entire surface. After depositing an A.degree. C.-8i film, it was patterned to form a source electrode 37 and a drain electrode 38, thereby manufacturing an EPROM cell (as shown in FIG. 2(f)).
しかして、本発明方法によれば、第2図(b)の工程で
POCff:+を拡散源として第1の多結晶シリコン膜
24にリンをドープした後、1000℃、02 ′al
f0.00596(7)A I−カス中ニオイア 10
分間アニールを行ない、更に1000’Cの温度を維持
したまま前記ガスをAr +02 =1 : 1の混合
ガスに変えて熱波化(稀釈酸化)を行なうことにより第
2の熱酸化膜25を形成しているので、第2の熱酸化1
15!25の膜厚の均一化、第2の熱酸化膜25と第1
の多結晶シリコン膜24との界面の凹凸の低減及び第1
の多結晶シリコン膜24からの不純物の蒸光の防止によ
り第2の熱酸化1!25の耐圧を著しく向上できるとと
もに耐圧のバラツキを低減することができる。According to the method of the present invention, after doping the first polycrystalline silicon film 24 with phosphorus using POCff:+ as a diffusion source in the step shown in FIG.
f0.00596 (7) A I-Nioia in waste 10
The second thermal oxide film 25 is formed by annealing for a minute, and then changing the gas to a mixed gas of Ar +02 = 1:1 while maintaining the temperature of 1000'C and performing thermal wave treatment (dilution oxidation). Therefore, the second thermal oxidation 1
15! Uniform film thickness of 25, second thermal oxide film 25 and first
Reduction of unevenness at the interface with the polycrystalline silicon film 24 and the first
By preventing evaporation of impurities from the polycrystalline silicon film 24, the withstand voltage of the second thermal oxidation 1!25 can be significantly improved, and variations in the withstand voltage can be reduced.
例えば、第3図(a)に従来のように通常の熱酸化を行
なった場合の第2の熱酸化膜の耐圧を、また同図(b)
に上記実施例の場合の第2の熱酸化膜の耐圧をそれぞれ
示す。これらの図から明らかなように上記実施例の方法
で形成された第2の熱酸化膜の方が耐圧が著しく向上し
、しかも耐圧のバラツキも極めて小さい。この結果、第
2図(f)図示のEPROMセルに書込み後、コントロ
ールゲート31に正の高電圧を印加しても記憶を良好に
保持することができる。また、低温プロセスを採用して
いるので、ウェハの反り等が発生して半導体メモリデバ
イスの歩留りが低下するという問題は生じない。For example, Fig. 3(a) shows the breakdown voltage of the second thermal oxide film when conventional thermal oxidation is performed, and Fig. 3(b) shows the breakdown voltage of the second thermal oxide film.
The breakdown voltages of the second thermal oxide film in the case of the above embodiment are shown in FIG. As is clear from these figures, the second thermal oxide film formed by the method of the above embodiment has a significantly improved breakdown voltage, and the variation in breakdown voltage is also extremely small. As a result, even if a positive high voltage is applied to the control gate 31 after writing to the EPROM cell shown in FIG. 2(f), the memory can be maintained well. Furthermore, since a low-temperature process is employed, there is no problem that the yield of semiconductor memory devices decreases due to wafer warping or the like.
なお、上記実施例では重量の酸素を含む不活性ガスとし
て0211度0.005%のArガスを用いたが、不活
性ガスとして窒素又はアルゴンと窒素との混合ガスを用
いてもよい。また、第4図に示すArガス中の酸素濃度
と第2の熱酸化膜の耐圧との関係かられかるように酸素
濃度が10%を超えると耐圧が劣化するので、不活性ガ
ス中の酸素濃度は10%以下であることが望ましい。In the above embodiment, Ar gas of 0.0211°C and 0.005% was used as the inert gas containing oxygen by weight, but nitrogen or a mixed gas of argon and nitrogen may be used as the inert gas. Furthermore, as shown in the relationship between the oxygen concentration in the Ar gas and the breakdown voltage of the second thermal oxide film shown in Fig. 4, if the oxygen concentration exceeds 10%, the breakdown voltage deteriorates. The concentration is preferably 10% or less.
また、上記実施例では酸化性ガスとしてAr:02=1
:1の混合ガスを用いたが、これに限らずアルゴンもし
くは窒素又はこれらの混合ガスと、酸素もしくは水蒸気
又はこれらの混合ガスとの混合ガス′を用いることがで
きる。また、上記実施例のように微量の酸素を含む不活
性ガスによる熱処理の温度を維持したまま酸化性ガスに
より熱酸化を行なう場合には、酸素又は水蒸気の分圧を
設定することによって第2の熱酸化膜の膜厚を制御する
ことができるので望ましい。In addition, in the above embodiment, Ar:02=1 as the oxidizing gas
Although a mixed gas of 1:1 was used, the present invention is not limited thereto, and a mixed gas of argon, nitrogen, or a mixed gas thereof, and oxygen, water vapor, or a mixed gas thereof may also be used. In addition, when performing thermal oxidation with an oxidizing gas while maintaining the temperature of the heat treatment with an inert gas containing a trace amount of oxygen as in the above example, the partial pressure of oxygen or water vapor can be set to This is desirable because the thickness of the thermal oxide film can be controlled.
更に、上記実施例ではフローティンググーh 29及び
コントロールゲート31の材料として多結晶シリコンを
用いたが、これ゛に限らず非晶質シリコンを用いてもよ
い。Further, in the above embodiment, polycrystalline silicon is used as the material for the floating group h29 and the control gate 31, but the material is not limited to this, and amorphous silicon may also be used.
以上詳述した如く本発明の半導体記憶装置の製造方法に
よれば、従来のプロセスを大幅に変更する必要がなく、
コストアップやデバイスの歩留り低下を招くことなしに
第2のゲート酸化膜の耐圧の向上した記憶保持特性の良
好な半導体記憶装置を製造できるものである。As detailed above, according to the method of manufacturing a semiconductor memory device of the present invention, there is no need to significantly change the conventional process.
A semiconductor memory device with improved memory retention characteristics and improved breakdown voltage of the second gate oxide film can be manufactured without increasing costs or reducing device yield.
第1図は従来のEPROMセルの断面図、第2図(a)
〜(f)は本発明の実施例におけるEPROMセルの1
!!造方法を示す断面図、第3図(a)は従来の方法に
より形成された第2の熱酸化膜の耐圧のヒストグラム、
同図(b)は本発明の実施例の方法により形成された第
2の熱酸化膜の耐圧のヒストグラム、第4図はアルゴン
ガス中の酸素濃度と第2の熱酸化膜の耐圧との関係を示
す特性図である。
21・・・P−型シリコン基板、22・・・フィールド
酸化膜、23・・・第1の熱酸化膜、24・・・第1の
多結晶シリコン膜、25・・・第2の熱酸化膜、26・
・・第2の多結晶シリコン膜、27・・・ホトレジスト
パターン、28・・・第1のゲート酸化膜、29・・・
フローティングゲート、30・・・第2のゲート酸化膜
、31・・・コントロールゲート、32・・・後酸化躾
、33.34・・・N+型ソース、ドレイン領域、35
・・・PSG膜、36・・・コンタクトホール、37・
・・ソース電極、38・・・ドレイン電極。
出願人代理人 弁理士 鈴江武彦
第1図
s2図
第2図Figure 1 is a cross-sectional view of a conventional EPROM cell, Figure 2 (a)
~(f) is one of the EPROM cells in the embodiment of the present invention
! ! 3(a) is a histogram of breakdown voltage of the second thermal oxide film formed by the conventional method,
Figure 4 (b) is a histogram of the breakdown voltage of the second thermal oxide film formed by the method of the embodiment of the present invention, and Figure 4 is the relationship between the oxygen concentration in argon gas and the breakdown voltage of the second thermal oxide film. FIG. 21... P-type silicon substrate, 22... Field oxide film, 23... First thermal oxide film, 24... First polycrystalline silicon film, 25... Second thermal oxidation membrane, 26.
...Second polycrystalline silicon film, 27...Photoresist pattern, 28...First gate oxide film, 29...
Floating gate, 30... Second gate oxide film, 31... Control gate, 32... Post oxidation control, 33. 34... N+ type source, drain region, 35
...PSG film, 36...contact hole, 37.
... Source electrode, 38... Drain electrode. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure s2 Figure 2
Claims (5)
絶縁膜を形成した後、全面に不純物をドープした第1の
非単結晶シリコン膜を堆積する工程と、微量の酸素を含
む不活性ガス中で熱処理し、更に微量の酸素を含む不活
性ガスを酸化性ガスに変えて熱処理を行ない、該第1の
非単結晶シリコン膜の表面に第2の絶縁膜を形成する工
程と、全面に第2の非単結晶シリコン膜を堆積する工程
と、これら第2の非単結晶シリコン膜、第2の絶縁膜、
第1の非単結晶シリコン膜及び第1の絶縁膜を順次パタ
ーニングする工程と、これらのパターンをマスクとして
第2導電型の不純物をイオン注入して第2導電型のソー
ス、ドレイン領域を形成する工程とを具備したことを特
徴とする半導体記憶装置の製造方法。(1) After forming a first insulating film on the surface of an element region of a semiconductor substrate of a first conductivity type, a step of depositing a first non-single-crystal silicon film doped with impurities on the entire surface and containing a trace amount of oxygen. forming a second insulating film on the surface of the first non-single crystal silicon film by performing heat treatment in an inert gas and further performing heat treatment by changing the inert gas containing a trace amount of oxygen to an oxidizing gas; , a step of depositing a second non-single crystal silicon film on the entire surface, and a step of depositing a second non-single crystal silicon film, a second insulating film,
A process of sequentially patterning the first non-single crystal silicon film and the first insulating film, and using these patterns as a mask, ion implantation of second conductivity type impurities is performed to form second conductivity type source and drain regions. A method of manufacturing a semiconductor memory device, comprising the steps of:
ィングゲート、第2の非単結晶シリコン膜のパターンを
コントロールゲートとする特許請求の範囲第1項記載の
半導体記憶装置の製造方法。(2) The method of manufacturing a semiconductor memory device according to claim 1, wherein the pattern of the first non-single crystal silicon film is a floating gate, and the pattern of the second non-single crystal silicon film is a control gate.
混合ガスである特許請求の範囲第1項記載の半導体記憶
装置の製造方法。(3) The method for manufacturing a semiconductor memory device according to claim 1, wherein the inert gas is argon, nitrogen, or a mixed gas thereof.
混合ガスと、酸素もしくは水蒸気又はこれらの混合ガス
との混合ガスである特許請求の範囲第1項記載の半導体
記憶装置の製造方法。(4) The method for manufacturing a semiconductor memory device according to claim 1, wherein the oxidizing gas is a mixed gas of argon, nitrogen, or a mixture thereof, and oxygen, water vapor, or a mixture thereof.
熱処理の温度を維持したまま更に酸素を微量に含む不活
性ガスを酸化性ガスに変えて熱処理を行ない、第1の非
単結晶シリコン膜の表面に第2の絶縁膜を形成する特許
請求の範囲第1項記載の半導体記憶装置の製造方法。(5) Heat treatment is performed in an inert gas containing a trace amount of oxygen, and while maintaining this heat treatment temperature, further heat treatment is performed by changing the inert gas containing a trace amount of oxygen to an oxidizing gas, and the first non-single crystal is formed. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein a second insulating film is formed on the surface of the silicon film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14917984A JPS6127680A (en) | 1984-07-18 | 1984-07-18 | Manufacture of semiconductor memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14917984A JPS6127680A (en) | 1984-07-18 | 1984-07-18 | Manufacture of semiconductor memory |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6127680A true JPS6127680A (en) | 1986-02-07 |
JPS6311785B2 JPS6311785B2 (en) | 1988-03-16 |
Family
ID=15469521
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14917984A Granted JPS6127680A (en) | 1984-07-18 | 1984-07-18 | Manufacture of semiconductor memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6127680A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS631076A (en) * | 1986-06-20 | 1988-01-06 | Toshiba Corp | Manufacture of semiconductor memory device |
JPH03205411A (en) * | 1989-05-30 | 1991-09-06 | Asahi Chem Ind Co Ltd | Thermoplastic copolymer, its production and thermoplastic resin composition containing same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5591877A (en) * | 1978-12-30 | 1980-07-11 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS56161646A (en) * | 1980-05-19 | 1981-12-12 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1984
- 1984-07-18 JP JP14917984A patent/JPS6127680A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5591877A (en) * | 1978-12-30 | 1980-07-11 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS56161646A (en) * | 1980-05-19 | 1981-12-12 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS631076A (en) * | 1986-06-20 | 1988-01-06 | Toshiba Corp | Manufacture of semiconductor memory device |
JPH03205411A (en) * | 1989-05-30 | 1991-09-06 | Asahi Chem Ind Co Ltd | Thermoplastic copolymer, its production and thermoplastic resin composition containing same |
Also Published As
Publication number | Publication date |
---|---|
JPS6311785B2 (en) | 1988-03-16 |
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