JPS6127680A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the dielectric strength of a second gate oxide film and a memory holding characteristic by carrying out thermal treatment in an inactive gas containing a little amount of oxygen to form a very thin oxide film on the surface of a first non-crystalline silicon film and preventing evaporation of impurities. CONSTITUTION:A field oxide film 22 and a first thermal oxide film 23 are formed on the surface of a P<-> type silicon substrate 21. A first polycrystalline silicon film 24 is deposited and annealed in Ar gas having O2 of 0.005% concentration. Furthermore, the gas is replaced by a mixed gas having the ratio of Ar to O2 equal to 1:1 and the film 24 is subjected to thermal oxidation therein to form a second thermal oxide film 25. A second polycrystalline silicon film 26 is deposited on the film 25 and subjected to patterning using a mask 27 to form a floating gate 29, a second gate oxide film 30 and a control gate 31. After As<+> ion is injected into the control gate 31 and subjected to thermal oxidation, an oxide film 32 and N<+> type source and drain regions 33 and 34 are formed and a PSG film 35, a source electrode 37 and a drain electrode 38 are formed, thereby to obtain an EPROM cell.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to an improvement in a method of manufacturing a semiconductor memory device.

[Technical background of the invention and its problems]

Conventionally, the E P ROM (E 1ectri) shown in FIG.
callyp programmable Read Q
nly n+cmory) is manufactured, for example, as follows.

First, a first layer is formed on the surface of an island-shaped element region surrounded by a field oxide film (not shown) of a P-type silicon substrate 1, for example.
After forming an oxide film, floating gates 1 to 1 are formed on the entire surface.
A first polycrystalline silicon film is deposited. Next, for example, POCj2q is expanded n(
After toping phosphorus as a source, a portion of it is selectively etched.

Next, a second thermal oxide film is formed on the surface of the first polycrystalline silicon film by performing low-temperature oxidation at 1000°C or less using, for example, oxygen or water vapor as an oxidizing gas, and then controlling the entire surface. A second polycrystalline silicon film that will become a gate is deposited and doped with impurities. Next, the second polycrystalline silicon film, the second thermal oxide film, the first polycrystalline silicon film, and the first thermal oxide film are sequentially etched by photolithography to form the first gate oxide gI2 and the floating gate. 3
, a second gate barrier film 4 and a control gate 5 are formed. Next, using these as a mask, N-type impurities such as As are ion-implanted.

Subsequently, thermal oxidation is performed, and the control gate 5 is
A post-oxidation film 6 is formed on the surface of the AS, the side surface of the floating gate 3, and the exposed surface of the substrate 1.
Activate the ion implantation layer to form N++ source and drain regions 7.8.

Next, after depositing a PSG film 9 as a passivation film on the entire surface, this PSG 119! 9 and a part of the post-oxidized film 6 are selectively etched to form a contact hole 10.10, and then an A1-81 film is deposited on the entire surface, and then patterned to form a source electrode 11 and a drain electrode 12. forming an EPROM cell.

The E P ROM cell described above is
This device performs writing by applying a high positive voltage to the +-type drain region 8 and control gate 5 to inject electrons into the floating gate 3.

However, if a high positive voltage is applied to the control gate 5 after writing, there is a drawback that the electrons injected into the floating gate 3 escape to the control gate 5 and the memory may not be retained.

This is due to the breakdown voltage deterioration of the second gate oxide film 4.
The reason for this is thought to be as follows. That is, 70-
Since the first polycrystalline silicon film is composed of grains having various plane orientations, the surface is uneven.

This is oxidized by low-temperature oxidation of 1000° C. or less, and the second gate oxidation If! 4, the interface between the floating gate 1-3 and the second gate oxide film 4 becomes uneven. This causes deterioration of the breakdown voltage of the second gate oxide film 4.

This phenomenon can be alleviated by high-temperature processes of 1,100°C or higher, but high-temperature processes change the position of pre-formed bonds and cause wafer warping, which deteriorates device performance and reduces yield. This cannot be an effective countermeasure because it will cause

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and provides a method for manufacturing a semiconductor memory device with good memory retention characteristics by improving the withstand voltage of the second gate oxide film without reducing the yield of the device. This is what we are trying to provide.

[Summary of the invention]

The method for manufacturing a semiconductor memory device of the present invention includes forming a first insulating film on the surface of an element region of a semiconductor substrate of a first conductivity type, and depositing a first non-monocrystalline silicon film doped with impurities over the entire surface. , C heat treatment in an inert gas containing a trace amount of oxygen,
Furthermore, heat treatment is performed by changing the inert gas containing a trace amount of oxygen to an oxidizing gas to form a second insulating film (thermal oxide film) on the surface of the first non-single crystal silicon film, and then the second non-single crystal silicon film is formed. The main points of this method are to deposit a crystalline silicon film, pattern it, and form a second conductivity type source and drain.

As described above, by performing heat treatment in an inert gas containing a trace amount of oxygen, the concentration of impurities doped in the first non-single crystal silicon film is made uniform, and the concentration of impurities doped in the first non-single crystal silicon film is made uniform. Pre-existing stress can be alleviated. When heat treatment is performed by changing the inert gas containing a trace amount of oxygen to an oxidizing gas while maintaining this state, the surface of the first non-single crystal silicon film is uniformly oxidized, and the second insulating Bl (thermal oxide film ) becomes uniform in film thickness. Furthermore, grain growth in the first non-single-crystal silicon film also occurs at the same time due to the heat treatment in the inert scum containing a trace amount of oxygen, and as a result, the surface unevenness is reduced. When the second insulating film is formed by low-temperature oxidation, the second insulating film
The unevenness at the interface between the insulating film and the first non-single crystal silicon film can be reduced. Several tens of oxide films are formed on the surface of the first non-single crystal silicon film by heat treatment in an inert gas containing a trace amount of oxygen, thereby preventing the surface of the first non-single crystal silicon film from becoming rough. At the same time, since a protective film is formed to prevent impurities from evaporating from the first non-single-crystal silicon film, variations in breakdown voltage of the second insulating film can be reduced. Furthermore, since this oxide film is extremely thin, it does not have the same adverse effect on the above-mentioned effect of improving breakdown voltage.

In addition, in the present invention, the oxidizing gas is a mixture of argon, nitrogen, or a mixture thereof, and oxygen, water vapor, or a mixture thereof, and the temperature when heat-treated in an inert gas containing a trace amount of oxygen is While maintaining the temperature, a heat treatment is performed by changing the inert gas containing a small amount of oxygen to an oxidizing gas, and a second layer is formed on the surface of the first non-single crystal silicon film.
If an insulating film (thermal oxide film) is formed, the thickness of the second insulating film can be controlled by the partial pressure of oxygen or water vapor.

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described with reference to FIGS. 2(a) to 2(f).

First, a field oxide film 22 with a thickness of 1.2 μm was formed on the surface of a P-type silicon substrate 21 with a resistivity of 10 to 20 Ω-cm and a plane orientation (911) using a conventional selective oxidation technique (see FIG. (a) As shown). Next, thermal oxidation was performed to form a first thermal oxide film 23 with a thickness of 500 mm on the surface of the island-shaped element region recessed by the field oxide film 22.

Subsequently, a first polycrystalline silicon film 24 having a thickness of 3,500 wafers was deposited over the entire surface by CVD to serve as a floating gate. Next, the first
The polycrystalline silicon film 24 of is doped with phosphorus, and ρB =
150. / Rotoshita. Tweet, 1000℃, 02 concentration 0. Annealing was performed for 10 minutes in Ar gas of 0.005%, and thermal oxidation was performed by changing the gas to a mixed gas of Δr:02-1;1 while maintaining the temperature of 1000°C. A second thermal oxide film 25 having a thickness of 500 ml was formed on the surface of the film 24 (as shown in FIG. 2(b)).

Next, a film Jf 3500 large 1,03 = 20Ω/
The second polycrystalline silicon film 26 serving as the control gate of the opening was 1fflfa. Subsequently, a photoresist pattern 27 was partially formed on this second polycrystalline silicon I] 126 by a photo studio technique (as shown in FIG. 1C).

Next, using this photoresist pattern 27 as a mask, the second polycrystalline silicon film 26 and the second thermal oxide film 25 are formed.
, first polycrystalline silicon film 24 and first thermal oxide film 23
were sequentially patterned to form the first goo 1 to oxide film 28, floating gate 29, second gate oxide film 30, and control gate 31. Subsequently, using these as a mask, ions of A S + were implanted under the conditions of an energy of 60 keV and a dose of 2.5×10 ” ctn' (as shown in FIG. 4(d)).

Next, after removing the photoresist pattern 27,
Thermal oxidation was carried out at 1000"C to form a post-oxide film 32 with a thickness of 500".At this time, the As ion-implanted layer was activated and ρS -30 to 40Ω/gate, X j = 0.
．． 41nrr N+ type source and drain regions 33.34
was formed. Subsequently, a PSG film 35 having a thickness of 0.8 pm was deposited as a passivation film (as shown in FIG. 2(e)). Next, the PSGff! 35 and post-oxidation Fl!
Contact holes 36 and 36 are formed by selectively etching a part of 32, and then a film thickness of 1.0 μz2? is applied to the entire surface. After depositing an A.degree. C.-8i film, it was patterned to form a source electrode 37 and a drain electrode 38, thereby manufacturing an EPROM cell (as shown in FIG. 2(f)).

According to the method of the present invention, after doping the first polycrystalline silicon film 24 with phosphorus using POCff:+ as a diffusion source in the step shown in FIG.
f0.00596 (7) A I-Nioia in waste 10
The second thermal oxide film 25 is formed by annealing for a minute, and then changing the gas to a mixed gas of Ar +02 = 1:1 while maintaining the temperature of 1000'C and performing thermal wave treatment (dilution oxidation). Therefore, the second thermal oxidation 1
15! Uniform film thickness of 25, second thermal oxide film 25 and first
Reduction of unevenness at the interface with the polycrystalline silicon film 24 and the first
By preventing evaporation of impurities from the polycrystalline silicon film 24, the withstand voltage of the second thermal oxidation 1!25 can be significantly improved, and variations in the withstand voltage can be reduced.

For example, Fig. 3(a) shows the breakdown voltage of the second thermal oxide film when conventional thermal oxidation is performed, and Fig. 3(b) shows the breakdown voltage of the second thermal oxide film.
The breakdown voltages of the second thermal oxide film in the case of the above embodiment are shown in FIG. As is clear from these figures, the second thermal oxide film formed by the method of the above embodiment has a significantly improved breakdown voltage, and the variation in breakdown voltage is also extremely small. As a result, even if a positive high voltage is applied to the control gate 31 after writing to the EPROM cell shown in FIG. 2(f), the memory can be maintained well. Furthermore, since a low-temperature process is employed, there is no problem that the yield of semiconductor memory devices decreases due to wafer warping or the like.

In the above embodiment, Ar gas of 0.0211°C and 0.005% was used as the inert gas containing oxygen by weight, but nitrogen or a mixed gas of argon and nitrogen may be used as the inert gas. Furthermore, as shown in the relationship between the oxygen concentration in the Ar gas and the breakdown voltage of the second thermal oxide film shown in Fig. 4, if the oxygen concentration exceeds 10%, the breakdown voltage deteriorates. The concentration is preferably 10% or less.

In addition, in the above embodiment, Ar:02=1 as the oxidizing gas
Although a mixed gas of 1:1 was used, the present invention is not limited thereto, and a mixed gas of argon, nitrogen, or a mixed gas thereof, and oxygen, water vapor, or a mixed gas thereof may also be used. In addition, when performing thermal oxidation with an oxidizing gas while maintaining the temperature of the heat treatment with an inert gas containing a trace amount of oxygen as in the above example, the partial pressure of oxygen or water vapor can be set to This is desirable because the thickness of the thermal oxide film can be controlled.

Further, in the above embodiment, polycrystalline silicon is used as the material for the floating group h29 and the control gate 31, but the material is not limited to this, and amorphous silicon may also be used.

〔Effect of the invention〕

As detailed above, according to the method of manufacturing a semiconductor memory device of the present invention, there is no need to significantly change the conventional process.
A semiconductor memory device with improved memory retention characteristics and improved breakdown voltage of the second gate oxide film can be manufactured without increasing costs or reducing device yield.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional EPROM cell, Figure 2 (a)
~(f) is one of the EPROM cells in the embodiment of the present invention
! ! 3(a) is a histogram of breakdown voltage of the second thermal oxide film formed by the conventional method,
Figure 4 (b) is a histogram of the breakdown voltage of the second thermal oxide film formed by the method of the embodiment of the present invention, and Figure 4 is the relationship between the oxygen concentration in argon gas and the breakdown voltage of the second thermal oxide film. FIG. 21... P-type silicon substrate, 22... Field oxide film, 23... First thermal oxide film, 24... First polycrystalline silicon film, 25... Second thermal oxidation membrane, 26.
...Second polycrystalline silicon film, 27...Photoresist pattern, 28...First gate oxide film, 29...
Floating gate, 30... Second gate oxide film, 31... Control gate, 32... Post oxidation control, 33. 34... N+ type source, drain region, 35
...PSG film, 36...contact hole, 37.
... Source electrode, 38... Drain electrode. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure s2 Figure 2

Claims (5)

[Claims] (1) After forming a first insulating film on the surface of an element region of a semiconductor substrate of a first conductivity type, a step of depositing a first non-single-crystal silicon film doped with impurities on the entire surface and containing a trace amount of oxygen. forming a second insulating film on the surface of the first non-single crystal silicon film by performing heat treatment in an inert gas and further performing heat treatment by changing the inert gas containing a trace amount of oxygen to an oxidizing gas; , a step of depositing a second non-single crystal silicon film on the entire surface, and a step of depositing a second non-single crystal silicon film, a second insulating film,
A process of sequentially patterning the first non-single crystal silicon film and the first insulating film, and using these patterns as a mask, ion implantation of second conductivity type impurities is performed to form second conductivity type source and drain regions. A method of manufacturing a semiconductor memory device, comprising the steps of: (2) The method of manufacturing a semiconductor memory device according to claim 1, wherein the pattern of the first non-single crystal silicon film is a floating gate, and the pattern of the second non-single crystal silicon film is a control gate. (3) The method for manufacturing a semiconductor memory device according to claim 1, wherein the inert gas is argon, nitrogen, or a mixed gas thereof. (4) The method for manufacturing a semiconductor memory device according to claim 1, wherein the oxidizing gas is a mixed gas of argon, nitrogen, or a mixture thereof, and oxygen, water vapor, or a mixture thereof. (5) Heat treatment is performed in an inert gas containing a trace amount of oxygen, and while maintaining this heat treatment temperature, further heat treatment is performed by changing the inert gas containing a trace amount of oxygen to an oxidizing gas, and the first non-single crystal is formed. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein a second insulating film is formed on the surface of the silicon film.