JPH0492463A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain high integration easily obtainable a high resistance value by a method wherein a high resistance element consists of a multilayered film by vapor growth of different specific resistance and electrode leading-out is performed so as to constitute resistance intervals to the growth direction of a multilayered film. CONSTITUTION:Ions of boron are implanted into an N-type silicon substance 11 of a specific resistance 10OMEGAcm to form a P-well layer 12 by high temperature drive in and to form a field insulating film 13 and a gate oxide film 14 by selective oxidation followed by forming a gate electrode 15 of a polycrystalline silicon film. Next, after oxidation treatment of the surface of the gate electrode 15, a silicon oxide film given gaseous reaction is made to grow for being made a first interlayer insulating film 19. Next, a through-hole is provided and a resistance thin film is made to grow so as to be made a high-resistance electrode 25. After forming a silicon-rich film nitride and growing an N-polycrystalline silicon film, a multilayered film having a different condition is made to grow. This multilayered film has specific resistance of the upper and lower layers is several hundred KOMEGAcm. Next, a contact hole is opened from the high-resistance element to form a passivation film 24 and to open a pad part for taking off an outer electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microscopic semiconductor device to which a high resistance element is applied.

[Summary of the invention]

The present invention relates to a semiconductor device, particularly a high resistance load type STATEC R.
A M (Random Access Memory
) etc., it is aimed at stably securing the resistance value of the high resistance, improving electrical characteristics and manufacturing yield, and increasing integration.
Conventionally, a semiconductor device such as a high-resistance load type static RAM, for example, uses an NchMO3) run transistor 3 as shown in FIG.
2 and a high resistance element 31 made of a polycrystalline silicon film, the manufacturing method thereof is, for example, as shown in FIG.
Then, a field insulating film 13 is formed by selective oxidation or the like, and a gate oxide film 14, a gate electrode 15, and a gate electrode 15 are formed in the active region.
Furthermore, LDD (
Lightly doped drain) and D D
D (double dlrfused drain)
For example, phosphorus is ion-implanted to form a low concentration impurity layer 16 for the drain and source so as to form a structure. Next, arsenic is ion-implanted through the sidewall spacer 17 formed by etching back the vapor-phase grown silicon oxide film to form the source and drain regions of the high concentration impurity layer 18, and then the vapor-grown silicon oxide film is etched back. The first interlayer insulating film 19 becomes
(Fig. 2(a)). Next, after opening a hole in the required area from the element, a polycrystalline silicon film made by thermally decomposing SiH4 under reduced pressure is grown in about 4,000 layers, and then photoetched to form a film with a length of 8 to 12 μm and a width of about 0.8 μm. A high resistance element 20 region is formed, and impurities are diffused into a desired region of the electrode extension portion (FIG. 2(b)). Subsequently, second and third interlayer insulating films 21 and 22 made of a vapor phase grown silicon oxide film (NSC) and PSG or BPSG films containing phosphorus, boron, etc. are laminated and reflow etc. are performed at 950 to 1050°C. . The second interlayer insulating film 21 is made of PSG, BPS
This is to prevent diffusion of impurities from the G film. Next, after opening a contact hole for taking out the electrode, AJ gold alloy sputtering was performed, and metal wiring 23 was formed by selective etching.
After forming and sintering in an atmosphere containing N2, an NSG film, a PSG film, or a plasma silicon nitride film is laminated as a passivation film 24 (FIG. 2(C)).

[Problem to be solved by the invention]

However, in the conventional technology, the high resistance element 20 is made of Si.
H4 or a polycrystalline silicon film that is introduced into a reduced pressure chamber as a carrier of N2, He, or N2 and thermally decomposed at 550 to 650°C is used, but the resistivity is only a few hundred ohms at most. I can only get it. Therefore, to lower the standby current of the stattake RAM, 5006~
A stable resistance value on the order of ITΩ is required, and therefore the shape pattern of the high resistance element must be long as described above, which has been an obstacle to fine integration.

However, the present invention is intended to solve these problems, to easily obtain a high resistance value, and to increase the degree of integration of semiconductor devices.

[Failure to solve the problem]

The semiconductor device of the present invention is a semiconductor device to which a high-resistance element is applied, in which the high-resistance element is a laminated film grown by vapor phase growth with different specific resistances, and a resistance interval is formed in the growth direction of the laminated film. The feature is that the electrodes are drawn out in such a way that the

〔Example〕

As an embodiment of the present invention, in the peripheral CMO3, the cells are Nch
MOS transistor and high resistance load type static RA
The process by which M was manufactured will be explained in detail with reference to FIG. Boron ions are implanted onto an N-type silicon substrate 11 with a specific resistance of 10Ω (7), a P-well layer 12 is formed by high-temperature drive-in, and a field insulating film 13 is formed by selective oxidation.
After forming the gate oxide film 14, channel doping etc. are performed by ion implantation to adjust the threshold voltage, and then
A gate electrode 15 of polycrystalline silicon film was formed.

A low concentration impurity layer 16 in which phosphorus is ion-implanted for Nch and boron is ion-implanted for Pch, and As is 5X for Nch into high concentration impurity layer 18 of the source and drain via a spacer 17 of silicon oxide film subjected to vapor phase reaction. 1.0”am-
2. Pch is ion implanted with BF2 of 3×10” (to). Next, the surface of the gate electrode 15 is oxidized at 850°C, and a silicon oxide film of 200 OA is grown by vapor phase reaction. An interlayer insulating film 19 was formed (FIG. 1(a)).

Next, a through hole with a diameter of 0.8 μm was provided, and the high resistance element 2
A resistive thin film of No. 5 was grown. This thin film growth was performed by first introducing SiH4 into a parallel plate vacuum chamber, and then
After applying a high frequency of 13.56 MHz at 380° C. to form a polycrystalline silicon film, NH3 was added at a rate of about 20 cc/min for 40 seconds to form a silicon-rich nitride film, and then the introduction of NH3 was stopped. After growing a polycrystalline silicon film for 30 seconds, the high frequency was stopped and a total of 250 OA of laminated films under different conditions were grown. This laminated thin film has a specific resistance of several hundred KQc for the upper and lower layers when evaluated individually on a monitor.
The refractive index of yn is about 2.9, and the intermediate layer of NH is 1.
The refractive index was approximately 2.45 at the 5 MΩ mark.

This value can be controlled by changing the partial pressure of NH3. Next, the laminated film was dry-etched using a mixed gas containing CF4 using the photoresist as a mask.
The high resistance element 25 with a μm diameter is patterned. (Figure 1(b)). Next, an interlayer insulating film 22 made of a vapor-grown BPSG film is laminated and reflowed at 900°C, and a contact hole is opened from the high resistance element.
The alloy was sputtered and patterned into a desired shape using photolithography, and then dry etched with a gas containing CΩ2 to form metal wiring 23. Thereafter, a passivation film 24 was laminated, and a hole was opened in the butt part for taking out the external electrode (FIG. 1(C)).

The resistance value of the high-resistance element of the semiconductor device manufactured in the above manner can now be stably obtained at about 1.5 TΩ. Conventionally, the high-resistance element obtained high resistance with a single layer of polycrystalline silicon film. Although it required a long route, it was possible to reduce the number to about 115.

Furthermore, in the past, since non-doped polycrystalline silicon regions were formed in the lateral direction, it was not possible to directly stack a PSG or BPSG film on top of this high-resistance element, and it was necessary to lay an NSC film underneath. However, with the structure of the present invention, it can be directly laminated on the surface of a high-resistance element and serve as a source of impurities, and the thin film doped with NH3 in the intermediate layer serves as a diffusion barrier for phosphorus and other substances, and will continue to be used in the process. Simplification was achieved.

In addition, when forming a thin film to become a high resistance element, experiments were conducted using N20.02.03 instead of NH3, and Si2H6 or 5i(CO2H1)4 instead of SiH4, but high resistance was obtained. The value could be controlled by changing pressure, temperature, and time, and a similar device effect was achieved.

Further, the present invention is not limited to MO5SCMO5-LSI, but also B
It can also be applied to i-CMO5IC, and high-resistance multilayer film growth can be performed not only in a plasma furnace but also in a reduced-pressure pyrolysis furnace. It can also be applied to its silicide and polycide structures.

〔Effect of the invention〕

As described above, according to the present invention, the high resistance element is changed from a single layer structure of polycrystalline silicon to a vapor phase laminated film including a high resistance thin film,
By setting the electrode spacing in the stacking direction, the resistance value of the high-resistance element can be easily secured, contributing to stabilization of electrical characteristics, process simplification, and stable supply of integrated fine semiconductor devices. ′

[Brief explanation of drawings]

FIGS. 1(a) to 1(c) are schematic cross-sectional views showing one embodiment of manufacturing a semiconductor device according to the present invention. FIGS. 2(a) to 2(c) are schematic cross-sectional views showing the manufacturing process of a conventional semiconductor device. FIG. 3 is a circuit block diagram of a memory cell. 11 ・ ・ ・ ・ 12 ・ ・ ・ ・ 13 ・ ・ φ ・ 14 ・ ・ ・ 15・ ・ ・ 16 ・ ・ ・ ・ 17 .22φ 23 ・ ・ ・ ・ 24 ・ ・ ・ ・ Silicon substrate P-well layer Field insulation film Gate oxide film Gate electrode Low concentration impurity layer Spacer High concentration impurity layer First interlayer insulation film High resistance element Interlayer insulation film Metal wiring passivation film More than one sword

Claims (1)

[Claims] In a semiconductor device to which a high-resistance element is applied, the high-resistance element is a laminated film grown by vapor phase growth with different specific resistances, and electrodes are drawn out so as to form a resistance interval in the growth direction of the laminated film. A semiconductor device characterized by: