JP2007251173A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device that reduces the gate tunnel leakage current and GIDL current of an on-chip memory mounted on SRAM and system LSI, a microprocessor, or a MOS transistor used for system LSI. <P>SOLUTION: The manufacturing method for the semiconductor device with N-channel type primary and secondary MIS transistors comprises a process to form a primary p-type well 210 that forms the primary MIS transistor and secondary p-type well 212 that forms the secondary MIS transistor, process to form a gate insulating film 221 and gate electrodes 230, 233 and 234 on the primary and secondary p-type wells, process to implant phosphor into the primary p-type well 210, process to implant arsenic into the secondary p-type well 212, process to form the sidewall film of the gate electrodes after the processes to implant phosphor and arsenic into the primary and secondary p-type wells respectively, and process to implant arsenic into the primary and secondary p-type wells 212 after the process to form the sidewall film of the gate electrodes. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an SRAM (static random access memory), an on-chip memory mounted on a system LSI, a microprocessor, or a system LSI.

Japanese Patent Application No. 9-536055 is known as a known technique for reducing the gate tunnel leakage current. This known example shows a circuit that reduces the leakage current by shutting off the power supply with a switch MOS having a thick gate tunnel leakage current and a small gate tunnel leakage current when the gate tunnel leakage current is large. Japanese Patent Application No. 2000-357862 is known as a technique for reducing GIDL (Gate Induced Drain Leakage) current. In this known example, on the premise that the threshold value of the MOS transistor is relatively low, first, in order to reduce the subthreshold leakage current, the substrate electrode of the P-channel type MOS transistor is set to a power supply voltage or higher and the N-channel type MOS transistor The substrate electrode is controlled below the ground potential. As a result, since GIDL becomes obvious, a technique for reducing the GIDL current by reducing the power supply voltage is disclosed. Japanese Patent Laid-Open No. 9-135029 discloses a technique in which phosphorus ions are implanted into the gate electrode and the source / drain regions of an n-channel MIS transistor as a countermeasure against the GIDL current.
Japanese Patent Application No. 9-536055 Japanese Patent Application No. 2000-357862 JP-A-9-1335029

In recent years, with the miniaturization of processes, the gate oxide film thickness of MOS transistors has become 4 nm or less. However, when the gate oxide film is 4 nm or less, the gate tunnel leakage current increases. When a voltage during operation is applied between the gate electrode and the source electrode, the gate tunnel leakage current is 10 ⁻¹² A / μm ^{2 by a} typical process. That's it.

An LSI used for a mobile phone is required to stand by with a low leakage current. Especially S
RAM needs to hold data for more than a week with a button battery, and if the process becomes worst and the oxide film becomes thin, the gate tunnel leakage current increases, making it impossible to hold data for more than a week There is. In addition, GI which is a leakage current flowing from the drain to the substrate
An increase in DL current is also a problem.

However, in the conventional known example (Japanese Patent Application No. 9-536055) for reducing the gate tunnel leakage current, M
Since the power supply is shut down by the OS, there is a problem that data held in the SRAM cell, the register file, the latch circuit, and the like are destroyed. In addition, in the conventional known example (Japanese Patent Application No. 11-255317) for reducing the GIDL current, when a MOS transistor having a relatively high threshold, for example, 0.7 V is used, the subthreshold leakage current is not significant. Even when the substrate electrode of the N-channel MOS transistor is set to a potential lower than the ground potential and the substrate electrode of the P-channel MOS transistor is set to a potential higher than the power supply potential, the off-current is not reduced, but the junction leakage current is increased. was there.

The following is a brief description of an outline of typical inventions disclosed in the present application. The semiconductor device includes a first having at least one N-channel MOS transistor.
And at least one logic circuit comprising a second current path having at least one P-channel MOS transistor, and one terminal of both current paths of the logic circuit is connected to each other. When one current path is conductive, the other current path is non-conductive. In the at least one logic circuit, the other terminal of the first current path is connected by a source line, a switch circuit is connected to the source line, and the switch circuit is
The source line is kept at a ground potential when the at least one logic circuit is selected to operate, and the source line is kept at a voltage higher than the ground potential during standby when not selected. Semiconductor integrated circuit device.

The substrate electrode of the N-channel MOS transistor is connected to the ground potential or the source line.

During standby, the voltage applied between the gate and source electrodes of the on-state MOS transistor is smaller than the power supply voltage, so that the gate tunnel leakage current can be reduced, and the retained data such as the latch is not destroyed.

Further, in a MOS transistor having a high threshold value with a subthreshold current smaller than GIDL, the voltage applied between the gate and drain electrodes in the off state is smaller than the power supply voltage, so that GIDL is reduced and the off current is reduced. . However, since a ground potential or a voltage higher than the ground potential is applied to the substrate electrode of the N-channel MOS transistor and a power supply potential is applied to the substrate electrode of the P-channel MOS transistor, the junction leakage current does not increase.

FIG. 13 shows that the threshold voltage is relatively high, about 0.7 V, and the subthreshold current is GIDL
The gate voltage dependence of the drain-source current Ids of the N-channel MOS transistor smaller than the current was shown. Ids is displayed on a log scale. When the drain voltage is set to the power supply potential (1.5 V) and when the drain voltage is set lower than the power supply potential according to the present invention (1.0 V)
Shows about. The source electrode and substrate electrode are connected to ground potential and the substrate potential is not biased. In the off state, the potential difference applied between the gate and the drain decreases and the GIDL current becomes small, so that the leakage current can be reduced.

According to the present invention, the semiconductor device further includes an N-channel MOS transistor using arsenic in a contact region of the source / drain regions and phosphorus in the extension region. In a semiconductor device having SRAM, the N-channel MOS transistor is replaced with S.
An N-channel MOS transistor in an RAM memory cell is used, and an N-channel MOS transistor using arsenic is used for both a contact area and an extension area for an N-channel MOS transistor in a peripheral circuit that controls the memory cell. .

  According to the present invention, leakage current can be reduced without destroying data.

Several preferred examples of the semiconductor memory device according to the present invention will be described below with reference to the drawings.

<Example 1>
FIG. 1 is a circuit diagram showing an embodiment of a semiconductor device according to the present invention. This circuit shows a part of a semiconductor integrated circuit composed of a P-channel MOS transistor MP and an N-channel MOS transistor MN. An insulating film used for the gate of the MOS transistor is 4 nm or less, or a gate tunnel leak 10 ^-12 A / μm at a power supply voltage of 1.5 V
It is formed on a semiconductor substrate such as single crystal silicon by using a semiconductor integrated circuit manufacturing technique of ^two or more.

FIG. 1 shows an inverter circuit INV and a latch circuit LATCH for holding data as a part of the semiconductor integrated circuit device.

The inverter circuit INV102 includes P-channel MOS transistors MP102 and N
It is composed of a channel type MOS transistor MN102. The gate electrode of the P-channel MOS transistor MP102 has an input signal I0, the drain electrode has a connection node N0,
A power supply potential VDD is connected to each source electrode.

The substrate electrode of the P-channel MOS transistor MP102 is connected to the power supply potential VDD. An input signal I0 is applied to the gate electrode of the N-channel MOS transistor MN102.
A connection node N0 is connected to the drain electrode, and a ground source electrode line VSSM is connected to the source electrode. The substrate electrode of the N-channel MOS transistor MN102 is connected to the ground source electrode line VSSM or the ground potential VSS.

The inverter circuit INV103 includes P-channel MOS transistors MP103 and N
The channel type MOS transistor MN103 is used. P channel MOS transistor MP103 has a gate electrode connected to connection node N0, a drain electrode connected to connection node N1, and a source electrode connected to power supply potential VDD. The substrate electrode of the P-channel MOS transistor MP103 is connected to the power supply potential VDD. The connection node N0 is connected to the gate electrode of the N-channel MOS transistor MN103, and the connection node N is connected to the drain electrode.
1 and the source electrode are connected to the ground source electrode line VSSM, respectively. The substrate electrode of the N-channel MOS transistor MN103 is connected to the ground source electrode line VSSM or the ground potential VSS.

The inverter circuit INV104 includes P-channel MOS transistors MP104 and N104.
The channel type MOS transistor MN104 is used. The connection node N1 is connected to the gate electrode of the P-channel MOS transistor MP104, the output node O0 is connected to the drain electrode, and the power supply potential VDD is connected to the source electrode. The substrate electrode of the P-channel MOS transistor MP104 is connected to the power supply potential VDD. The connection node N1 is connected to the gate electrode of the N-channel MOS transistor MN104, and the output node O is connected to the drain electrode.
0 and the source electrode are connected to the ground source electrode line VSSM, respectively. The substrate electrode of the N-channel MOS transistor MN104 is connected to the ground source electrode line VSSM or the ground potential VSS.

The latch circuit LATCH includes flip-flops (P-channel MOS transistors (MP105, MP06)) configured by connecting the input and output of a CMOS inverter to each other.
N-channel type transistor (consisting of MN105 and MN106) and storage node N
2 and the storage node N3 store information.

Storage node N3 is connected to the gate electrode of P-channel MOS transistor MP105, storage node N2 is connected to the drain electrode, and power supply potential VDD is connected to the source electrode.
The substrate electrode of the P-channel MOS transistor MP105 is connected to the power supply potential VDD.

Storage node N2 is connected to the gate electrode of P-channel MOS transistor MP106, storage node N3 is connected to the drain electrode, and power supply potential VDD is connected to the source electrode.
The substrate electrode of the P-channel MOS transistor MP106 is connected to the power supply potential VDD.

N-channel MOS transistor MP105 has a gate electrode connected to storage node N3, a drain electrode connected to storage node N2, and a source electrode connected to ground source electrode line VSSM. The substrate electrode of the N-channel MOS transistor MN105 is connected to the ground source electrode line VSSM or the ground potential VSS. N-channel MOS transistor M
The storage node N2 is connected to the gate electrode of P106, the storage node N3 is connected to the drain electrode, and the ground source electrode line VSSM is connected to the source electrode. The substrate electrode of the N-channel MOS transistor MN106 is connected to the ground source electrode line VSSM or the ground potential VSS.
Connected to.

An N channel type MOS transistor MN101 for connecting the ground source electrode line VSSM to the ground potential VSS and an N channel type MOS transistor MN100 for connecting the ground source electrode line VSSM to the potential VSSS higher than the ground potential, for example, 0.5V are arranged. .

Next, the operation state and the standby state will be described using the operation waveforms of FIG. Here, the power supply voltage VDD is 1.5 V, the ground potential VSS is 0 V, and the potential VSSS higher than the ground potential is 0.00.
5V. This voltage is changed depending on the characteristics of the device.

In operation, the N-channel MOS transistor MN101 is on, and VSSM is at the ground potential VSS, for example 0V. The potentials of I0, N1, and N3 are 1.5V, N0
, N2 potential is 0V. At this time, a P-channel MOS transistor (MP10
3, MP106) and N-channel MOS transistors (MN102, MN104, M
N105) is on and P-channel MOS transistors (MP102, MP104, MP1)
05) and the N-channel MOS transistors (MN103, MN106) are off.

1.5 V is applied between the gate and source electrodes of the P-channel MOS transistor MP103, and a gate tunnel leakage current flows from the source electrode to the gate electrode. This current flows to the ground potential VSS through the connection node N0 and the on-state N-channel MOS transistor MN102.

Similarly, 1. between the gate and source electrodes of the N-channel MOS transistor MP104.
5V is applied, and a gate tunnel leakage current flows from the gate electrode to the source electrode. This current flows from the power supply potential VDD through the connection node N1 and the on-channel P-channel MOS transistor MP103.

Similarly, 1. between the gate and source electrodes of the P-channel MOS transistor MP106.
5V is applied, and a gate tunnel leakage current flows from the source electrode to the gate electrode. This current flows to the ground potential VSS through the connection node N2 and the on-state N-channel MOS transistor MN105.

Similarly, 1. between the gate and source electrodes of the N-channel MOS transistor MN105.
5V is applied, and a gate tunnel leakage current flows from the gate electrode to the source electrode. This current flows from the power supply potential VDD through the connection node N2 and the on-channel P-channel MOS transistor MP106. A gate tunnel leakage current flows during operation by the above path.

On the other hand, during standby, the N-channel MOS transistor MN100 is on and VSS
M is a potential VSSS higher than the ground potential, for example, 0.5V. The potentials of I0, N1, and N3 are 1.5V, and the potentials of N0 and N2 are 0.5V. At this time, P-channel MO
S transistor (MP103, MP106) and N channel type MOS transistor (M
N102, MN104, MN105) are on, and a P-channel MOS transistor (MP1)
02, MP104, MP105) and an N-channel MOS transistor (MN103,
MN 106) is off.

Compared with the case where 1.0 V is applied between the gate and source electrodes of the P-channel MOS transistor MP103 and a potential difference of 1.5 V is applied to the gate tunnel leakage current, about 1
The order of magnitude is reduced.

Similarly, 1. between the gate and source electrodes of the N-channel MOS transistor MN104.
Compared with the case where 0 V is applied and the potential difference of 1.5 V is applied to the gate tunnel leakage current, it is reduced by about one digit.

Similarly, 1. between the gate and source electrodes of the P-channel MOS transistor MP106.
Compared with the case where 0 V is applied and the potential difference of 1.5 V is applied to the gate tunnel leakage current, it is reduced by about one digit.

Similarly, 1. between the gate and source electrodes of the N-channel MOS transistor MN105.
Compared with the case where 0 V is applied and the potential difference of 1.5 V is applied to the gate tunnel leakage current, the voltage is reduced by about one digit.

As described above, since the voltage applied between the gate and the source decreases, the gate tunnel leakage current decreases. On the other hand, the retained data is not destroyed. In addition, since the voltage applied between the gate and the drain in the off state decreases, the GIDL current also decreases.

In this embodiment, the case of the inverter circuit and the latch circuit has been described. However, the same effect can be obtained with other semiconductor integrated circuits such as a NAND circuit and a NOR circuit.

<Example 2>
FIG. 3 is a circuit diagram showing an embodiment of a semiconductor device according to the present invention. This circuit shows a part of a semiconductor integrated circuit composed of a P-channel MOS transistor MP and an N-channel MOS transistor MN. The insulating film used for the gate of the MOS transistor is 4 nm or less, or a tunnel leakage current Is formed on a semiconductor substrate such as single crystal silicon by using a semiconductor integrated circuit manufacturing technique with a power supply voltage of 1.5 V and 10 ⁻¹² A / μm ² or more.

FIG. 3 shows an inverter circuit INV and a latch circuit LATCH for holding data as a part of the semiconductor integrated circuit device.

The inverter circuit INV112 includes P-channel MOS transistors MP112 and N
It is composed of a channel type MOS transistor MN112. The input signal I1 is connected to the gate electrode of the P-channel MOS transistor MP112, the connection node N4 is connected to the drain electrode,
A power source electrode line VDDM is connected to each source electrode. P-channel MO
The substrate electrode of the S transistor MP112 is connected to the power source electrode line VDDM or the power source potential V.
Connected to DD. The input signal I1 is connected to the gate electrode of the N-channel MOS transistor MN112, the connection node N4 is connected to the drain electrode, and the ground potential VSS is connected to the source electrode. The substrate electrode of the N-channel MOS transistor MN112 is connected to the ground potential VSS.

The inverter circuit INV113 includes P-channel MOS transistors MP113 and N
The channel type MOS transistor MN113 is used. A connection node N4 is connected to the gate electrode of the P-channel MOS transistor MP113, a connection node N5 is connected to the drain electrode, and a power source electrode line VDDM is connected to the source electrode. P channel type M
The substrate electrode of the OS transistor MP113 is connected to the power source electrode line VDDM or the power potential VDD. N channel MOS transistor MN113 has a gate electrode connected to connection node N4, a drain electrode connected to connection node N5, and a source electrode connected to ground potential VSS. The substrate electrode of the N-channel MOS transistor MN114 is connected to the ground potential VSS.

The inverter circuit INV114 includes P-channel MOS transistors MP114 and N
It is composed of a channel type MOS transistor MN114. The gate of the P-channel MOS transistor MP114 has a connection node N5, the drain electrode has an output signal O1,
A power source electrode line VDDM is connected to each source electrode. P-channel MO
The substrate electrode of the S transistor MP114 is the power source electrode line VDDM or the power source potential V
Connected to DD. The connection node N5 is connected to the gate electrode of the N-channel MOS transistor MN114, the output signal O1 is connected to the drain electrode, and the ground potential VSS is connected to the source electrode. The substrate electrode of the N-channel MOS transistor MN114 is connected to the ground potential VSS.

The latch circuit LATCH is a flip-flop (P-channel MOS transistors (MP115, MP116)) in which the input and output of a CMOS inverter are connected to each other.
The information is stored in the storage node N6 and the storage node N7 using N-channel transistors (MN115 and MN116).

Storage node N7 is connected to the gate electrode of P-channel MOS transistor MP115, storage node N6 is connected to the drain electrode, and power source electrode line VDDM is connected to the source electrode. The substrate electrode of the P-channel MOS transistor MP105 is connected to the power source electrode line VDDM or the power potential VDD.

Storage node N6 is connected to the gate electrode of P-channel MOS transistor MP116, storage node N7 is connected to the drain electrode, and power source electrode line VDDM is connected to the source electrode. The substrate electrode of the P-channel MOS transistor MP116 is connected to the power source electrode line VDDM or the power potential VDD.

N-channel MOS transistor MP115 has a gate electrode connected to storage node N7, a drain electrode connected to storage node N6, and a source electrode connected to ground potential VSS.
The substrate electrode of the N-channel MOS transistor MN115 is connected to the ground potential VSS.

N-channel MOS transistor MP116 has a gate electrode connected to storage node N6, a drain electrode connected to storage node N7, and a source electrode connected to ground potential VSS.
The substrate electrode of the N-channel MOS transistor MN116 is connected to the ground potential VSS.

In addition, a P channel type MOS transistor MP101 for connecting the power source electrode line VDDM to the power source potential VDD and a P channel type MOS transistor MP100 for connecting the power source electrode line VDDM to a potential VDDD lower than the power source potential, for example, 1.0V are arranged. .

Next, the operation state and the standby state will be described using the operation waveforms of FIG. Here, the power supply voltage VDD is 1.5V, the ground potential VSS is 0V, and the potential VDDD lower than the power supply potential is 1.V.
0V. This voltage is changed depending on the characteristics of the device.

In operation, the N-channel MOS transistor MP100 is on and VDDM is at the power supply potential VDD, for example, 1.5V. N4, N7 potential is 1.5V, I1,
The potentials of N5 and N6 are 0V. At this time, a P-channel MOS transistor (MP
112, MP114, MP116) and an N-channel MOS transistor (MN113)
, MN1 15) are on, and the P-channel MOS transistors (MP113, MP115) and N-channel MOS transistors (MN112, MP114, MN116) are off.

1.5 V is applied between the gate and the source electrode of the N-channel MOS transistor MN113, and a gate tunnel leakage current flows from the gate electrode to the source electrode. This current flows from the power supply potential VDD through the connection node N4 and the on-channel P-channel MOS transistor MP112.

Similarly, 1. between the gate and source electrodes of the P-channel MOS transistor MP114.
5V is applied, and a gate tunnel leakage current flows from the source electrode to the gate electrode. This current flows to the ground potential VSS through the connection node N5 and the on-state N-channel MOS transistor MN113.

Similarly, 1. between the gate and source electrodes of the P-channel MOS transistor MP116.
5V is applied, and a gate tunnel leakage current flows from the source electrode to the gate electrode. This current flows to the ground potential VSS through the connection node N6 and the on-state N-channel MOS transistor MN115.

Similarly, 1. between the gate and source electrodes of the N-channel MOS transistor MN115.
5V is applied, and a gate tunnel leakage current flows from the gate electrode to the source electrode. This current flows from the power supply potential VDD through the connection node N6 and the on-channel P-channel MOS transistor MP116. A gate tunnel leakage current flows during operation by the above path.

On the other hand, during standby, the P-channel MOS transistor MP101 is on and VDD
M is a potential VVDD lower than the power supply potential, for example, 1.0V. The potentials of N4 and N7 are 1.0V, and the potentials of I1, N5, and N6 are 0V. At this time, the P-channel MOS transistors (MP112, MP114, MP116) and the N-channel MOS transistors (MN113, MN115) are turned on, and the P-channel MOS transistors (MP113)
, MP115) and N-channel MOS transistors (MN112, MN114, MN
116) is off.

Compared with the case where 1.0 V is applied between the gate and source electrodes of the N-channel MOS transistor MN113 and a potential difference of 1.5 V is applied to the gate tunnel leakage current, about 1
The order of magnitude is reduced.

Similarly, 1. between the gate and source electrodes of the P-channel MOS transistor MP114.
Compared with the case where 0 V is applied and the potential difference of 1.5 V is applied to the gate tunnel leakage current, it is reduced by about one digit.

Similarly, 1. between the gate and source electrodes of the P-channel MOS transistor MP116.
Compared with the case where 0 V is applied and the potential difference of 1.5 V is applied to the gate tunnel leakage current, it is reduced by about one digit.

Similarly, 1. between the gate and source electrodes of the N-channel MOS transistor MN115.
Compared with the case where 0 V is applied and the potential difference of 1.5 V is applied to the gate tunnel leakage current, it is reduced by about one digit.

As described above, since the voltage applied between the gate and the source decreases, the gate tunnel leakage current decreases. On the other hand, the retained data is not destroyed. In addition, since the voltage applied between the gate and the drain in the off state decreases, the GIDL current also decreases.

In the present embodiment, the case of the inverter circuit and the latch circuit has been described, but the same effect can be obtained with other semiconductor integrated circuits such as a NAND circuit and a NOR circuit.

<Example 3>
FIG. 15 is a circuit diagram showing an embodiment in which the present invention is applied to an SRAM. The semiconductor manufacturing apparatus 98 is composed of P-channel type MOS transistor and N-channel type MOS transistors, MOS transistors or insulating film is 4nm or less to be used in the gate of the tunnel leakage current power supply voltage 1.5V, 10 ^- It is formed on a semiconductor substrate such as single crystal silicon by using a semiconductor integrated circuit manufacturing technique of ¹² A / μm ² or more.

The SRAM 98 that is a semiconductor device is divided into a plurality of mats MEMBLK. Details of the mat are shown in FIG. The mat unit is, for example, every 2M bits, and is divided into 8 mats in a 16M SRAM. The step-down circuit PWR generates internal power supplies (VDD, VSSS, VDDD) based on the power supply potential VCC applied from the external pad, and distributes them to each mat. Data 116 from the input buffer INBUF becomes a decode signal and a control signal through the predecoder 115 and the control circuit 117, and is distributed to each mat. Each mat 108 includes a plurality of basic units 106. The basic unit is composed of a two-column memory CELL.

CELL0 is a flip-flop (load-type P-channel MOS transistors (MP00, MP01)) formed by connecting the input and output of a pair of CMOS inverters to each other.
A transfer type N channel type which selectively connects a drive type N channel type transistor (consisting of MN00 and MN01) and a storage node NL0 and a storage node NR0 of the flip-flop to a data line (DT0, DB0). It is composed of MOS transistors (MN02, MN03). The gate electrode of the N channel type MOS transistor (MN02, MN03)
Sub-word line SWL0 is connected.

The memory cell CELL1 is a flip-flop (P-channel MOS transistors (MP10, MP11) formed by connecting the inputs and outputs of a pair of CMOS inverters to each other.
), An N-channel MOS transistor configured to selectively connect the storage node NL1 and the storage node NR1 of the flip-flop to data lines (DT1, DB1). (MN12, MN13). A sub word line SWL0 is connected to the gate electrodes of the N channel type MOS transistors (MN12, MN13).

The basic unit includes a sense amplifier circuit (103) and a read data drive circuit (
104), a write amplifier circuit (105), and an equalize precharge circuit (99, 100).
) And a Y switch circuit (101, 102). Sense amplifier circuit (103
) Includes a flip-flop composed of P-channel MOS transistors (MP20, MP21) and N-channel MOS transistors (MN20, MN21), and a latch-type sense amplifier circuit composed of an N-channel MOS transistor MN22 that activates the sense amplifier. It is composed of switch circuits (MP22, MP23). MOS transistor (MN22, MP
22, MP23) is connected to an activation signal SA.

The Y switch circuit 101 includes P-channel MOS transistors (MP05, MP06) and N-channel MOS transistors (MN04, MN05) that connect the data lines (DT0, DB0) and the sense amplifier circuit 103.

The Y switch circuit 102 includes P-channel MOS transistors (MP15, MP16) and N-channel MOS transistors (MN14, MN15) that connect the data lines (DT1, DB1) and the sense amplifier circuit 103.

The control signals (YSW, YSWB) send the sense amplifier circuit 103 to the data lines (DT0, DB
0) or a data line (DT1, DB1).

The write amplifier circuit 105 has two clocked inverters (CINV2, CINV3).
And an inverter INV0. The signal on the data bus 111 is propagated to the data line by the control signal (WBC, WBCB).

The read data drive circuit 104 includes two clocked inverters (CINV2, CI
NV3). The read data is propagated to the data bus 111 by control signals (RBC, RBCB).

The equalize / precharge circuit 99 includes a P-channel MOS transistor MP02 that connects the power supply potential VDD and the data line DT0, a P-channel MOS transistor MP03 that connects the power supply potential VDD and the data line DB0, and a P that connects the data line DT0 and the data line DB0. The channel type MOS transistor MP04 is used.

A control signal EQ is connected to the gate electrodes of the P-channel MOS transistors (MP02, MP03, MP04).

The equalize / precharge circuit 99 includes a P-channel MOS transistor MP02 that connects the power supply potential VDD and the data line DT0, a P-channel MOS transistor MP03 that connects the power supply potential VDD and the data line DB0, and a P that connects the data line DT0 and the data line DB0. The channel type MOS transistor MP04 is used. A control signal EQ is connected to the gate electrodes of the P-channel MOS transistors (MP02, MP03, MP04).

The equalize / precharge circuit 100 is configured to connect the power supply potential VDD and the data line DT1 to P
P-channel MOS transistor MP13 connecting channel type MOS transistor MP12, power supply potential VDD and data line DB1, and P connecting data line DT1 and data line DB1
It is composed of a channel type MOS transistor MP14. A control signal EQ is connected to the gate electrodes of the P-channel MOS transistors (MP12, MP13, MP14).

Each column has a voltage lower than the power supply voltage on the data lines (DT, DB) during standby, for example, 1.
Switch circuits (109, 110) for supplying 0V are arranged. Switch circuit 10
9 includes a P-channel MOS transistor MP07 that connects the voltage VDDD lower than the power supply voltage and the data line DT0, and a P-channel MOS transistor MP08 that connects the voltage VDDD lower than the power supply voltage and the data line DB0. P-channel MOS transistor (
The control signal CVDDD is connected to the gate electrodes of MP07 and MP08).

The switch circuit 110 connects the voltage VDDD lower than the power supply voltage and the data line DT1 to P
Channel type MOS transistor MP17, voltage VDDD lower than power supply voltage and data line DB
1 is composed of a P-channel type MOS transistor MP18 connected to one. P channel type M
A control signal CVDDD is connected to the gate electrodes of the OS transistors (MP17, MP18).

All the memory cell ground source electrode lines VSSM in the memory mat 108 are connected by a metal layer, and are connected to a power source by N channel type MOS transistors (MN6, MN7). The N-channel MOS transistor MN6 is a transistor that connects the power supply VSSS that supplies a voltage higher than the ground potential VSS and the ground source electrode line VSSM, and a control signal STVSSM is connected to the gate electrode. N-channel MOS transistor MN
A transistor 7 connects the ground potential VSS and the ground source electrode line VSSM, and a control signal ACVSSM is connected to the gate electrode.

The control signal STVSSM is generated by the AND circuit AND0 and the inverter circuit INV1 using the chip selection signal CS and the mat selection signal MAT. Control signal ACVS
SM is generated by the AND circuit AND0 using the chip selection signal CS and the mat selection signal MAT.

The control signal CVDDD is generated by the AND circuit AND0 using the chip selection signal CS and the mat selection signal MAT.

The sub-word line SWL receives the input address and control signal 116 as a predecoder 115.
And pre-decoded by the word decoder and the word driver 114.

The control signal EQ includes a chip selection signal CS, a mat selection signal MAT, and a reset pulse A.
It is generated by the NAND circuit NAND0 using TD.

The control signal (YSWB, YSW) uses the Y address AY to invert the inverter circuit INV2.
Generated by.

The control signal SA includes a chip selection signal CS, a mat selection signal MAT, and a write selection signal WE.
AND circuit AND2 and inverter circuit (INV3, INV4 using FSEN)
). FSEN is a timing pulse generated from ATD.

Control signals (RBC, RBCB) are generated by the inverter circuit INV5 using the control signal SA.

The control signals (WBC, WBCB) are generated by the AND circuit AND3 and the inverter circuit INV6 using the chip selection signal CS, the mat selection signal MAT, and the write selection signal WE.

Control signals (CS, WE, YA, MAT, ATD) are generated using the control circuit 117 from the input address and control signal. The mat selection signal MAT may be prepared as a fast mat selection signal FMAT using another control circuit 118 as shown in FIG. The selection of the word line takes into account the process variation and timing to prevent malfunction, while the circuit driven to read / write the memory cell (the circuit that controls the operating potential to the selected state, If the precharge circuit or the like is earlier than the word line selection, the timing control accuracy may be lowered.

Therefore, the control circuit 117 that is the source for selecting the word line has a high threshold value M.
The control circuit 118 that uses an OSFET (including both P-channel type and N-channel type) and outputs a signal that activates a circuit driven to read / write data from / to the memory cell has the high threshold value and Two types of low threshold voltage MOSFETs (including both P-channel type and N-channel type) are used. If a MOSFET with a low threshold value is included, it becomes weak against process variations and it is difficult to obtain the accuracy of output timing, but the control circuit 118 can output the mat selection signal earlier than the control circuit 117. It is possible to simplify the design by using the same circuit configuration, and read out from the memory cell by increasing the types of thresholds including MOSFETs having lower threshold values than the control circuit from which the word line is selected. A circuit for controlling a circuit driven for writing is configured, whereby a mat selection signal MA from which a word line is selected
The accuracy of the timing of T is increased, and the timing of the mat selection signal FMAT, which is a source for selecting a circuit to be read / written to / from the memory cell, is surely output earlier than the mat selection signal MAT. Can do.

This configuration is particularly effective in the design of memory devices that are asynchronous and have strict selection timing accuracy. For example, the fast mat selection signal FMAT is supplied to the AND circuit AND0 of the circuit that controls the memory cell ground source electrode line VSSM, the AND circuit AND1 of the circuit that controls the supply of VDDD, and the NAND circuit NAND0 of the circuit that controls the equalization / precharge. Used in place of signal MAT.

Next, a case where a read operation is performed from the standby state will be described with reference to operation waveforms in FIG.
When the chip selection signal CS is “L” (“LOW” level) or when the mat is not selected, the memory mat is in a standby state. At this time, the memory cell ground source electrode line VSS
M is supplied with a voltage VSSS, for example, 0.5 V, higher than the ground potential. The data line (D
T, DB) is supplied with a voltage VDDD lower than the power supply voltage VDD, for example, 1.0V.
At this time, the storage node NL0 of the memory cell CELL0 is 0.5V, and NR0 is the power supply potential V
DD, for example, 1.5V. P-channel MOS transistor MP01 in the on state
A voltage of 1.0 V, which is lower than the power supply voltage of 1.5 V, is applied between the gate and source electrodes of the gate, and the gate tunnel leakage current is reduced. In addition, a voltage of 1.0 V, which is lower than the power supply voltage 1.5 V, is applied between the gate and source electrodes of the N-channel MOS transistor MN00 in the on state, and the gate tunnel leakage current is reduced. In addition, a voltage of 1.0 V lower than the power supply voltage 1.5 V is applied between the gate and source electrodes of the off-state transfer N-channel MOS transistors (MN02, MN03), and the GIDL current is reduced.

When the chip selection signal CS becomes “H” or the address changes, an ATD pulse is generated and a read operation is started. The memory cell ground source electrode line VSSM of the selected mat 108 becomes the ground potential 0 V by the mat selection signal MAT and the chip selection signal CS. Further, a P-channel MOS transistor (that has supplied the voltage VDDD to the data lines (DT, DB)) (
MP07, MP08, MP17, MP18) are turned off.

The data lines (DT, DB) are precharged to the power supply voltage VDD by the control signal EQ generated from the ATD pulse.

As a result, the storage node NL0 of the memory cell CELL0 is 0V, and NR0 is the power supply potential VD.
D For example, 1.5V. A power supply voltage of 1.5 V is applied between the gate and source electrodes of the P-channel MOS transistor MP01 in the on state, and the gate tunnel leakage current increases. Further, a power supply voltage of 1.5 V is applied between the gate and source electrodes of the N-channel MOS transistor MN00 in the on state, and the gate tunnel leakage current increases. Also,
A power supply voltage of 1.5 V is applied between the gate and source electrodes of the off-state transfer N-channel MOS transistors (MN02, MN03), and the GIDL current increases.

Thereafter, the word line SWL0 is selected, a minute potential difference is generated in the data lines (DT, DB), and the sense amplifier 103 is activated by the control signal SA to amplify the minute potential difference and output the data to the data bus 111.

Next, the case where the write operation is performed from the standby state will be described with reference to the operation waveforms of FIG.
The standby state is the same as in the read operation.

When the chip selection signal CS becomes “H” or the address changes, an ATD pulse is generated and a write operation is started. The memory cell ground source electrode line VSSM of the selected mat 108 becomes the ground potential 0 V by the mat selection signal MAT and the chip selection signal CS. Further, a P-channel MOS transistor (that has supplied the voltage VDDD to the data lines (DT, DB)) (
MP07, MP08, MP17, MP18) are turned off.

The data lines (DT, DB) are precharged to the power supply voltage VDD by the control signal EQ generated from the ATD pulse.

As a result, the storage node NL0 of the memory cell CELL0 is 0V, and NR0 is the power supply potential VD.
D For example, 1.5V. A power supply voltage of 1.5 V is applied between the gate and source electrodes of the P-channel MOS transistor MP01 in the on state, and the gate tunnel leakage current increases. Further, a power supply voltage of 1.5 V is applied between the gate and source electrodes of the N-channel MOS transistor MN00 in the on state, and the gate tunnel leakage current increases. Also,
A power supply voltage of 1.5 V is applied between the gate and source electrodes of the off-state transfer N-channel MOS transistors (MN02, MN03), and the GIDL current increases.

Thereafter, the word line SWL0 is selected. A data bus 11 is connected to the data lines (DT, DB).
1 is input, and data is written into the memory cell CELL by this signal.

In this embodiment, the source voltage of the memory cell is raised to 0.5 V during standby, but the power supply of the memory cell may be lowered to 1.0 V. However, when changing from the standby state to the operating state, it is required to shift faster than when changing from the operating state to the standby state. For this reason, raising the source voltage to 0.5 V during standby is more advantageous than raising the source to 0.5 V because the burden on the power supply circuit is less than reducing the power supply of the memory cell to 1.0 V. Further, as can be seen from the characteristics of FIG. 13, even when the voltage is the same 0.5 V, it can be said that increasing the source voltage on the low potential side is advantageous in reducing the current.

FIG. 14 shows the leakage current of the 1 SRAM cell during standby and during operation. The GIDL current, subthreshold leakage current, and GIDL are all small during standby.

FIG. 16 shows an example of the characteristics of the step-down circuit PWR. When generating the potential VDDD supplied to the bit line or the like and the operation potential (high potential VDD, low potential VSSS) supplied to the memory cell, the external pad is supplied when the potential VCC supplied from the external pad becomes a predetermined value or more. The configuration is such that the supplied potential is controlled and output. For example, when the potential VCC supplied from the external pad is 1.5 V or less, the high potential VDD supplied to the memory cell is the same as the power supply potential VCC supplied from the external pad, and when VCC is 1.5 V or more, VDD Is controlled to be constant at 1.5V. The potential VDDD lower than the power supply potential is controlled to be the same as the potential VCC supplied from the external pad when VCC is 1.0 V or less, and constant at 1.0 V when VCC is 1.0 V or more. . The potential VSSS higher than the ground potential is the potential VCC.
Is 0 V when the voltage is 1.0 V or less, and the potential VCC supplied from the external power supply pad is 1.0 V.
In the above case, it is 1.0 based on the high potential VDD supplied to the memory cell.
V is controlled to be a low value. As a result, even if the power supply potential VCC input from outside the semiconductor chip fluctuates, the voltage applied to the memory cell is always 1.0 V, and data destruction can be prevented. Note that the low-potential-side potential VSS supplied from another external pad is a ground potential, so it can be considered that it does not vary. The application of the operation potential generation circuit that can be controlled by the feedback circuit is not limited to the semiconductor integrated circuit including the memory, and is also effective in the previous embodiment.

In this embodiment, in order to reduce the GIDL current, in the semiconductor device, arsenic is used for the contact region and phosphorus is used for the extension region among the source / drain regions.
A channel type MOS transistor is provided. In a semiconductor device having an SRAM, the N-channel MOS transistor is used as an N-channel MOS transistor in an SRAM memory cell, and a contact region and an extension region are provided for an N-channel MOS transistor in a peripheral circuit that controls the memory cell. N-channel MO using arsenic for both
S transistors are used.

In FIG. 26, the characteristics of the gate voltage Vgs and the current between the source and the drain when arsenic is used for the contact region and the arsenic is used for the extension region among the source / drain regions of the N-channel MOS transistor. The characteristics of the gate voltage Vgs and the current Ids between the source and the drain when phosphorus is used are shown in FIG. The coordinates are (a)
The same applies to (b). As is apparent from this waveform, the off current when the gate voltage is 0.0 V is clearly lower in the case where phosphorus is used (b), and the method of the present invention (the operating potential of the memory cell during standby) When Vssm is increased from 0.0 V to 0.5 V), it can be seen that using phosphorus in the extension region is effective for reducing the off-current. Although not shown here, it has been found that the effect in the high temperature operating region is significant.

P (phosphorus) has a larger variation in device characteristics such as Vth-Lowering characteristics than As (arsenic), and the current driving force is lower than that of As. Therefore, it is difficult to adjust the ion implantation concentration and energy. Arsenic was used for the area to be removed and the extension area.
Japanese Patent Laid-Open No. 9-135029 discloses a device structure of phosphorus in both the contact region and the extension region, but it is effective for the present inventors to inject phosphorus into the extension region to reduce the GIDL current. In addition, it has been shown that it is effective to use arsenic in the contact area in terms of device performance (current driving capability, short channel characteristics).

The reason why this effect is obtained is that the band bending due to the vertical electric field from the gate electrode is alleviated by phosphorus implantation in the extension region overlapping under the gate electrode. Further, the broadening of the implantation profile alleviates the junction field strength in the vertical direction between the channel region and the extension region, thereby contributing to the effect of reducing the PN junction leakage.

17 to 25 are cross-sectional views showing an example of the manufacturing method of the semiconductor device of this embodiment in the order of steps. Each figure shows an N channel type MOS transistor Qm constituting the memory cell portion MC.
n, a P channel type MOS transistor Qmp, an N channel type MOS transistor Qpn and a P channel type MOS transistor Qpp constituting the peripheral circuit part PERI, and a high breakdown voltage part H
The description is divided into an N-channel MOS transistor Qhn and a P-channel MOS transistor Qhp constituting V. The N channel type MOS transistor Qmn constituting the memory cell unit MC is used for driving and transfer MOS transistors of each memory cell CELL in FIG. The P channel type MOS transistor Qmp constituting the memory cell portion MC is used as a load MOS transistor of each memory cell CELL in FIG. The N channel type MOS transistor Qpn and the P channel type MOS transistor Qpp constituting the peripheral circuit portion PERI are shown in FIG.
This is used for P and N channel type MOS transistors other than the memory cell portion. That is, the sense amplifier circuit (103), the read data drive circuit (104), and the write amplifier circuit (1
05), equalizing precharge circuit (99, 100) and Y switch circuit (101, 1
02), a MOS transistor used for a word decoder and a word driver (114), a predecoder (115), and a control circuit (117). The N-channel MOS transistor Qhn and the P-channel MOS transistor Qhp constituting the high withstand voltage portion HV are circuits having different input and output operating voltages, that is, the input buffer (INBUF) and the step-down circuit (PWR) in FIG.
Used for the N and P channel type MOS transistors constituting the input / output circuit IO.

Hereinafter, it demonstrates in order of a process using drawing. First, as shown in FIG.
A semiconductor substrate 200 made of single crystal silicon is prepared, and an element isolation region 201 is formed on the main surface of the semiconductor substrate 200. The element isolation region 201 can be formed as follows, for example. First, a silicon oxide film (SiO ₂ ) and a silicon nitride film (Si ₃ N ₄ ) are sequentially formed on the main surface of the semiconductor substrate 200, and this silicon nitride film is etched using a patterned photoresist film. A groove-type isolation region is formed in the semiconductor substrate 200 using the etched silicon nitride film as a mask. Thereafter, an insulating film, for example, a silicon oxide film, for embedding the trench type isolation region is deposited, and the silicon oxide film in a region other than the trench type isolation region is removed by using a CMP method or the like, and further a silicon nitride film by a wet etching method or the like. Remove. Thereby, an element isolation region (trench isolation) 201 is formed. The element isolation region is not limited to the trench type isolation region. For example, LOCOS (Local Oxidization of
(Silicon) may be used to form a field insulating film. A thin silicon oxide film is deposited in order to mitigate damage on the surface of the semiconductor substrate due to the next ion implantation process.

Thereafter, impurities are ion-implanted using the patterned photoresist film as a mask to form p wells 210 and 212 and n wells 211 and 213 as shown in FIG. Impurities having a p-type conductivity, such as boron B or boron fluoride BF2, are ion-implanted into the p-well, and impurities having an n-type conductivity, such as phosphorus P and arsenic As, are ion-implanted into the n-well. Thereafter, impurities for controlling the threshold value of the MOSFET in each well region (
In an N channel type MOS transistor, an impurity (P) having an n type conductivity type, a P channel type MO transistor
In the S transistor, an impurity (BF2) having a p-type conductivity is ion-implanted.

Next, as shown in FIG. 17B, a silicon oxide film 221 to be a gate insulating film is formed.
At this time, a thick gate oxide film was formed in the high breakdown voltage portion, and a thin gate oxide film was formed in the peripheral circuit portion and the memory cell portion using photolithography and etching techniques.

In this embodiment, since the thickness of the thick gate oxide film corresponds to 3.3 V by external input / output, it is 8.0.
The thickness of the thin gate oxide film was set to 3.0 nm, which causes a problem of gate leakage current during standby. After removing the oxide film other than the high withstand voltage portion by the photolithography / wet etching technique, the oxide film having two kinds of film thickness is formed by thermal oxidation again and thermal oxidation. Thereafter, a polycrystalline silicon film 222 for the gate electrode is deposited, and n-type / p-type impurities (phosphorus and boron) are ion-implanted into the N and P-channel MOS electrode regions using the resist mask 223, respectively.

As shown in FIG. 18A, gate electrodes 230, 231, 232, 233, 234, and 235 are formed by processing using photolithography / dry etching. Next, as shown in FIG. 18B, the semiconductor region to be the extension region and the semiconductor region of the opposite conductivity type (the same conductivity type as the well and higher concentration than the well region) for suppressing punch through are ion-implanted. Form by law. In the N channel type MOS transistor, ion implantation is performed by changing the mask (process) in each of the memory cell portion MC, the peripheral circuit portion PERI, and the high breakdown voltage portion HV. In the memory cell part MC, n-type semiconductor regions 241 and 242 and a p-type semiconductor region 243 are implanted by injecting n-type impurities such as phosphorus and p-type impurities (boron) in order to reduce a standby GIDL current. 244 is formed. In this case, other regions (P-channel MOS transistor region, peripheral circuit portion / high voltage portion region) are masked with a resist. In the peripheral circuit portion PERI, n-type semiconductor regions 245 and 246 and p-type semiconductor regions 247 and 248 are formed by implanting n-type impurities such as arsenic and p-type impurities (boron) in order to realize high-speed operation. To do. In that case, other areas (P-channel MOS transistor area, memory cell area / high voltage area)
Is masked with resist.

Next, as shown in FIG. 18C, the p-type impurity (boron) and the n-type impurity (As) are implanted into the n-type well region 211 to be a P-channel MOS transistor, thereby extending the extension region and Semiconductor regions 251, 254, 255, 256, semiconductor regions 253, 254, 2 having the same conductivity type as the well and having a higher concentration than the well region for suppressing punch-through.
57, 258 are formed. The P channel type MOS transistor does not change the type of impurities and the condition (energy) of the ion implantation in the memory cell part MC and the peripheral circuit part PERI. A region to be a MOS transistor and a region to be a P-channel MOS transistor in the high breakdown voltage portion HV are masked with a resist. The N-channel MOS transistor of the high breakdown voltage portion is formed by injecting n-type impurities arsenic and phosphorus and p-type impurities (boron) so as to alleviate the vertical electric field at the edge end, thereby causing an n-type semiconductor region 259,
260, 261, and 262 and p-type semiconductor regions 263 and 264 are formed. The n-type semiconductor regions 259 and 260 close to the semiconductor surface are mainly composed of arsenic due to the difference in distribution coefficient, and the n-type semiconductor regions 261 and 262 implanted deeper are mainly composed of phosphorus.

Next, as shown in FIG. 19A, p-type impurities (boron) and n-type impurities (As) are implanted into the n-type well region 213 to be a P-channel MOS transistor of the high breakdown voltage portion HV. As a result, a p-type semiconductor region 266 serving as an extension region and a semiconductor region 267 having the same conductivity type as the well and having a higher concentration than the well region are formed to suppress punch-through. In this embodiment, the mask (process, ion implantation condition) is changed between the high breakdown voltage portion HV, the memory cell portion MC, and the peripheral circuit portion PERI. If the breakdown voltage can satisfy the characteristics of the product, the P channel type is used. The MOS transistor can be formed in one mask (process) without changing the impurity type and ion implantation conditions (energy) in the memory cell portion MC, the peripheral circuit portion PERI, and the high breakdown voltage portion HV.

The order of ion implantation of the extension region and the well and the anti-conducting and high-concentration semiconductor region is not limited. That is, ion implantation of a region that becomes a P-channel MOS transistor may be performed prior to ion implantation into the N-channel MOS transistor region. 18 (b) (c
According to the above, in the N channel type MOS transistor, the ion implantation is performed in the order of the memory cell portion, the peripheral circuit portion, and the high breakdown voltage portion, but the order does not matter. Depending on the amount of impurities in the ion implantation of the high withstand voltage portion, the memory cell portion and the peripheral circuit portion are not covered with a mask when ion implantation is performed.
Although it is possible not to prepare a mask for the high voltage section, if there is a difference in the amount of impurities,
It is necessary to prepare another mask as shown in FIG.

As shown in FIG. 19A, after depositing a silicon oxide film on the semiconductor substrate 200 by, for example, a CVD method, the silicon oxide film is anisotropically etched, whereby the gate electrode 23 is obtained.
Side wall spacers (gate side wall films) 265 are formed on the side walls of 0, 231, 232, 233, 234, and 235, respectively. Next, as shown in FIG. 19B, the photoresist film 2
Using p as a mask, p-type impurities (boron) are ion-implanted into the well n-wells 210 and 212 to form p-type semiconductor regions 271 on both sides of the gate electrodes 231, 232 and 235 on the n-well. The p-type semiconductor region 271 is formed in a self-aligned manner with respect to the gate electrodes 231, 232, 235 and the sidewall spacer 265, and functions as a source / drain region of the p-channel MISFET.

Similarly, an n-type impurity (As) is formed in the p wells 211 and 213 using the photoresist film as a mask.
) Is implanted to form an n-type semiconductor region 280 to be in contact with the electrode. The n-type semiconductor region 280 is formed in a self-aligned manner with respect to the gate electrodes 230, 233 and 234 and the sidewall spacer 265. The n-type semiconductor region 280 functions as a source / drain region of the n-channel MISFET. As a result, a low concentration impurity semiconductor region is formed before the sidewall spacer 265 is formed, and the sidewall spacer 2 is formed.
After the formation of 65, an LDD (Lightly Doped Drain) structure transistor for forming a high concentration impurity semiconductor region is formed in each region (FIG. 19C). In this embodiment, the source / drain regions of the N-channel MOS transistor are formed first, but the P-channel M
The OS transistor may be formed first.

Next, as shown in FIG. 20A, the silicon oxide film is etched to expose the surface of the source / drain semiconductor region, and a refractory metal film (Co, Ti, W, Mo, Ta) is deposited and annealed. Then, by removing the unreacted refractory metal film, the gate electrodes 230, 231, 232,
233, 234, 235 and part of the surface of the semiconductor region forming the source / drain are silicided (290, 291). Thereafter, a silicon nitride film 292 is deposited.

As shown in FIG. 19B, after a silicon oxide film is deposited on the semiconductor substrate 200 by a CVD method or a sputtering method, the silicon oxide film is polished by, for example, a CMP method,
A first interlayer insulating film 300 having a planarized surface is formed. Next, a connection hole is formed in the first interlayer insulating film 300 using a photolithography technique. This connection hole is formed in a necessary portion on the n-type semiconductor region or the p-type semiconductor region.

For example, a plug is formed in the connection hole as follows. First, the titanium nitride film 301 is formed on the entire surface of the semiconductor substrate 200 including the inside of the connection hole. The titanium nitride film is, for example, C
It can be formed by the VD method. Since the CVD method is excellent in the step coverage of the coating, it is possible to form a titanium nitride film with a uniform thickness even in a fine connection hole. Next, a metal (lithium) film 3 for embedding the connection hole
02 is formed. The metal film can be formed by, for example, a CVD method. Next, the plug can be formed by removing the metal film and the titanium nitride film in regions other than the connection holes by, for example, a CMP method.

By forming such a silicide layer, the contact resistance at the bottom of the connection hole 12 can be reduced. Similarly, a connection hole is formed in the second interlayer insulating film 310. The connection hole is formed by a titanium nitride film 311 and a metal (tungsten) film 312. These plugs are used to connect local wiring. Next, for example, a titanium nitride film 321 and an aluminum film 322 are formed on the entire surface of the semiconductor substrate 200 by a CVD method or a sputtering method, and the deposited films are patterned by a photolithography technique to form a wiring of the first wiring layer. . The first layer wiring is used for a bit line or the like in the memory portion. An insulating film that covers the wiring, for example, a silicon oxide film is formed, and this insulating film is planarized by CMP to form a second interlayer insulating film 330. Second
A photoresist film having an opening is formed on the interlayer insulating film 330 in a region where a connection hole is to be formed, and etching is performed using this photoresist film as a mask. As a result, the second interlayer insulating film 3
Connection holes are formed in 30 predetermined regions. A plug is formed in the connection hole.

The plug can be formed as follows. First, a barrier metal layer 340 is formed on the entire surface of the semiconductor substrate 200 including the inside of the connection hole, and further a metal (tungsten) film 34 that fills the connection hole.
1 is formed. Thereafter, the metal film and the barrier metal layer in the region other than the connection hole are removed by CMP to form a plug. The barrier metal layer has a function of preventing diffusion of tungsten to the periphery of the second interlayer insulating film 330 and the like. For example, a titanium nitride film can be exemplified. Note that the film is not limited to a titanium nitride film, and may be another metal film as long as it has a function of preventing diffusion of tungsten. For example, tantalum (Ta) or tantalum nitride (TaN) can be used instead of titanium nitride. Similar to the first wiring layer, the wiring (351, 352) of the second wiring layer is formed. An insulating film covering the wiring is formed, and the insulating film is planarized by CMP to form a third interlayer insulating film 360. A connection hole is formed on the third interlayer insulating film 360 in the same manner as the second interlayer insulating film 330, and plugs (361, 362) are formed in the connection hole. Similar to the second wiring layer, wirings (363, 364) of the third wiring layer are formed. An insulating film 370 that covers the wiring is formed, and a silicon nitride film is formed as a passivation film 371 on the insulating film. Before shipping as a product, there are an inspection process, a resin sealing process, and the like.

As a result of prototyping a memory cell using this device structure in which arsenic is implanted into a region that makes contact with the extension region and phosphorus is applied to the extension region, it is found that the standby current can be reduced by about 50% at 25 ° C. and 90 ° C. It was. In other words, the standby current of the semiconductor device can be suppressed not only at the normal operation temperature but also at a high temperature, and by adopting this structure, the guaranteed operation temperature of the product (for example, 70 ° C. or less) can be set high. It has the effect.

By adopting this device structure in the thin film NMOS, the standby current of the semiconductor device can be reduced from 2.5 uA to 1.0 uA in the conventional As structure. This effect is due to the fact that the main component of the standby current is the NMOS GIDL current (about 70%).

Note that only phosphorus is used in the extension region of the N-channel MOS transistor in the memory cell portion, but phosphorus and arsenic may be implanted for high-speed operation. In this case, two types of ion sources are required, but the effect of increasing the drive current can be obtained. The structure is similar to that of the N-channel MOS transistor in the high breakdown voltage portion. Since it is necessary to perform ion implantation with energy lower than that of the high breakdown voltage MOS, it is necessary to change the mask when ion implantation is performed in the extension region of the high breakdown voltage portion. As a result, the spread of the semiconductor region is larger than that of the high breakdown voltage portion itself. Narrow.

<Example 4>
FIG. 8 shows an embodiment in which the present invention is applied to a microprocessor. The insulation film used for the gate of the MOS transistor is 4nm or less, or the tunnel leakage current is 1.5V.
Thus, it is formed on a semiconductor substrate such as single crystal silicon by using a semiconductor integrated circuit manufacturing technique of 10 ⁻¹² A / μm ² or more.

The microprocessor 130 includes an IP circuit 133, a cache memory 131, and a CPU.
132. A control circuit 134 for controlling the operation and standby state is also mounted on the microprocessor 130.

The ground source electrode line VSSM of the cache memory 131 is connected to a potential VSSS higher than the ground potential via an N-channel MOS transistor MN200.
It is connected to the ground potential VSS via the OS transistor MN201. N channel type M
A control signal STBY0 is connected to the gate electrode of the OS transistor MN200. N
A control signal ACTV0 is connected to the gate electrode of the channel type MOS transistor MN201.

The ground source electrode line VSSM of the CPU circuit 132 is connected to an N-channel MOS transistor M.
It is connected to the potential VSSS higher than the ground potential via N202, and is connected to the ground potential VSS via the N-channel MOS transistor MN203. A control signal STBY1 is connected to the gate electrode of the N-channel MOS transistor MN202. A control signal ACTV1 is connected to the gate electrode of the N-channel MOS transistor MN203.

The ground source electrode line VSSM of the IP circuit 133 is connected to an N-channel MOS transistor MN.
It is connected to the potential VSSS that is higher than the ground potential via 204, and is also connected to the ground potential VSS via the N-channel MOS transistor MN205. A control signal STBY2 is connected to the gate electrode of the N-channel MOS transistor MN204. A control signal ACTV2 is connected to the gate electrode of the N-channel MOS transistor MN205.

When the control signal STBY0 becomes “H” and ACTV0 becomes “L”, the cache memory 131 is set.
Is in a standby state, and the voltage VSSS, for example, 0.5 V, where the potential of VSSM is higher than the ground potential.
It becomes. At this time, the voltage applied between the gate and source of the MOS transistor is lowered, and the gate tunnel leakage current is reduced. However, the data in the cache memory is retained without being destroyed.

When the control signal STBY0 is “L” and ACTV0 is “H”, the cache memory 131 is set.
Becomes an operating state, and the potential of VSSM becomes the ground potential VSS. In this case, the gate tunnel leakage current of the MOS transistor increases compared to the standby time.

When the control signal STBY1 becomes “H” and ACTV1 becomes “L”, the CPU circuit 132 enters a standby state, and the potential of VSSM becomes a voltage VSSS higher than the ground potential, for example, 0.5V. At this time, the voltage applied between the gate and source of the MOS transistor is lowered, and the gate tunnel leakage current is reduced. However, the data in the register file and the latch is retained without being destroyed.

When the control signal STBY1 is “L” and ACTV1 is “H”, the CPU circuit 132 is in an operating state, and the potential of VSSM becomes the ground potential VSS. In this case, the gate tunnel leakage current of the MOS transistor increases compared to the standby time.

When the control signal STBY2 becomes “H” and ACTV2 becomes “L”, the IP 138 enters a standby state, and the potential of VSSM becomes a voltage VSSS higher than the ground potential, for example, 0.5V. At this time, the voltage applied between the gate and source of the MOS transistor is lowered, and the gate tunnel leakage current is reduced.

When the control signal STBY2 is “L” and ACTV2 is “H”, the IP 138 is in an operating state and the potential of VSSM becomes the ground potential VSS. In this case, the gate tunnel leakage current of the MOS transistor increases compared to the standby time.

<Example 5>
FIG. 9 shows an embodiment in which the present invention is applied to a microprocessor. The insulation film used for the gate of the MOS transistor is 4nm or less, or the tunnel leakage current is 1.5V.
Thus, it is formed on a semiconductor substrate such as single crystal silicon by using a semiconductor integrated circuit manufacturing technique of 10 ⁻¹² A / μm ² or more.

The microprocessor 135 includes an IP circuit 138, a cache memory 136, and a CPU.
137. A control circuit 139 for controlling the operation and standby state is also mounted on the microprocessor 135.

The power source electrode line VDDM of the cache memory 136 is connected to the potential VDDD lower than the power source potential via the P channel type MOS transistor MP200, and the P channel type M
It is connected to the power supply potential VDD via the OS transistor MP201. P channel type M
A control signal STBYB0 is connected to the gate electrode of the OS transistor MP200.
A control signal ACTVB0 is connected to the gate electrode of the P-channel MOS transistor MP201.

The power source electrode line VDDM of the CPU circuit 137 is connected to the P channel type MOS transistor M.
It is connected to a potential VDDD lower than the power supply potential via P202, and is connected to the power supply potential VDD via a P-channel MOS transistor MP203. A control signal STBYB1 is connected to the gate electrode of the P-channel MOS transistor MP202. A control signal ACTVB1 is connected to the gate electrode of the P-channel MOS transistor MP203.

The power source electrode line VDDM of the IP circuit 138 is connected to the P channel type MOS transistor MP.
It is connected to the power supply potential VDDD lower than the power supply potential through 204, and is connected to the power supply potential VDD through the P-channel MOS transistor MP205. A control signal STBYB2 is connected to the gate electrode of the P-channel MOS transistor MP204. A control signal ACTVB2 is connected to the gate electrode of the P-channel MOS transistor MP205.

When the control signal STBYB0 becomes “L” and ACTVB0 becomes “H”, the cache memory 1
36 is in a standby state where the voltage VDDD is lower than the power supply potential.
0V. At this time, the voltage applied between the gate and source of the MOS transistor decreases,
Gate tunnel leakage current is reduced. However, the data in the cache memory is retained without being destroyed.

When the control signal STBYB0 becomes “H” and ACTVB0 becomes “L”, the cache memory 1
36 becomes an operating state, and the potential of VDDM becomes the power supply potential VDD. In this case, the gate tunnel leakage current of the MOS transistor increases compared to the standby time. When the control signal STBYB1 becomes “L” and ACTVB1 becomes “H”, the CPU circuit 137 enters a standby state and VDD
The potential M becomes a voltage VDDD lower than the power supply potential, for example, 1.0V. At this time, the voltage applied between the gate and source of the MOS transistor is lowered, and the gate tunnel leakage current is reduced. However, the data in the register file and the latch is retained without being destroyed.

When the control signal STBYB1 becomes “H” and ACTVB1 becomes “L”, the CPU circuit 137 enters an operating state, and the potential of VDDM becomes the power supply potential VDD. In this case, the gate tunnel leakage current of the MOS transistor increases compared to the standby time.

When the control signal STBYB2 becomes “L” and ACTVB2 becomes “H”, the IP circuit 138
In a standby state, the potential VDDM becomes a voltage VDDD lower than the power supply potential, for example, 1.0V. At this time, the voltage applied between the gate and source of the MOS transistor is lowered, and the gate tunnel leakage current is reduced.

When the control signal STBYB2 becomes “H” and ACTVB2 becomes “L”, the IP circuit 138
An operating state is entered, and the potential of VDDM becomes the power supply potential VDD. In this case, the gate tunnel leakage current of the MOS transistor increases compared to the standby time.

<Example 6>
FIG. 10 shows an embodiment in which an SRAM or a microprocessor using the present invention is applied to a system operating on a battery such as a mobile phone. The mobile phone 140 is equipped with the battery 141, the SRAM described in the third embodiment, and the microprocessor 130 described in the fourth embodiment. A battery driving terminal, an SRAM, and a microprocessor are provided on a single semiconductor substrate. A circuit 143 that generates a voltage VSSS higher than the ground potential, for example, 0.5 V from the power supply potential VDD is also mounted.

The SRAM 98 is in a standby state when CS is “L”, the ground electrode becomes 0.5 V, and the gate tunnel leakage current is reduced.

The microprocessor 130 is in a standby state when STBY is “H” and ACTV is “L”, the ground electrode becomes 0.5 V, and the gate tunnel leakage current is reduced. As a result, the life of the battery can be extended.

<Example 6>
FIG. 10 shows an embodiment in which an SRAM or a microprocessor using the present invention is applied to a system operating on a battery such as a mobile phone. The mobile phone 140 is equipped with the battery 141, the SRAM described in the third embodiment, and the microprocessor 130 described in the fourth embodiment. A battery driving terminal, an SRAM, and a microprocessor are provided on a single semiconductor substrate. A circuit 143 that generates a voltage VSSS higher than the ground potential, for example, 0.5 V from the power supply potential VDD is also mounted.

The SRAM 98 is in a standby state when CS is “L”, the ground electrode becomes 0.5 V, and the gate tunnel leakage current is reduced.

The microprocessor 130 is in a standby state when STBY is “H” and ACTV is “L”, the ground electrode becomes 0.5 V, and the gate tunnel leakage current is reduced. As a result, the life of the battery can be extended.

<Example 7>
FIG. 11 shows an embodiment in which an SRAM or a microprocessor using the present invention is applied to a system operating with a battery such as a cellular phone. The mobile phone 144 is equipped with a battery 141, an SRAM 146, and a microprocessor 147. A power supply chip 145 that supplies the power supply VDDI of the SRAM 146 and the microprocessor 147 is also mounted.

FIG. 12 shows operation waveforms. During operation, the standby signal STBY becomes "L" and the SRAM
146 and the microprocessor 147 are supplied with the power supply potential VDD. During standby, the standby signal STBY becomes “H” and the power supply potential V is applied to the SRAM 146 and the microprocessor 147.
A potential lower than DD is applied. At this time, the gate tunnel leakage current and the GIDL current are reduced. As a result, the life of the battery can be extended.

Note that the present invention may be applied to a MIS transistor in which the gate oxide film of the MOS transistor in this text is used as an insulating film. According to the present invention, leakage current can be reduced without destroying data.

1 is a circuit diagram of a semiconductor device integrated circuit according to Embodiment 1. FIG. 6 is an operation waveform of the semiconductor device integrated circuit according to the first embodiment. 6 is a circuit diagram of a semiconductor device integrated circuit according to Embodiment 2. FIG. 7 is an operation waveform of the semiconductor device integrated circuit according to the second embodiment. 4 is a circuit diagram of a semiconductor memory device according to Embodiment 3. FIG. FIG. 10 shows operation waveforms during standby and reading according to the third embodiment. FIG. 9 shows operation waveforms during standby and writing according to the third embodiment. 6 is a circuit diagram of a semiconductor integrated circuit according to Embodiment 4. FIG. FIG. 10 is a circuit diagram of a semiconductor integrated circuit according to a fifth embodiment. FIG. 10 is a circuit diagram of a semiconductor integrated circuit according to a sixth embodiment. FIG. 10 is a circuit diagram of a semiconductor integrated circuit according to a seventh embodiment. FIG. 10 is an operation waveform of the semiconductor integrated circuit according to the seventh embodiment. MOS transistor current reduction effect in this method. The leakage current reduction effect concerning Example 3. FIG. 6 is a schematic circuit diagram of a semiconductor memory device according to Embodiment 3. FIG. FIG. 10 is a characteristic diagram of a step-down circuit according to the third embodiment. 1 is a cross-sectional view of main parts of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit according to the present invention. 1 is a cross-sectional view of main parts of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit according to the present invention. 1 is a cross-sectional view of main parts of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit according to the present invention. 1 is a cross-sectional view of main parts of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit according to the present invention. 1 is a cross-sectional view of main parts of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit according to the present invention. The characteristic view at the time of applying the manufacturing method of this invention.

Explanation of symbols

CELL …… SRAM memory cell
MN: N-channel MOS transistor
MP …… P-channel MOS transistor
INV …… Inverter circuit CINV …… Clocked inverter circuit LATCH …… Latch circuit NAND …… NAND circuit AND …… NAND circuit N …… Connection node I …… Input signal O …… Output signal
NL, NR... SRAM memory cell internal node VDD... Power supply potential VDDD... Potential lower than power supply VCC... High power supply potential VDDM supplied from external pad. VSSS …… potential higher than ground potential VSSM …… ground source electrode line DT, DB …… data line SWL …… sub word line STBY …… standby selection signal ACTV …… operation selection signal ACVSSM …… control signal STVSSM …… control signal CVDDD ... Control signal EQ ... Equalize / precharge circuit control signals YSW, YSWB ... Y switch control signal SA ... Sense amplifier control signals RBC, RBCB ... Read data output control signals WBC, WBCB ... Write data input control signals CS …… Chip selection signal WE …… Write selection signal AY …… Y address MAT ...... mat selection signal ATD ...... ATD pulse 98,146 ...... SRAM
99, 100 ... Equalize, precharge circuit 101, 102 ... Y switch circuit 103 ... Sense amplifier circuit 104 ... Read data drive circuit 105 ... Write amplifier circuit 106 ... Basic unit 108, MEMBLK ... Memory cell mat 109, 110 ... Switch circuit 111 ... Data bus 114 ... Word decoder and word driver 115 ... Predecoder 116 ... Address and control signals 117, 118 ... Control circuits 130, 135, 147 ... Microprocessor 131, 136... Cache memory 132, 137... CPU circuit 133, 138... IP circuit 134, 139... Control circuit 140, 144.
FMAT …… Fast mat selection signal PWR …… Step down circuit INBUF …… Input buffer Qmn, Qmp …… N of memory cell portion and P channel type MISFET
Qpn, Qpp ...... N of peripheral circuit part and P channel type MISFET
Qhn, Qhp ... N and P-channel type MISFETs in the high voltage section
200... Semiconductor substrate 201... Device isolation regions 210, 211, 212, 213... Well 221... Insulating film 222 .. Polycrystalline silicon film 223, 270 ... Resist masks 230, 231, 232, 233, 234 235... Gate electrodes 241, 242, 245, 246, 253, 254, 257, 258, 259,
260, 261, 262, 267, 280... N-type semiconductor regions 243, 244, 247, 248, 251, 254, 255, 256, 263,
264, 266, 271... P-type semiconductor region 265... Side wall spacers 290, 291... Silicide film 292. Titanium nitride films 302, 312, 322, 341, 352, 364... Metal films 340, 351, 364... Barrier metal layer 371.

Claims (3)

In a method of manufacturing a semiconductor device having N-channel first and second MIS transistors,
A first P-type well for forming the first MIS transistor in a semiconductor substrate; and the second M
Forming a second P-type well for forming an IS transistor;
Forming a gate insulating film and a gate electrode on the first and second P-type wells;
Injecting phosphorus into the first P-type well;
Injecting arsenic into the second P-type well;
Forming a sidewall film of the gate electrode after implanting phosphorus and arsenic into the first and second P-type wells, respectively;
A method for manufacturing a semiconductor device, comprising: a step of implanting arsenic into the first and second P-type wells after the step of forming a sidewall film of the gate electrode. The semiconductor device includes an SRAM memory cell and a circuit for controlling the SRAM memory cell.
The N-channel MIS transistor in the SRAM memory cell is composed of the first MIS transistor,
2. The method of manufacturing a semiconductor device according to claim 1, wherein an N-channel MIS transistor in the circuit to be controlled is configured by the second MIS transistor. The semiconductor device further includes an input / output circuit including an N-channel third MIS transistor,
In the step of forming the first and second P-type wells, a third P-type well for forming the third MIS transistor is formed.
In the step of forming the gate insulating film and the gate electrode, a gate insulating film and a gate electrode are formed on the third P-type well,
In the step of injecting arsenic into the first and second P-type wells after forming the sidewall film of the gate electrode, arsenic is injected into the third P-type well,
3. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of injecting arsenic and phosphorus into the third P-type well before the step of forming the sidewall film of the gate electrode.