JPS631076A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory having excellent memory holding characteristics by removing an insulating film formed onto a substrate, depositing a nonsingular crystal Si film onto the substrate and shaping a floating gate through heat treatment. CONSTITUTION:A first insulating film 23 is formed onto an element region surface in a semiconductor substrate 21, a section as a drain region or a source region in the insulating film 23 or each section as both regions is removed to expose the substrate 12, a nonsingular crystal Si film 24 as a floating gate is deposited on the whole surface, and a single crystal film 25 is shaped through annealing in an N2, atmosphere at a high temperature. P is doped to the film 25 through thermal diffusion and a thermal oxide film 26 is formed, and a polycrystalline Si film 27 for a control gate is deposited. A photo-resist pattern 28 is shaped partially to the film 27. The films 27, 26, 25, 23 are etched in succession, using the pattern 28 as a mask, thus forming a gate oxide film 29, the floating gate 30, a gate oxide film 31 and the control gate 32.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor memory device having a floating gate, and in particular, a method for manufacturing a semiconductor memory device having a structure with improved memory retention characteristics. It is related to.

(Prior art) EPROM (dan-rasable programmable)
QeadOnly Memory) is widely used as a read-only memory that can be replaced. A conventional memory cell tM2 of an EPROM and its manufacturing method will be described below with reference to the drawings.
Fig. 3 is a cross-sectional view of a conventional EPROM cell, and Fig. 4 is a sectional view of a conventional EPROM cell. There is a cross-sectional view C showing the main steps of the I-soaking method.

First, a first thermal oxidation layer 3 is formed on the surface of an island-shaped element region recessed in a field oxide film of a P-type silicon substrate 1, and a first polycrystalline silicon layer 3 is formed, which becomes a floating layer on the entire surface. jff v4tl'. Next, a second thermal oxide film 4 is formed on the surface of the first polycrystalline silicon film 3 by performing low-temperature oxidation at, for example, 1000°C or less, and then a second polycrystalline silicon film 5 that will become a control gate is formed on the entire surface. Jet product (see Figure 4(a)). Next, a photoresist pattern 6 is formed by photolithography, and using this as a mask, the second polycrystalline silicon II 9, the second thermal oxide film, the first polycrystalline silicon layer, and the first thermal oxide IIQ are sequentially etched. A first gate oxide layer 12, a floating gate 13, a second gate oxidized film 14, and a control gate 15 are then formed. Next, using these as a mask, N-type impurities such as AS are ion-implanted (see FIG. 4(b)). After removing the resist mask, oxidation is performed to form a post-oxide film 7 on the surface of the control gate 15, the side surface of the floating gate 13, and the exposed surface of the Ll substrate, and 1) a.
An N+ type drain region 8 is formed by activating the s ion implantation layer.
and source region 9 is formed. Next, deposit, for example, PSGIItAlo as a passivation layer on the entire surface (
See Figure 4 (C)>. Next, this PSG film 10 and a part of the thermal oxide film 7 are selectively etched to form a contact ball 16, and an Al-81 film is deposited on the entire surface and then repatterned to form a drain electrode 17 and a source electrode. Electrodes 18 are formed to manufacture the EPROM memory (see FIG. 3).

The above-mentioned EPROM has an advice r for writing by applying a high positive voltage to the cell 1, the N+ type drain region 8 and the control gate 15 of the transistor, and injecting electrons into the floating groups 1 to 13.

However, fortune telling 1v, control gate 15
When a high positive voltage is applied to the floating gate 13, the electrons injected into the floating gate 13 leak to the control circuit 15, which erases the memory.

(Problems to be Solved by the Invention) In the EPROM described above, electrons are injected into the floating gate 1 through the insertion operation, and these injected electrons must be stored in the floating gate for a long period of time. However, if a positive AT pressure is applied to the control gate due to some unspecified cause, the injected electrons may be absorbed by the control gate, and the memory may be erased without realizing it. Although rare, C is a fatal defect for EPROMs.

A fourth object of the present invention is to provide a method for manufacturing a semiconductor memory device that can prevent leakage of electrons injected into the floating gate, have good memory retention characteristics, and improve yield.

[Structure of the Invention] (Means for Solving the Problems) A method for manufacturing a semiconductor memory device of the present invention includes forming a first insulating film on the surface of an element region of a semiconductor IA substrate of one conductivity type; After removing 811 portions of the first insulating film that are in contact with the drain region, the source region, or both regions and exposing the substrate, the first non-uniform film becomes a floating goo on the entire surface. After the crystalline silicon film is deposited, the main point is to perform heat treatment to form a second insulating film (for example, a thermal oxide film) on the surface of the first non-single crystal silicon film.

(Function) In the conventional manufacturing method, the surface leakage of electrons injected into the floating gate is due to the breakdown voltage deterioration of the second insulating film formed on the floating gate, as will be described later. The interface between the first polycrystalline silicon film, which will become the floating gate, and the second insulating film is uneven
This is thought to be due to the presence of RACC aspevity.

In the manufacturing method of the present invention, after exposing a portion of the substrate,
The entire surface is coated with the first non-illuminated silicone,
By heat-treating this, the non-monocrystalline silicon IQ is reduced to a single product from the interface with the exposed surface of the substrate, which spreads to pirates. The first non-t11 crystallized in this way
Even if a second insulating film (in this case, a thermal oxide film) is formed using a secondary acid (11) on the surface area of the crystalline silicon film (hereinafter referred to as the L1 silicon film) The unevenness at the interface between the second insulating film and the first single-crystal silicon film is extremely reduced, the withstand voltage of the second insulating film is improved, and leakage of electrons injected into the floating gate can be prevented.

[Example J The leakage of electrons injected into the floating gate is
This was due to deterioration of the breakdown voltage of the second gate oxide film, and the cause was thought to be as follows. That is, since the first polycrystalline silicon film, which becomes the floating gate, is composed of grains with various plane orientations, a second thermal oxide film, which becomes the second gate, is formed by low-temperature oxidation at 1000° C. or less. As a result, the interface between the floating gate and the second gate oxide film becomes uneven, and the withstand voltage of the second gate oxide film is degraded by IU.

Although this phenomenon can be alleviated by 8-temperature wrestling at temperatures above 1100°C, the effect is not sufficient, and the Oi depletion process can be done by changing the depth of the impurity layer formed in advance or by changing the depth of the impurity layer formed beforehand. This is not an effective countermeasure because it causes warping, which leads to deterioration of device performance and a decrease in yield. The present invention was made based on the above findings.

The present invention will be described below as EP ROM L! An embodiment applied to the production of a cell will be described with reference to FIGS. 1(a) to 1).

Droplet resistivity 10-20Ωcm, surface orientation (911) 1]
A field oxidation film 11U 22 having a thickness of 1.2 μm is formed on the surface of the mold silicon substrate 21 using a conventional selective oxidation technique (see FIG. 1(a)).

Next, thermal oxidation is performed and the field oxidation is +1! A first insulating layer 23 (thermal oxide film) 23 is formed on the surface of the island-like element 22 surrounded by 500 layers.

Next, a portion of the first thermal oxide film 23 intended as a drain region is selectively removed using NH4F to expose the surface of the silicon substrate 21 (see FIG. 1(b)).

Thereafter, a first non-single-crystalline silicon film (amorphous silicon film) 24 with a thickness of 1,000 layers was deposited on the entire surface by the CVD method to form a floating film, and then deposited in an N2 atmosphere at 700°C. Then, a first single crystal silicon layer 25 is formed (see FIG. 1C).

Next, the first monocrystalline silicon belly is doped with phosphorus by thermal diffusion, and then thermally oxidized at 1000° C. to form a second thermal oxide film 26 with a thickness of 500 μm. Thickness 3! A second polycrystalline silicon film 27 is deposited to serve as a control gate with a sheet resistance of 20Ω.

Subsequently, a photoresist pattern 28 is partially formed on this second polycrystalline silicon film 27 (FIG. 1(d)
)reference).

Next, using this photoresist pattern 28 as a mask, the second polycrystalline silicon film 27, the second thermal oxide film 26,
The first monocrystalline silicon II film 25 and the first thermal oxide film 23 were sequentially etched to form a first gate oxide film 29, a floating gate 30, a second gate oxide film 31, and a control gate 32. Next, △S is energy eobcv, to-Xfa 2.5x 10+5
/Cm20) 1t'F tee; A'n Eiri zuru (Figure 1 (
(Resin 1 (ζ(n.

Next, after removing the front 11α photoresist butter 28, thermal oxidation is performed at 100° C. to form a post-oxide film 33 with a thickness of 500 mm. At this time, the AS ion-implanted layer is activated, and the N
Type 1 drain region 34 and source region 35 are formed. Next, as a passivation film, a thickness of 0.8
A PSG film 36 having a thickness of .mu.m is deposited (see FIG. 1(f)).

Next, -81(
A contact hole 37 is formed by selectively etching the contact hole 37, and further the thickness is 1.0 μm (1) AI-8i
After depositing llu, buttering and drain Raijin 3
8 and a source electrode (439) to manufacture an EPROM hill (see FIG. 1(g)).According to the present invention, however, in the process shown in FIG. 1(c), the first amorphous silicon I&
) 2 /l'c N , by annealing in an atmosphere, single crystallization occurs from the Zλ-extended interface of the substrate 21, and the first amorphous ? 1. The silicon film is made into a single crystal. The surface of the first single crystal silicon 11025 is subjected to low temperature oxidation at 1000'C to transform it into a second thermally oxidized film 26 and the first single crystallized silicon 11025. Irregularities at the interface with the silicon film 25
asperity) is greatly reduced. As a result of this, even if some random high voltage of 1 is applied to the control gate 32 of the EPROM shown in FIG. Able to retain memory well. Furthermore, since this method employs a low-temperature process, there is no problem that the yield of semiconductor memory devices decreases due to warping of the wafer or the like.

In this embodiment, an amorphous silicon film is used as the first non-monocrystalline silicon film in the process shown in FIG. 1(C), but a polycrystalline silicon film may also be used.

However, an amorphous silicon film is more desirable because it can be more easily turned into a single crystal than a polycrystalline silicon film in the next heat treatment step.

In addition, by removing the thermal oxidation layer 19 from both the drain region and the source region after forming the first thermal oxide film in the process shown in FIG. 1(b'), the following new effects can be obtained. can get. This method will be explained with reference to FIG.
That is, after removing the oxide film on both the drain and source regions, the first amorphous silicon film is subjected to HE deposition, and heat treatment is performed in an N2 atmosphere. Then, almost the entire first amorphous silicon film is turned into a single crystal. Next, a step similar to that shown in FIG. 1(d) is performed, but in the next step, the first single crystal silicon film 25 and the second polycrystalline silicon HA 27 on the drain and source regions are left, so that a small A resist pattern 28 is provided on the polycrystalline silicon film 27'' in both the drain and source regions (see FIG. 2(a)). Next, using the Moeki bottom resist pattern 28 as a mask, the same process as shown in FIG.
(See figure (b)).

Further, a post-oxidation film 33 is formed, and the PSG film 36 is
(See Figure 2 (C)). Next, in the same manner as in the step shown in FIG. 1(g), a hole 37 is opened in the contact 1, and a drain electrode 38 and a source electrode 39 are formed (see FIG. 2(d).
)reference).

In this method, since the first monocrystalline silicon film doped with phosphorus and having low resistance is left on the drain region and the source region, the contact hole 37 of the electrode wiring is left as shown in FIG. 2(d). The lateral margin has become larger, and the yield has improved significantly.

[Effects of the Invention] In the manufacturing method of the present invention, after forming the first gate oxide film, the substrate surface of the drain and source regions is exposed, and the first non-conductor layer, which becomes the floating goo 1-, is exposed. Since a single crystal silicon film is deposited and subjected to heat treatment, this non-single crystal silicon film can be easily turned into a single crystal. The breakdown voltage of the second gate oxide film formed on the surface of the single-crystal floating gate is significantly improved compared to the breakdown voltage of the second Goo 1-oxide film formed on the conventional polycrystalline silicon film. do. Therefore, the electrons injected into the floating gate by the write operation leak even if a random positive high voltage is applied to the control gate.
It showed good memory retention properties.

In addition, since the second oxidation film is formed on the surface of the tli crystallized silicon film, a withstand voltage of 600% can be obtained by low-temperature oxidation, and the yield of devices is also improved.

In addition, in the manufacturing method of the present invention that exposes the substrate surface of both the drain and source regions, it is possible to leave a low-resistance single-crystal silicon film on both regions, and in this case, it is possible to leave a low-resistance single-crystal silicon film on both regions. The directional margin is increased and the yield is significantly improved.

[Brief explanation of the drawing]

FIG. 1 shows the E P Rolvl in J5 according to the embodiment of the present invention.
T? FIG. 2 is a sectional view showing a manufacturing method of another embodiment of the present invention, and FIG.
FIG. 4 is a cross-sectional view of a PROM cell according to a conventional EPROM manufacturing method. 21...P-type silicon substrate, 23...0'! 1
insulating film (thermal oxide film), 24...first non-single crystal silicon B'A (amorphous?1 silicon 11Q), 255
...first monocrystalline silicon film, 26...second absolute silicon film) φ (thermal oxide film), 27...second polycrystalline silicon film, 29...first gate Oxide film, 30...
・Floating group 1-131...Second game 1-oxidation j1ω, 32...]n 1~roll group 1~, 34
...l\゛ type train rogue, 35...N+ type source region. Figure 1 (2) - To - To ~ To C ~ ^ [N ℃

Claims (1)

[Claims] 1. In a method for manufacturing a semiconductor memory device in which a floating gate is formed on a semiconductor substrate of one conductivity type, after forming a first insulating film on the substrate, a portion scheduled as a drain region is formed. and a portion scheduled as a source region, after removing the first insulating film from at least one portion of the substrate, depositing a non-single crystal silicon film on the substrate, and performing heat treatment. A method for manufacturing a semiconductor memory device. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the non-single crystal silicon film is an amorphous silicon film. 3. The method of manufacturing a semiconductor memory device according to claim 1, wherein after forming the first insulating film, both portions of the first insulating film, which are intended as a drain region and a source region, are removed.