JPS6311785B2 - - Google Patents
Info
- Publication number
- JPS6311785B2 JPS6311785B2 JP59149179A JP14917984A JPS6311785B2 JP S6311785 B2 JPS6311785 B2 JP S6311785B2 JP 59149179 A JP59149179 A JP 59149179A JP 14917984 A JP14917984 A JP 14917984A JP S6311785 B2 JPS6311785 B2 JP S6311785B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon film
- film
- single crystal
- crystal silicon
- oxygen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000007789 gas Substances 0.000 claims description 24
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 23
- 239000001301 oxygen Substances 0.000 claims description 23
- 229910052760 oxygen Inorganic materials 0.000 claims description 23
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 20
- 239000011261 inert gas Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- 230000001590 oxidative effect Effects 0.000 claims description 9
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 19
- 230000015556 catabolic process Effects 0.000 description 14
- 238000007254 oxidation reaction Methods 0.000 description 14
- 230000003647 oxidation Effects 0.000 description 12
- 230000002829 reductive effect Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体記憶装置の製造方法の改良に関
する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a method for manufacturing a semiconductor memory device.
従来第１図図示のEPROM（Electrically
Programmable Read Only memory）は例えば
以下のようにして製造されている。
Conventionally, EPROM (Electrically
Programmable Read Only memory) is manufactured, for example, as follows.
まず、例えばP-型シリコン基板１の図示しな
いフイールド酸化膜によつて囲まれた島状の素子
領域表面に第１の酸化膜を形成した後、全面にフ
ローテイングゲートとなる第１の多結晶シリコン
膜を堆積する。次に、この第１の多結晶シリコン
膜に例えばPOCl3を拡散源としてリンをドープし
た後、その一部を選択的にエツチングする。つづ
いて、例えば酸化性ガスとして酸素又は水蒸気を
用いて1000℃以下の低温酸化を行ない、第１の多
結晶シリコン膜の表面に第２の熱酸化膜を形成し
た後、全面にコントロールゲートとなる第２の多
結晶シリコン膜を堆積し、不純物をドープする。
次いで、写真蝕刻法により第２の多結晶シリコン
膜、第２の熱酸化膜、第１の多結晶シリコン膜及
び第１の熱酸化膜を順次エツチングして、第１の
ゲート酸化膜２、フローテイングゲート３、第２
のゲート酸化膜４及びコントロールゲート５を形
成する。つづいて、これらをマスクとして利用
し、Ｎ型不純物、例えばAsをイオン注入する。
つづいて、熱酸化を行ない、前記コントロールゲ
ート５の表面、フローテイングゲート３の側面及
び露出した基板１の表面に後酸化膜６を形成する
とともに、前記Asイオン注入層を活性化してN+
型ソース、ドレイン領域７，８を形成する。次い
で、全面にパツシベーシヨン膜としてPSG膜９
を堆積した後、このPSG膜９及び前記後酸化膜
６の一部を選択的にエツチングしてコンタクトホ
ール１０，１０を開孔し、更に全面にAl―Si膜
を蒸着した後、パターニングしてソース電極１１
及びドレイン電極１２を形成してEPROMセルを
製造する。 First, for example, after forming a first oxide film on the surface of an island-shaped element region surrounded by a field oxide film (not shown) of a P - type silicon substrate 1, a first polycrystalline film that will become a floating gate is formed on the entire surface. Deposit a silicon film. Next, this first polycrystalline silicon film is doped with phosphorus using, for example, POCl 3 as a diffusion source, and then a portion of it is selectively etched. Next, a second thermal oxide film is formed on the surface of the first polycrystalline silicon film by performing low-temperature oxidation at a temperature of 1000°C or less using, for example, oxygen or water vapor as an oxidizing gas, and then the entire surface becomes a control gate. A second polycrystalline silicon film is deposited and doped with impurities.
Next, the second polycrystalline silicon film, the second thermal oxide film, the first polycrystalline silicon film, and the first thermal oxide film are sequentially etched by photolithography to form the first gate oxide film 2 and the first gate oxide film 2. Taing Gate 3, 2nd
A gate oxide film 4 and a control gate 5 are formed. Next, using these as a mask, N-type impurities such as As are ion-implanted.
Subsequently, thermal oxidation is performed to form a post-oxidation film 6 on the surface of the control gate 5, the side surface of the floating gate 3, and the exposed surface of the substrate 1, and to activate the As ion-implanted layer to N +
Type source and drain regions 7 and 8 are formed. Next, a PSG film 9 is applied as a passivation film to the entire surface.
After depositing, this PSG film 9 and a part of the post-oxidation film 6 are selectively etched to form contact holes 10, 10, and an Al--Si film is further deposited on the entire surface, followed by patterning. Source electrode 11
Then, a drain electrode 12 is formed to manufacture an EPROM cell.
上述したEPROMセルはセルトランジスタの
N+型ドレイン領域８とコントロールゲート５と
に正の高電圧を印加してフローテイングゲート３
へ電子を注入し、書込みを行なうデバイスであ
る。 The EPROM cell described above has a cell transistor
A positive high voltage is applied to the N + type drain region 8 and the control gate 5 to make the floating gate 3
This is a device that performs writing by injecting electrons into the memory.
しかしながら、書込み後コントロールゲート５
に正の高電圧を印加すると、フローテイングゲー
ト３への注入電子がコントロールゲート５へ抜
け、記憶が保持されない場合があるという欠点が
ある。 However, after writing, control gate 5
If a high positive voltage is applied to the floating gate 3, the electrons injected into the floating gate 3 may escape to the control gate 5, resulting in a disadvantage that the memory may not be retained.
これは第２のゲート酸化膜４の耐圧劣化のため
であり、その原因は以下のように考えられる。す
なわち、フローテイングゲートとなる第１の多結
晶シリコン膜は種々の面方位を有するグレインか
ら構成されているため、表面に凹凸（surfase
asperity）がある。これを1000℃以下の低温酸化
により酸化し、第２のゲート酸化膜４を形成する
と、フローテイングゲート３と第２のゲート酸化
膜４との界面に凹凸が生じる。これが第２のゲー
ト酸化膜４の耐圧劣化を招くものである。 This is due to the deterioration of the withstand voltage of the second gate oxide film 4, and the cause is thought to be as follows. In other words, since the first polycrystalline silicon film that becomes the floating gate is composed of grains with various plane orientations, the surface has irregularities.
asperity). When this is oxidized by low-temperature oxidation at 1000° C. or less to form the second gate oxide film 4, irregularities are generated at the interface between the floating gate 3 and the second gate oxide film 4. This causes deterioration of the breakdown voltage of the second gate oxide film 4.
このような現象は1100℃以上の高温プロセスに
よつて緩和されるが、高温プロセスは予め形成さ
れた接合の位置を変えたり、ウエハの反りをもた
らす等のため、デバイスの性能を劣化させ、歩留
りを低下させることになるので有効な対策とはな
りえない。 This phenomenon can be alleviated by high-temperature processes of 1100°C or higher, but high-temperature processes change the positions of pre-formed bonds and cause wafer warping, which deteriorates device performance and reduces yield. This cannot be an effective countermeasure because it will reduce the
本発明は上記事情に鑑みてなされたものであ
り、デバイスの歩留りを低下することなく、第２
のゲート酸化膜の耐圧を向上し、記憶保持特性の
良好な半導体記憶装置を製造し得る方法を提供し
ようとするものである。
The present invention has been made in view of the above circumstances, and it is possible to obtain a second method without reducing the yield of devices.
The present invention aims to provide a method for manufacturing a semiconductor memory device with good memory retention characteristics by improving the withstand voltage of a gate oxide film.
本発明の半導体記憶装置の製造方法は、第１導
電型の半導体基板の素子領域表面に第１の絶縁膜
を形成し、全面に不純物をドープした第１の非単
結晶シリコン膜を堆積した後、微量の酸素を含む
不活性ガス中で熱処理し、更に微量の酸素を含む
不活性ガスを酸化性ガスに変えて熱処理を行な
い、第１の非単結晶シリコン膜の表面に第２の絶
縁膜（熱酸化膜）を形成、次いで第２の非単結晶
シリコン膜の堆積、パターニングおよび第２導電
型のソース、ドレイン形成を行なうことを骨子と
するものである。
The method for manufacturing a semiconductor memory device of the present invention includes forming a first insulating film on the surface of an element region of a semiconductor substrate of a first conductivity type, and depositing a first non-monocrystalline silicon film doped with impurities over the entire surface. A second insulating film is formed on the surface of the first non-single crystal silicon film by heat treatment in an inert gas containing a trace amount of oxygen, and then heat treatment by changing the inert gas containing a trace amount of oxygen to an oxidizing gas. The main points of this method are to form a (thermal oxide film), then deposit and pattern a second non-single crystal silicon film, and form a second conductivity type source and drain.
上述したように微量の酸素を含む不活性ガス中
で熱処理を行なうことにより、第１の非単結晶シ
リコン膜にドープされた不純物の濃度を均一にす
るとともに第１の非単結晶シリコン膜中に予め存
在している応力を緩和することができる。この状
態を保つたまま微量の酸素を含む不活性ガスを酸
化性ガスに変えて熱処理を行なうと第１の非単結
晶シリコン膜の表面は均等に酸化され、第２の絶
縁膜（熱酸化膜）の膜厚が均一となる。また、微
量の酸素を含む不活性ガス中での熱処理により第
１の非単結晶シリコン膜中のグレインの成長も同
時に起り、この結果表面の凹凸が少なくなつてい
るため、酸化性ガスを用いた低温酸化により第２
の絶縁膜を形成した場合、第２の絶縁膜と第１の
非単結晶シリコン膜との界面における凹凸を低減
することができる。微量の酸素を含む不活性ガス
中での熱処理により第１の非単結晶シリコン膜の
表面に数＋Åの酸化膜が形成され、第１の非単結
晶シリコン膜の表面が荒れるのを防止するととも
に第１の非単結晶シリコン膜から不純物が蒸発す
るのを防止する保護膜となるため、第２の絶縁膜
の耐圧のバラツキを低減することができる。しか
も、この酸化膜は極めて薄いため、上述したよう
な耐圧を改善する効果には何等悪影響を与えな
い。 As described above, by performing heat treatment in an inert gas containing a trace amount of oxygen, the concentration of impurities doped in the first non-single crystal silicon film is made uniform, and the concentration of impurities doped in the first non-single crystal silicon film is made uniform. Pre-existing stress can be alleviated. If heat treatment is performed by changing the inert gas containing a trace amount of oxygen to an oxidizing gas while maintaining this state, the surface of the first non-single crystal silicon film will be uniformly oxidized, and the second insulating film (thermal oxide film) will be formed. ) becomes uniform in film thickness. In addition, grain growth in the first non-single-crystal silicon film also occurs at the same time due to the heat treatment in an inert gas containing a trace amount of oxygen, and as a result, the surface unevenness is reduced. 2nd by low temperature oxidation
When an insulating film is formed, unevenness at the interface between the second insulating film and the first non-single crystal silicon film can be reduced. By heat treatment in an inert gas containing a trace amount of oxygen, an oxide film with a thickness of several Å is formed on the surface of the first non-single crystal silicon film, which prevents the surface of the first non-single crystal silicon film from becoming rough. Since this serves as a protective film that prevents impurities from evaporating from the first non-single crystal silicon film, variations in breakdown voltage of the second insulating film can be reduced. Moreover, since this oxide film is extremely thin, it does not have any adverse effect on the above-mentioned effect of improving breakdown voltage.
なお、本発明において、酸化性ガスをアルゴン
もしくは窒素又はこれらの混合ガスと、酸素もし
くは水蒸気又はこれらの混合ガスとの混合ガスと
し、酸素を微量に含む不活性ガス中で熱処理した
ときの温度を維持したまま更に酸素を微量に含む
不活性ガスを酸化性ガスに変えて熱処理を行な
い、第１の非単結晶シリコン膜の表面に第２の絶
縁膜（熱酸化膜）を形成するようにすれば、酸素
又は水蒸気の分圧により第２の絶縁膜の膜厚を制
御することができる。 In addition, in the present invention, the oxidizing gas is a mixture of argon, nitrogen, or a mixture thereof, and oxygen, water vapor, or a mixture thereof, and the temperature when heat-treated in an inert gas containing a trace amount of oxygen is While maintaining the temperature, a heat treatment is performed by changing an inert gas containing a small amount of oxygen to an oxidizing gas to form a second insulating film (thermal oxide film) on the surface of the first non-single crystal silicon film. For example, the thickness of the second insulating film can be controlled by the partial pressure of oxygen or water vapor.
以下、本発明の実施例を第２図ａ〜ｆを参照し
て説明する。
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 2a to 2f.
まず、比抵抗10〜20Ω−cm、面方位（911）の
P-型シリコン基板２１表面に通常の選択酸化技
術を用いて、膜厚1.2μmのフイールド酸化膜２２
を形成した（第２図ａ図示）。次に、熱酸化を行
ない、前記フイールド酸化膜２２によつて囲まれ
た島状の素子領域表面に膜厚500μmの第１の熱酸
化膜２３を形成した。つづいて、CVD法により
全面にフローテイングゲートとなる膜厚3500Åの
第１の多結晶シリコン膜２４を堆積した。つづい
て、POCl3を拡散源として第１の多結晶シリコン
膜２４にリンをドープし、ρs＝15Ω／□とした。
つづいて、1000℃、O2濃度0.005％のArガス中に
おいて10分間アニールを行ない、更に1000℃の温
度を保つたまま前記ガスをAr：O2＝１：１の混
合ガスに変えて熱酸化を行ない、第１の多結晶シ
リコン膜２４の表面に膜厚500Åの第２の熱酸化
膜２５を形成した（同図ｂ図示）。 First, with a specific resistance of 10 to 20 Ω-cm and a plane orientation (911),
A field oxide film 22 with a thickness of 1.2 μm is formed on the surface of the P - type silicon substrate 21 using a conventional selective oxidation technique.
was formed (as shown in Figure 2a). Next, thermal oxidation was performed to form a first thermal oxide film 23 with a thickness of 500 μm on the surface of the island-shaped element region surrounded by the field oxide film 22. Subsequently, a first polycrystalline silicon film 24 having a thickness of 3500 Å was deposited over the entire surface by CVD to serve as a floating gate. Subsequently, the first polycrystalline silicon film 24 was doped with phosphorus using POCl 3 as a diffusion source to set ρs=15Ω/□.
Next, annealing was performed for 10 minutes at 1000°C in Ar gas with an O 2 concentration of 0.005%, and then thermal oxidation was performed by changing the gas to a mixed gas of Ar:O 2 = 1:1 while maintaining the temperature at 1000°C. A second thermal oxide film 25 having a thickness of 500 Å was formed on the surface of the first polycrystalline silicon film 24 (as shown in FIG. 2B).
次いで、全面に膜厚3500Å、ρs＝20Ω／□のコ
ントロールゲートとなる第２の多結晶シリコン膜
２６を堆積した。つづいて、この第２の多結晶シ
リコン膜２６上に写真蝕刻法により部分的にホト
レジストパターン２７を形成した（同図ｃ図示）。
次いで、このホトレジストパターン２７をマスク
として前記第２の多結晶シリコン膜２６、第２の
熱酸化膜２５、第１の多結晶シリコン膜２４及び
第１の熱酸化膜２３を順次パターニングして第１
のゲート酸化膜２８、フローテイングゲート２
９、第２のゲート酸化膜３０及びコントロールゲ
ート３１を形成した。つづいて、これらをマスク
としてAs+をエネルギー60keV、ドーズ量2.5×
1015cm-2の条件でイオン注入した（同図ｄ図示）。 Next, a second polycrystalline silicon film 26 was deposited over the entire surface to be a control gate with a film thickness of 3500 Å and ρs = 20Ω/□. Subsequently, a photoresist pattern 27 was partially formed on the second polycrystalline silicon film 26 by photolithography (as shown in figure c).
Next, using this photoresist pattern 27 as a mask, the second polycrystalline silicon film 26, second thermal oxide film 25, first polycrystalline silicon film 24, and first thermal oxide film 23 are sequentially patterned to form a first
gate oxide film 28, floating gate 2
9. A second gate oxide film 30 and a control gate 31 were formed. Next, using these as masks, apply As + at an energy of 60 keV and a dose of 2.5×
Ion implantation was performed under conditions of 10 15 cm -2 (shown in d of the same figure).
次いで、前記ホトレジストパターン２７を除去
した後、1000℃で熱酸化を行ない、膜厚500Åの
後酸化膜３２を形成した。この際、前記Asイオ
ン注入層が活性化してρs＝30〜40Ω／□、xj＝
0.4μmのN+型ソース、ドレイン領域３３，３４
が形成された。つづいて、パツシベーシヨン膜と
して膜厚0.8μmのPSG膜３５を堆積した（同図ｅ
図示）。次いで、前記PSG膜３５及び後酸化膜３
２の一部を選択的にエツチングしてコンタクトホ
ール３６，３６を開孔し、更に全面に膜厚1.0μm
のAl―Si膜を堆積した後、パターニングしてソ
ース電極３７、ドレイン電極３８を形成し、
EPROMセルを製造した（同図ｆ図示）。 Next, after removing the photoresist pattern 27, thermal oxidation was performed at 1000° C. to form a post-oxide film 32 with a thickness of 500 Å. At this time, the As ion-implanted layer is activated and ρs=30 to 40Ω/□, xj=
0.4 μm N + type source and drain regions 33 and 34
was formed. Subsequently, a PSG film 35 with a thickness of 0.8 μm was deposited as a passivation film (Fig.
(Illustrated). Next, the PSG film 35 and the post-oxide film 3
Contact holes 36, 36 are formed by selectively etching a part of 2, and a film thickness of 1.0 μm is formed on the entire surface.
After depositing an Al--Si film, patterning is performed to form a source electrode 37 and a drain electrode 38.
An EPROM cell was manufactured (shown in figure f).
しかして、本発明方法によれば、第２図ｂの工
程でPOCl3を拡散源として第１の多結晶シリコン
膜２４にリンをドープした後、1000℃、O2濃度
0.005％のArガス中において10分間アニールを行
ない、更に1000℃の温度を維持したまま前記ガス
をAr：O2＝１：１の混合ガスに変えて熱酸化
（稀釈酸化）を行なうことにより第２の熱酸化膜
２５を形成しているので、第２の熱酸化膜２５の
膜厚の均一化、第２の熱酸化膜２５と第１の多結
晶シリコン膜２４との界面の凹凸の低減及び第１
の多結晶シリコン膜２４からの不純物の蒸発の防
止により第２の熱酸化膜２５の耐圧を著しく向上
できるとともに耐圧のバラツキを低減することが
できる。 According to the method of the present invention, after doping the first polycrystalline silicon film 24 with phosphorus using POCl 3 as a diffusion source in the step shown in FIG .
Annealing was performed for 10 minutes in 0.005% Ar gas, and then thermal oxidation (dilution oxidation) was performed by changing the gas to a mixed gas of Ar:O 2 =1:1 while maintaining the temperature of 1000°C. Since the second thermal oxide film 25 is formed, the thickness of the second thermal oxide film 25 is made uniform and the unevenness of the interface between the second thermal oxide film 25 and the first polycrystalline silicon film 24 is reduced. and the first
By preventing evaporation of impurities from the polycrystalline silicon film 24, the breakdown voltage of the second thermal oxide film 25 can be significantly improved, and variations in breakdown voltage can be reduced.
例えば、第３図ａに従来のように通常の熱酸化
を行なつた場合の第２の熱酸化膜の耐圧を、また
同図ｂに上記実施例の場合の第２の熱酸化膜の耐
圧をそれぞれ示す。これらの図から明らかなよう
に上記実施例の方法で形成された第２の熱酸化膜
の方が耐圧が著しく向上し、しかも耐圧のバラツ
キも極めて小さい。この結果、第２図ｆ図示の
EPROMセルに書込み後、コントロールゲート３
１に正の高電圧を印加しても記憶を良好に保持す
ることができる。また、低温プロセスを採用して
いるので、ウエハの反り等が発生して半導体メモ
リデバイスの歩留りが低下するという問題は生じ
ない。 For example, Fig. 3a shows the breakdown voltage of the second thermal oxide film when normal thermal oxidation is performed as in the conventional method, and Fig. 3b shows the breakdown voltage of the second thermal oxide film in the case of the above embodiment. are shown respectively. As is clear from these figures, the second thermal oxide film formed by the method of the above embodiment has a significantly improved breakdown voltage, and the variation in breakdown voltage is also extremely small. As a result, as shown in Fig. 2 f
After writing to EPROM cell, control gate 3
Even if a high positive voltage is applied to 1, the memory can be retained well. Furthermore, since a low-temperature process is employed, there is no problem that the yield of semiconductor memory devices decreases due to wafer warping or the like.
なお、上記実施例では微量の酸素を含む不活性
ガスとしてO2濃度0.005％のArガスを用いたが、
不活性ガスとして窒素又はアルゴンと窒素との混
合ガスを用いてもよい。また、第４図に示すAr
ガス中の酸素濃度と第２の熱酸化膜の耐圧との関
係からわかるように酸素濃度が10％を超えると耐
圧が劣化するので、不活性ガス中の酸素濃度は10
％以下であることが望ましい。 In the above example, Ar gas with an O 2 concentration of 0.005% was used as the inert gas containing a trace amount of oxygen.
Nitrogen or a mixed gas of argon and nitrogen may be used as the inert gas. Also, Ar shown in Figure 4
As can be seen from the relationship between the oxygen concentration in the gas and the breakdown voltage of the second thermal oxide film, the breakdown pressure deteriorates when the oxygen concentration exceeds 10%, so the oxygen concentration in the inert gas is 10%.
% or less.
また、上記実施例では酸化性ガスとしてAr：
O2＝１：１の混合ガスを用いたが、これに限ら
ずアルゴンもしくは窒素又はこれらの混合ガス
と、酸素もしくは水蒸気又はこれらの混合ガスと
の混合ガスを用いることができる。また、上記実
施例のように微量の酸素を含む不活性ガスによる
熱処理の温度を維持したまま酸化性ガスにより熱
酸化を行なう場合には、酸素又は水蒸気の分圧を
設定することによつて第２の熱酸化膜の膜厚を制
御することができるので望ましい。 In addition, in the above example, Ar:
Although a mixed gas of O 2 =1:1 was used, the present invention is not limited to this, and a mixed gas of argon or nitrogen or a mixed gas thereof and oxygen or water vapor or a mixed gas thereof may be used. In addition, when performing thermal oxidation with an oxidizing gas while maintaining the temperature of the heat treatment with an inert gas containing a trace amount of oxygen as in the above example, the partial pressure of oxygen or water vapor can be set. This is desirable because the thickness of the thermal oxide film in step 2 can be controlled.
更に、上記実施例ではフローテイングゲート２
９及びコントロールゲート３１の材料として多結
晶シリコンを用いたが、これに限らず非晶質シリ
コンを用いてもよい。 Furthermore, in the above embodiment, the floating gate 2
Although polycrystalline silicon is used as the material for 9 and the control gate 31, the material is not limited to this, and amorphous silicon may also be used.
以上詳述した如く本発明の半導体記憶装置の製
造方法によれば、従来のプロセスを大幅に変更す
る必要がなく、コストアツプやデバイスの歩留り
低下を招くことなしに第２のゲート酸化膜の耐圧
の向上した記憶保持特性の良好な半導体記憶装置
を製造できるものである。
As described in detail above, according to the method of manufacturing a semiconductor memory device of the present invention, it is not necessary to significantly change the conventional process, and the breakdown voltage of the second gate oxide film can be increased without increasing the cost or reducing the yield of the device. A semiconductor memory device with improved memory retention characteristics can be manufactured.
第１図は従来のEPROMセルの断面図、第２図
ａ〜ｆは本発明の実施例におけるEPROMセルの
製造方法を示す断面図、第３図ａは従来の方法に
より形成された第２の熱酸化膜の耐圧のヒストグ
ラム、同図ｂは本発明の実施例の方法により形成
された第２の熱酸化膜の耐圧のヒストグラム、第
４図はアルゴンガス中の酸素濃度と第２の熱酸化
膜の耐圧との関係を示す特性図である。
２１…P-型シリコン基板、２２…フイールド
酸化膜、２３…第１の熱酸化膜、２４…第１の多
結晶シリコン膜、２５…第２の熱酸化膜、２６…
第２の多結晶シリコン膜、２７…ホトレジストパ
ターン、２８…第１のゲート酸化膜、２９…フロ
ーテイングゲート、３０…第２のゲート酸化膜、
３１…コントロールゲート、３２…後酸化膜、３
３，３４…N+型ソース、ドレイン領域、３５…
PSG膜、３６…コンタクトホール、３７…ソー
ス電極、３８…ドレイン電極。
FIG. 1 is a cross-sectional view of a conventional EPROM cell, FIGS. 2 a to f are cross-sectional views showing a method of manufacturing an EPROM cell in an embodiment of the present invention, and FIG. 3 a is a cross-sectional view of a conventional EPROM cell. Fig. 4 shows the histogram of the breakdown voltage of the thermal oxide film, and Fig. 4 shows the histogram of the breakdown voltage of the second thermal oxide film formed by the method of the embodiment of the present invention. FIG. 3 is a characteristic diagram showing the relationship with the withstand voltage of the film. 21... P - type silicon substrate, 22... Field oxide film, 23... First thermal oxide film, 24... First polycrystalline silicon film, 25... Second thermal oxide film, 26...
Second polycrystalline silicon film, 27... Photoresist pattern, 28... First gate oxide film, 29... Floating gate, 30... Second gate oxide film,
31... Control gate, 32... Post oxide film, 3
3, 34...N + type source and drain regions, 35...
PSG film, 36... contact hole, 37... source electrode, 38... drain electrode.
Claims (1)
１の絶縁膜を形成した後、全面に不純物をドープ
した第１の非単結晶シリコン膜を堆積する工程
と、微量の酸素を含む不活性ガス中で熱処理し、
更に微量の酸素を含む不活性ガスを酸化性ガスに
変えて熱処理を行ない、該第１の非単結晶シリコ
ン膜の表面に第２の絶縁膜を形成する工程と、全
面に第２の非単結晶シリコン膜を堆積する工程
と、これら第２の非単結晶シリコン膜、第２の絶
縁膜、第１の非単結晶シリコン膜及び第１の絶縁
膜を順次パターニングする工程と、これらのパタ
ーンをマスクとして第２導電型の不純物をイオン
注入して第２導電型のソース、ドレイン領域を形
成する工程とを具備したことを特徴とする半導体
記憶装置の製造方法。 ２ 第１の非単結晶シリコン膜のパターンをフロ
ーテイングゲート、第２の非単結晶シリコン膜の
パターンをコントロールゲートとする特許請求の
範囲第１項記載の半導体記憶装置の製造方法。 ３ 不活性ガスがアルゴンもしくは窒素又はこれ
らの混合ガスである特許請求の範囲第１項記載の
半導体記憶装置の製造方法。 ４ 酸化性ガスがアルゴンもしくは窒素又はこれ
らの混合ガスと、酸素もしくは水蒸気又はこれら
の混合ガスとの混合ガスである特許請求の範囲第
１項記載の半導体記憶装置の製造方法。 ５ 酸素を微量に含む不活性ガス中で熱処理し、
この熱処理の温度を維持したまま更に酸素を微量
に含む不活性ガスを酸化性ガスに変えて熱処理を
行ない、第１の非単結晶シリコン膜の表面に第２
の絶縁膜を形成する特許請求の範囲第１項記載の
半導体記憶装置の製造方法。[Claims] 1. After forming a first insulating film on the surface of an element region of a semiconductor substrate of a first conductivity type, a step of depositing a first non-single crystal silicon film doped with an impurity over the entire surface; heat treated in an inert gas containing oxygen,
Furthermore, a step of changing an inert gas containing a trace amount of oxygen to an oxidizing gas and performing heat treatment to form a second insulating film on the surface of the first non-single crystal silicon film; A step of depositing a crystalline silicon film, a step of sequentially patterning the second non-single crystal silicon film, the second insulating film, the first non-single crystal silicon film, and the first insulating film, and forming these patterns. 1. A method of manufacturing a semiconductor memory device, comprising the step of ion-implanting impurities of a second conductivity type as a mask to form source and drain regions of a second conductivity type. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the pattern of the first non-single crystal silicon film is a floating gate, and the pattern of the second non-single crystal silicon film is a control gate. 3. The method of manufacturing a semiconductor memory device according to claim 1, wherein the inert gas is argon, nitrogen, or a mixed gas thereof. 4. The method of manufacturing a semiconductor memory device according to claim 1, wherein the oxidizing gas is a mixed gas of argon, nitrogen, or a mixture thereof, and oxygen, water vapor, or a mixture thereof. 5 Heat treatment in an inert gas containing a trace amount of oxygen,
While maintaining this heat treatment temperature, heat treatment is performed by changing the inert gas containing a small amount of oxygen to an oxidizing gas, thereby forming a second non-single crystal silicon film on the surface of the first non-single crystal silicon film.
2. A method for manufacturing a semiconductor memory device according to claim 1, wherein an insulating film is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14917984A JPS6127680A (en) | 1984-07-18 | 1984-07-18 | Manufacture of semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14917984A JPS6127680A (en) | 1984-07-18 | 1984-07-18 | Manufacture of semiconductor memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6127680A JPS6127680A (en) | 1986-02-07 |
| JPS6311785B2 true JPS6311785B2 (en) | 1988-03-16 |
Family
ID=15469521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14917984A Granted JPS6127680A (en) | 1984-07-18 | 1984-07-18 | Manufacture of semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6127680A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0644627B2 (en) * | 1986-06-20 | 1994-06-08 | 株式会社東芝 | Method of manufacturing semiconductor memory device |
| JP2667550B2 (en) * | 1989-05-30 | 1997-10-27 | 旭化成工業株式会社 | Method for producing thermoplastic copolymer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5591877A (en) * | 1978-12-30 | 1980-07-11 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS56161646A (en) * | 1980-05-19 | 1981-12-12 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1984
- 1984-07-18 JP JP14917984A patent/JPS6127680A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5591877A (en) * | 1978-12-30 | 1980-07-11 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS56161646A (en) * | 1980-05-19 | 1981-12-12 | Fujitsu Ltd | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6127680A (en) | 1986-02-07 |
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| EXPY | Cancellation because of completion of term |