JP3054614B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3054614B2 JP3054614B2 JP10347052A JP34705298A JP3054614B2 JP 3054614 B2 JP3054614 B2 JP 3054614B2 JP 10347052 A JP10347052 A JP 10347052A JP 34705298 A JP34705298 A JP 34705298A JP 3054614 B2 JP3054614 B2 JP 3054614B2
- Authority
- JP
- Japan
- Prior art keywords
- grain size
- crystal grain
- electrode
- semiconductor device
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、多結晶膜からなる
電極を備えた半導体装置に関する。The present invention relates to a semiconductor device provided with an electrode made of a polycrystalline film.
【０００２】[0002]
【従来の技術】例えば半導体メモリに用いられるＭＯＳ
トランジスタにあっては、電極として多結晶膜である多
結晶シリコンが、しばしば用いられる。斯かるＭＯＳト
ランジスタの典型的構造を図３に示し、これを、その製
造過程と共に説明するに、先ず、シリコン基板（１）上
全面に、熱酸化膜及び多結晶シリコン膜を順次堆積した
後、パターニングによりゲート酸化膜（２）及びゲート
電極（３）の重畳体を残す。この後、イオン注入法によ
る不純物拡散を行うと、ゲート電極（３）に不純物が添
加されると共に、ゲート電極（３）がマスクとなって、
ドレイン（４）及びソース（５）が自己整合的に形成さ
れる。2. Description of the Related Art For example, a MOS used in a semiconductor memory
In a transistor, polycrystalline silicon, which is a polycrystalline film, is often used as an electrode. FIG. 3 shows a typical structure of such a MOS transistor, which will be described together with its manufacturing process. First, a thermal oxide film and a polycrystalline silicon film are sequentially deposited on the entire surface of a silicon substrate (1). By patterning, an overlap of the gate oxide film (2) and the gate electrode (3) is left. Thereafter, when impurity diffusion is performed by ion implantation, impurities are added to the gate electrode (3), and the gate electrode (3) serves as a mask,
The drain (4) and the source (5) are formed in a self-aligned manner.
【０００３】上記構造における問題点は、ゲート電極へ
のイオン注入時に、チャネリング効果により注入イオン
がゲート電極（３）下の基板（１）に侵入し、トランジ
スタ特性を低下させる危険性のあるところである。The problem with the above structure is that when implanting ions into the gate electrode, the implanted ions may enter the substrate (1) below the gate electrode (3) due to the channeling effect, thereby deteriorating the transistor characteristics. .
【０００４】そこで、特開昭６３−４８８６５号公報に
記載の如く、ゲート電極を構成する多結晶シリコンの結
晶粒径を小さくすることにより、注入イオンの基板への
侵入を阻止する構成が提案された。斯かる構造は、注入
イオンの阻止において効果を有する反面、ゲート電極の
抵抗率を高くする傾向をもつ。なぜなら、多結晶シリコ
ンの抵抗率は、その結晶粒径が小さくなるに従い大きく
なるからである。Therefore, as described in JP-A-63-48865, a configuration has been proposed in which the crystal grain size of the polycrystalline silicon constituting the gate electrode is reduced to prevent the penetration of implanted ions into the substrate. Was. Such a structure is effective in blocking implanted ions, but tends to increase the resistivity of the gate electrode. This is because the resistivity of polycrystalline silicon increases as the crystal grain size decreases.
【０００５】[0005]
【発明が解決しようとする課題】従って、本発明は、多
結晶膜からなる電極にイオン注入する際に、注入イオン
が基板へ侵入するのを阻止し、かつ前記電極の抵抗率の
増大を抑制し得る構造を提供しようとするものである。SUMMARY OF THE INVENTION Accordingly, the present invention prevents the implanted ions from entering the substrate and suppresses an increase in the resistivity of the electrode when implanting ions into the electrode made of a polycrystalline film. It is intended to provide a structure that can be used.
【０００６】[0006]
【課題を解決するための手段】本発明は、多結晶膜から
なる電極と、当該電極をマスクとしたイオン注入法によ
り自己整合的に形成された不純物拡散領域を備えた半導
体装置において、前記電極が結晶粒径の小さい部分と結
晶粒径の大きい部分とを備え、且つ前記結晶粒径の大き
い部分が、結晶粒径が０．３μｍ以上の部分を有するこ
とを特徴とし、また前記結晶粒径の小さい部分が、結晶
粒径が０．１μｍ以下の部分を有することを特徴とす
る。According to the present invention, there is provided an electrode comprising a polycrystalline film and an ion implantation method using the electrode as a mask.
In a semiconductor device having an impurity diffusion region formed in a self-aligned manner, the electrode includes a portion having a small crystal grain size and a portion having a large crystal grain size, and the portion having a large crystal grain size is formed of a crystal grain. It is characterized in that it has a portion having a diameter of 0.3 μm or more, and the portion having a small crystal grain size has a portion having a crystal grain size of 0.1 μm or less.
【０００７】また、前記結晶粒径の大きい部分が、前記
電極の表面側に設けられていることを特徴とし、前記結
晶粒径の小さい部分が、前記電極の裏面側に設けられて
いることを特徴とする。[0007] Further, the invention is characterized in that the portion having the large crystal grain size is provided on the front surface side of the electrode, and the portion having the small crystal grain size is provided on the back surface side of the electrode. Features.
【０００８】さらには、前記電極が、シリコンの多結晶
膜からなることを特徴とする。Further, the invention is characterized in that the electrode is made of a polycrystalline silicon film.
【０００９】[0009]
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施の形態を図１
を参照して説明する。FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIG.
【００１１】基板となるシリコン半導体層（１０）上
に、熱酸化法により、酸化膜（１１）を３００Å形成す
る。続いてこの上に多結晶シリコン膜（１２）をＳｉＨ
4の熱分解により減圧ＣＶＤ法にて３０００Å堆積させ
る（図１Ａ）。堆積温度は６２０℃から５６０℃まで漸
次下降せしめ、圧力０．５Ｔｏｒｒ、ＳｉＨ4流量１２
０ｃｃ／ｍｉｎとする。堆積温度がおよそ５７５℃を境
にして低温側では堆積されたシリコンはアモルファス状
態であり、高温側では多結晶化している。図１Ａにおい
て、番号（１２ａ）はアモルファス部分を、又番号（１
２ｂ）は多結晶部分をそれぞれ示している。同図に示す
如く、アモルファス部分（１２ａ）及び多結晶部分（１
２ｂ）は、いずれも膜面と平行に層状に形成されてい
る。An oxide film (11) is formed on the silicon semiconductor layer (10) serving as a substrate by thermal oxidation at a thickness of 300 °. Subsequently, a polycrystalline silicon film (12) is
By thermal decomposition of No. 4 , 3,000Å is deposited by a low pressure CVD method (FIG. 1A). The deposition temperature was gradually lowered from 620 ° C. to 560 ° C., pressure 0.5 Torr, SiH 4 flow 12
0 cc / min. The silicon deposited is in an amorphous state on a low temperature side with a deposition temperature of about 575 ° C., and is polycrystalline on a high temperature side. In FIG. 1A, the number (12a) indicates the amorphous portion, and the number (1a).
2b) shows polycrystalline portions, respectively. As shown in the figure, the amorphous portion (12a) and the polycrystalline portion (1
2b) is formed in layers in parallel with the film surface.
【００１２】次いで、６００℃、１０時間のアニールが
行われる。このアニールの結果、図１Ａにおけるアモル
ファス部分（１２ａ）は多結晶化し、同図Ｂに示す如
く、多結晶化部分（１２ｃ）となる。アニール後の結晶
粒径は、前記ＣＶＤ法堆積時の堆積温度に依存したもの
となり、斯かる依存特性が図２に示されている。同図か
ら判る様に、堆積温度が低いほど、結晶粒径が大きくな
る。従って、今の場合、当初アモルファス状態であった
表面側のアモルファス部分（１２ａ）の方が、裏面側
（即ち半導体層１０側）の多結晶部分（１２ｂ）よりも
結晶粒径が大きくなる。この結果、アニール後において
は、結晶粒径の小さい多結晶膜からなる部分（１２ｂ）
と結晶粒径の大きい多結晶膜からなる多結晶化部分（１
２ｃ）とを備えた多結晶シリコン膜（１２）が得られ
る。Next, annealing is performed at 600 ° C. for 10 hours. As a result of this annealing, the amorphous portion (12a) in FIG. 1A is polycrystallized, and becomes a polycrystallized portion (12c) as shown in FIG. The crystal grain size after the annealing depends on the deposition temperature at the time of the CVD method deposition, and such a dependence characteristic is shown in FIG. As can be seen from the figure, the lower the deposition temperature, the larger the crystal grain size. Therefore, in this case, the amorphous part (12a) on the front side, which was initially in an amorphous state, has a larger crystal grain size than the polycrystalline part (12b) on the back side (that is, the semiconductor layer 10 side). As a result, after annealing, the portion (12b) composed of a polycrystalline film having a small crystal grain size is obtained.
And a polycrystallized portion composed of a polycrystal film having a large crystal grain size (1
2c) to obtain a polycrystalline silicon film (12).
【００１３】このとき、上述した通りアモルファス部分
（１２ａ）堆積時の堆積温度が５７５℃〜５６０℃の範
囲であることから、上記多結晶化部分（１２ｃ）は結晶
粒径が０．３μｍ以上の部分を有することとなる。ま
た、多結晶部分（１２ｂ）の堆積温度が５７５℃〜６２
０℃の範囲であることから、アニール後の結晶粒径の小
さい多結晶膜からなる部分（１２ｂ）は、結晶粒径が
０．１μｍ以下の部分を有することとなる。At this time, since the deposition temperature at the time of depositing the amorphous portion (12a) is in the range of 575 ° C. to 560 ° C. as described above, the polycrystalline portion (12c) has a crystal grain size of 0.3 μm or more. Parts. The deposition temperature of the polycrystalline portion (12b) is 575 ° C. to 62 ° C.
Since the temperature is in the range of 0 ° C., the portion (12b) formed of the polycrystalline film having a small crystal grain size after annealing has a portion having a crystal grain size of 0.1 μm or less.
【００１４】そして、膜厚方向において裏面側から表面
側に向けて粒径が順次大となる結晶粒径の分布を有する
ように、結晶粒径の大きい部分（１２ｃ）が表面側に配
され、結晶粒径の小さい部分（１２ｂ）が裏面側に配さ
れた多結晶シリコン膜（１２）が得られる。A portion (12c) having a large crystal grain size is arranged on the front surface side so as to have a crystal grain size distribution in which the grain size increases gradually from the back side to the front side in the thickness direction. A polycrystalline silicon film (12) in which a portion (12b) having a small crystal grain size is disposed on the back surface side is obtained.
【００１５】その後、パターニングによりゲート酸化膜
（１３）及びゲート電極（１４）の重畳体を残す。この
パターニングのためには、多結晶シリコン膜（１２）に
対してはＳＦ6を主体としたガスを、又酸化膜（１１）
に対してはＣＨＦ3を主体としたガスを、夫々用いたＲ
ＩＥ（反応性イオンエッチング）法が採用される。After that, an overlap of the gate oxide film (13) and the gate electrode (14) is left by patterning. For this patterning, a gas mainly composed of SF 6 is applied to the polycrystalline silicon film (12), and an oxide film (11) is used.
For the R, the gas mainly composed of CHF 3 was used.
An IE (Reactive Ion Etching) method is employed.
【００１６】最後に、イオン注入法による不純物拡散を
行うと、ゲート電極（１４）に不純物が添加されると共
に、ゲート電極（１４）がマスクとなってシリコン半導
体（１０）中にドレイン（１５）及びソース（１６）の
不純物拡散領域が自己整合的に形成される。注入イオン
としてはリン等が最適である。Finally, when impurity diffusion is performed by ion implantation, impurities are added to the gate electrode (14), and the drain (15) is formed in the silicon semiconductor (10) by using the gate electrode (14) as a mask. And impurity diffusion regions of the source (16) are formed in a self-aligned manner. Phosphorus or the like is most suitable as the implanted ions.
【００１７】この様にして得られた装置の構造にあって
は、多結晶膜からなるゲート電極（１４）が、結晶粒径
が０．３μｍ以上の部分を有する結晶粒径の大きい部分
を備えているので、ゲート電極の抵抗率は大きくならな
い。In the structure of the device thus obtained, the gate electrode (14) made of a polycrystalline film has a portion having a large crystal grain size having a portion having a crystal grain size of 0.3 μm or more. Therefore, the resistivity of the gate electrode does not increase.
【００１８】加えて本発明にあっては、ゲート電極（１
４）が、結晶粒径が０．１μｍ以下の部分を有する結晶
粒径の小さい部分を備えているために、ゲート電極（１
４）へのイオン注入時に、注入イオンが半導体基板（１
０）内に侵入することが阻止される。In addition, in the present invention, the gate electrode (1
4) has a portion with a small crystal grain size having a portion with a crystal grain size of 0.1 μm or less, so that the gate electrode (1)
When the ions are implanted into the semiconductor substrate (1),
0) is prevented.
【００１９】さらには、上記結晶粒径の大きい部分がゲ
ート電極（１４）の表面側に配され、結晶粒径の小さい
部分が電極（１４）の裏面側に配されることで、その効
果が一層顕著なものとなる。Furthermore, the effect is obtained by arranging the portion having a large crystal grain size on the front surface side of the gate electrode (14) and the portion having a small crystal grain size on the back surface side of the electrode (14). It will be even more pronounced.
【００２０】上記実施例では、ゲート電極（１４）を構
成する多結晶膜の結晶粒径は、ゲート電極（１４）の裏
面側から表面側に向かって漸増するものであったが、段
階的に変化されても良い。その場合、多結晶シリコン膜
（１２）の堆積温度を当初高い値に固定して堆積を行
い、適当な膜厚になった時点で、反応ガス供給を停止す
ると共に堆積温度を下げ、この温度が所定の値に達した
時点で、堆積温度を維持し、かつ反応ガス供給を再開す
ることとなる。In the above embodiment, the crystal grain size of the polycrystalline film constituting the gate electrode (14) gradually increases from the back side to the front side of the gate electrode (14). May be changed. In this case, the deposition is performed with the deposition temperature of the polycrystalline silicon film (12) fixed initially at a high value, and when the film thickness becomes appropriate, the supply of the reaction gas is stopped and the deposition temperature is lowered. When the predetermined value is reached, the deposition temperature is maintained and the supply of the reaction gas is restarted.
【００２１】又、電極材料として、多結晶シリコンの
他、他の結晶材料をも使用し得る。As the electrode material, other crystalline materials can be used in addition to polycrystalline silicon.
【００２２】[0022]
【発明の効果】以上説明した如く、本発明によれば、多
結晶膜からなる電極と、当該電極をマスクとしたイオン
注入法により自己整合的に形成された不純物拡散領域を
備えた半導体装置において前記電極が結晶粒径の小さい
部分と結晶粒径の大きい部分とを備え、且つ前記結晶粒
径の大きい部分が、結晶粒径が０．３μｍ以上の部分を
有している。従って、前記電極へのイオン注入時に、注
入イオンが電極下の半導体層内へ侵入することを阻止す
ることができると共に、電極の抵抗が増大することを抑
制でき、半導体装置の特性が良好なものとなる。As described above, according to the present invention, an electrode made of a polycrystalline film and an ion
In a semiconductor device including an impurity diffusion region formed in a self-aligned manner by an implantation method , the electrode includes a portion having a small crystal grain size and a portion having a large crystal grain size, and the portion having a large crystal grain size is formed of a crystal. It has a portion having a particle size of 0.3 μm or more. Therefore, at the time of ion implantation into the electrode, it is possible to prevent the implanted ions from entering the semiconductor layer below the electrode, to suppress an increase in the resistance of the electrode, and to improve the characteristics of the semiconductor device. Becomes
【図１】本発明に係る半導体装置の製造工程を説明する
ための工程別断面図である。FIG. 1 is a sectional view for explaining a process of manufacturing a semiconductor device according to the present invention.
【図２】堆積温度と結晶粒径との関係を示す曲線図であ
る。FIG. 2 is a curve diagram showing a relationship between a deposition temperature and a crystal grain size.
【図３】従来装置の断面図である。FIG. 3 is a sectional view of a conventional device.
１０…半導体基板、１１…酸化膜、１２…多結晶膜、１
３…ゲート酸化膜、１４…ゲート電極10: semiconductor substrate, 11: oxide film, 12: polycrystalline film, 1
3 ... gate oxide film, 14 ... gate electrode
フロントページの続き (72)発明者 秋月 誠 大阪府守口市京阪本通２丁目５番５号 三洋電機株式会社内 (72)発明者 青江 弘行 大阪府守口市京阪本通２丁目５番５号 三洋電機株式会社内 (56)参考文献 特開 昭53−108767（ＪＰ，Ａ) 特開 昭63−48865（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/28 - 21/288 H01L 21/336 H01L 21/44 - 21/445 H01L 29/40 - 29/51 H01L 29/78 Continued on the front page (72) Inventor Makoto Akizuki 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Hiroyuki Aoe 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo (56) References JP-A-53-108767 (JP, A) JP-A-63-48865 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21 / 28-21/288 H01L 21/336 H01L 21/44-21/445 H01L 29/40-29/51 H01L 29/78
Claims (5)
スクとしたイオン注入法により自己整合的に形成された
不純物拡散領域を備えた半導体装置において、 前記電極が結晶粒径の小さい部分と結晶粒径の大きい部
分とを備え、且つ前記結晶粒径の大きい部分が、結晶粒
径が０．３μｍ以上の部分を有することを特徴とする半
導体装置。1. An electrode comprising a polycrystalline film and said electrode
Self-aligned by ion implantation
In a semiconductor device having an impurity diffusion region , the electrode includes a portion having a small crystal grain size and a portion having a large crystal grain size, and the portion having a large crystal grain size has a portion having a crystal grain size of 0.3 μm or more. A semiconductor device comprising:
が０．１μｍ以下の部分を有することを特徴とする請求
項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the portion having a small crystal grain size has a portion having a crystal grain size of 0.1 μm or less.
の表面側に配されたことを特徴とする請求項１又は２記
載の半導体装置。3. The semiconductor device according to claim 1, wherein the portion having a large crystal grain size is disposed on a surface side of the electrode.
の裏面側に配されたことを特徴とする請求項１乃至３の
いずれかに記載の半導体装置。4. The semiconductor device according to claim 1, wherein the portion having a small crystal grain size is arranged on a back surface side of the electrode.
ることを特徴とする請求項１乃至４のいずれかに記載の
半導体装置。5. The semiconductor device according to claim 1, wherein said electrode is made of a polycrystalline silicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10347052A JP3054614B2 (en) | 1998-12-07 | 1998-12-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10347052A JP3054614B2 (en) | 1998-12-07 | 1998-12-07 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1138612A Division JP2944103B2 (en) | 1989-05-31 | 1989-05-31 | MOS transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11243188A JPH11243188A (en) | 1999-09-07 |
| JP3054614B2 true JP3054614B2 (en) | 2000-06-19 |
Family
ID=18387603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10347052A Expired - Lifetime JP3054614B2 (en) | 1998-12-07 | 1998-12-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3054614B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7232774B2 (en) | 2004-01-20 | 2007-06-19 | International Business Machines Corporation | Polycrystalline silicon layer with nano-grain structure and method of manufacture |
| CN105845575B (en) * | 2015-01-14 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor devices |
-
1998
- 1998-12-07 JP JP10347052A patent/JP3054614B2/en not_active Expired - Lifetime
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| Publication number | Publication date |
|---|---|
| JPH11243188A (en) | 1999-09-07 |
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