JP2944103B2 - MOS transistor - Google Patents
MOS transistorInfo
- Publication number
- JP2944103B2 JP2944103B2 JP1138612A JP13861289A JP2944103B2 JP 2944103 B2 JP2944103 B2 JP 2944103B2 JP 1138612 A JP1138612 A JP 1138612A JP 13861289 A JP13861289 A JP 13861289A JP 2944103 B2 JP2944103 B2 JP 2944103B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- grain size
- crystal grain
- film
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000013078 crystal Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 239000002356 single layer Substances 0.000 claims description 5
- 239000010408 film Substances 0.000 description 18
- 150000002500 ions Chemical class 0.000 description 9
- 239000000758 substrate Substances 0.000 description 9
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】 （イ） 産業上の利用分野 本発明は電極を多結晶膜で形成した半導体装置に関す
る。The present invention relates to a semiconductor device having electrodes formed of a polycrystalline film.
（ロ） 従来の技術 例えば半導体メモリに用いられるMOSトランジスタに
あっては、電極として多結晶シリコンが、しばしば用い
られる。斯るMOSトランジスタの典型的構造を第３図に
示し、これを、その製造過程と共に説明するに、先ず、
シリコン基板（１）上全面に、熱酸化膜及び多結晶シリ
コン膜を順次堆積した後、パターニングによりゲート酸
化膜（２）及びゲート電極（３）の重畳体を残す。この
後、イオン注入法による不純物拡散を行うと、ゲート電
極（３）に不純物が添加されると共に、ゲート電極
（３）がマスクとなって、ドレイン（４）及びソース
（５）が自己整合的に形成される。(B) Conventional technology For example, in a MOS transistor used for a semiconductor memory, polycrystalline silicon is often used as an electrode. A typical structure of such a MOS transistor is shown in FIG. 3 and is described together with its manufacturing process.
After a thermal oxide film and a polycrystalline silicon film are sequentially deposited on the entire surface of the silicon substrate (1), an overlapped body of the gate oxide film (2) and the gate electrode (3) is left by patterning. Thereafter, when impurity diffusion is performed by an ion implantation method, an impurity is added to the gate electrode (3) and the drain (4) and the source (5) are self-aligned using the gate electrode (3) as a mask. Formed.
上記構造における問題点は、ゲート電極へのイオン注
入時に、チャネリング効果により注入イオンがゲート電
極（３）下の基板（１）に侵入し、トランジスタ特性を
低下させる危険性のあることである。The problem with the above structure is that at the time of ion implantation into the gate electrode, the implanted ions may enter the substrate (1) below the gate electrode (3) due to the channeling effect, thereby deteriorating the transistor characteristics.
そこで、特開昭63−48865号公報に記載の如く、ゲー
ト電極を構成する多結晶シリコンの結晶粒径を小さくす
ることにより、注入イオンの基板への侵入を阻止する構
成が提案された。斯る構造は、注入イオンの阻止におい
て効果を有する反面、ゲート電極の抵抗率を高くする傾
向をもつ。なぜなら、多結晶シリコンの抵抗率は、その
結晶粒径が小さくなるに従い大きくなるからである。Therefore, as described in Japanese Patent Application Laid-Open No. 63-48865, a configuration has been proposed in which the implanted ions are prevented from entering the substrate by reducing the crystal grain size of the polycrystalline silicon constituting the gate electrode. Such a structure is effective in blocking implanted ions, but tends to increase the resistivity of the gate electrode. This is because the resistivity of polycrystalline silicon increases as the crystal grain size decreases.
（ハ） 発明が解決しようとする課題 従って、本発明は、MOSトランジスタにおいて、シリ
コンの多結晶膜からなるゲート電極にイオン注入する際
に、注入イオンが基板へ侵入するのを阻止し、かつ前記
電極の抵抗率の増大を抑制し得る構造を提供しようとす
るものである。(C) Problems to be Solved by the Invention Accordingly, the present invention provides a MOS transistor which, when implanting ions into a gate electrode made of a polycrystalline silicon film, prevents implanted ions from entering a substrate, An object of the present invention is to provide a structure capable of suppressing an increase in the resistivity of an electrode.
（ニ） 課題を解決するための手段 本発明は、シリコンの多結晶膜からなるゲート電極を
備えたMOSトランジスタにおいて、前記多結晶膜は、結
晶粒径が、前記ゲート電極の裏面側において小さく、表
面側において大きい単層膜であることを特徴とする。(D) Means for Solving the Problems The present invention relates to a MOS transistor having a gate electrode made of a polycrystalline silicon film, wherein the polycrystalline film has a small crystal grain size on the back side of the gate electrode, It is characterized in that it is a large single-layer film on the surface side.
（ホ） 作用 本発明にあっては、その電極の裏面側における結晶粒
径の小さい部分が注入イオンの基板への侵入を阻止し、
一方、電極の表面側における結晶粒径の大きい部分が電
極の抵抗率を小さい値にする。(E) Function In the present invention, the portion having a small crystal grain size on the back surface side of the electrode prevents the implanted ions from entering the substrate,
On the other hand, a portion where the crystal grain size is large on the surface side of the electrode makes the resistivity of the electrode small.
（ヘ） 実施例 以下、本発明の一実施例を第１図を参照して説明す
る。(F) Embodiment One embodiment of the present invention will be described below with reference to FIG.
シリコン基板（10）に、熱酸化法により、酸化膜（1
1）を300Å形成する。続いてこの上に単層の多結晶シリ
コン膜（12）をSiH4の熱分解により減圧CVD法にて3000
Å堆積させる（第１図Ａ）。堆積温度は620℃から560℃
まで漸次下降せしめ、圧力0.5Torr、SiH4流量120cc/min
とする。堆積温度がおよそ575℃を境にして低温側では
堆積されたシリコンはアモルファス状態であり、高温側
では多結晶化している。第１図Ａにおいて、番号（12
a）はアモルファス部分を又、番号（12b）は多結晶部分
を夫々示している。An oxide film (1) is formed on a silicon substrate (10) by thermal oxidation.
1) Form 300mm. Subsequently, a single-layer polycrystalline silicon film (12) was deposited on the thin film by thermal decomposition of SiH 4 to form a polycrystalline silicon film (12).
Å Deposit (Fig. 1A). Deposition temperature from 620 ° C to 560 ° C
Gradually lower to 0.5 Torr, SiH 4 flow rate 120cc / min
And The silicon deposited is in an amorphous state on a low temperature side with a deposition temperature of about 575 ° C., and is polycrystalline on a high temperature side. In FIG. 1A, the number (12
a) indicates an amorphous portion, and number (12b) indicates a polycrystalline portion.
次いで、600℃、10時間のアニールが行われる。この
アニールの結果、第１図Ａにおけるアモルファス部分
（12a）は多結晶化し、第１図Ｂに示す如く、多結晶化
部分（12c）となる。アニール後の結晶粒径は、当初ア
モルファス状態であるか多結晶状態であるかに拘らず、
前記CVD法堆積時の堆積温度に依存したものとなり、斯
る依存特性が第２図に示されている。同図から判る様
に、堆積温度が低いほど、結晶粒径は大きくなる。従っ
て、今の場合、多結晶シリコン膜（12）の裏面側（即ち
基板側）から表面側に向けて、膜（12）を構成する結晶
粒径が順次大となる。Next, annealing is performed at 600 ° C. for 10 hours. As a result of this annealing, the amorphous portion (12a) in FIG. 1A is polycrystallized and becomes a polycrystallized portion (12c) as shown in FIG. 1B. The crystal grain size after annealing, regardless of whether it is initially amorphous or polycrystalline,
It depends on the deposition temperature at the time of the CVD method deposition, and such dependence characteristics are shown in FIG. As can be seen from the figure, the lower the deposition temperature, the larger the crystal grain size. Therefore, in this case, the crystal grain size of the polycrystalline silicon film (12) gradually increases from the back side (that is, the substrate side) to the front side.
その後、パターニングによりゲート酸化膜（13）及び
ゲート電極（14）の重畳体を残す このパターニングの
ためには、多結晶シリコン膜（12）に対してはSF6を主
体としたガスを、又酸化膜（11）に対してはCHF3を主体
としたガスを、夫々用いたRIE（反応性イオンエッチン
グ）法が採用される。Then, for this patterning to leave the superposition of gate oxide film (13) and the gate electrode (14) by patterning, the gas mainly composed of SF 6 for the polycrystalline silicon film (12), and oxidation For the film (11), a RIE (Reactive Ion Etching) method using each gas mainly composed of CHF 3 is adopted.
最後に、イオン注入法による不純物拡散を行うと、ゲ
ート電極（14）に不純物が添加されると共に、ゲート電
極（14）がマスクとなって、ドレイン（15）及びソース
（16）が自己整合的に形成される。注入イオンとしては
リン等が好適である。Finally, when impurity diffusion is performed by ion implantation, impurities are added to the gate electrode (14), and the drain (15) and the source (16) are self-aligned using the gate electrode (14) as a mask. Formed. Phosphorus or the like is preferable as the implanted ions.
この様にして得られた装置の構造にあっては、多結晶
シリコンの単層膜からなるゲート電極（14）の表面側に
結晶粒径の大きい部分が存在するためゲート電極の抵抗
率は大きくならず、又、ゲート電極（14）の裏面側には
結晶粒径の小さい部分が存在するため、ゲート電極（1
4）へのイオン注入時に、注入イオンが基板（10）内に
侵入することが阻止される。In the structure of the device thus obtained, the resistivity of the gate electrode is large because a portion having a large crystal grain size exists on the surface side of the gate electrode (14) made of a single-layer film of polycrystalline silicon. In addition, since a portion having a small crystal grain size exists on the back surface side of the gate electrode (14), the gate electrode (1
At the time of ion implantation to 4), the implanted ions are prevented from entering the substrate (10).
以上のように、本実施例では、多結晶シリコンの単層
膜からなるゲート電極（14）を構成する結晶粒径が、ゲ
ート電極（14）の裏面側から表面側に向かって漸増する
ものである。As described above, in the present embodiment, the crystal grain size of the gate electrode (14) formed of a single-layer film of polycrystalline silicon gradually increases from the back side to the front side of the gate electrode (14). is there.
（ト） 発明の効果 本発明の構造によれば、シリコンの多結晶膜からなる
ゲート電極の抵抗率を大きくすることなく、イオン注入
時の注入イオンがゲート電極下の基板に侵入することを
防止でき、従ってMOSトランジスタの特性が良好なもの
となる。(G) Effects of the Invention According to the structure of the present invention, it is possible to prevent implanted ions at the time of ion implantation from entering the substrate below the gate electrode without increasing the resistivity of the gate electrode made of a polycrystalline silicon film. Therefore, the characteristics of the MOS transistor are improved.
第１図Ａ、Ｂ、Ｃは、本発明実施例装置を製造するため
の工程別断面図、第２図は堆積温度と結晶粒径との関係
を示す曲線図、第３図は従来装置を示す断面図である。1A, 1B, and 1C are cross-sectional views for each process for manufacturing an apparatus according to the present invention, FIG. 2 is a curve diagram showing the relationship between deposition temperature and crystal grain size, and FIG. FIG.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 秋月 誠 大阪府守口市京阪本通２丁目18番地 三 洋電機株式会社内 (72)発明者 青江 弘行 大阪府守口市京阪本通２丁目18番地 三 洋電機株式会社内 (56)参考文献 特開 昭53−10867（ＪＰ，Ａ) 特開 平１−231373（ＪＰ，Ａ) 特開 平２−298074（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/28 - 21/288 H01L 21/336 H01L 21/44 - 21/445 H01L 29/40 - 29/51 H01L 29/78 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Makoto Akizuki 2-18-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Hiroyuki Aoe 2-18-3 Keihanhondori, Moriguchi-shi, Osaka (56) References JP-A-53-10867 (JP, A) JP-A-1-231373 (JP, A) JP-A-2-298074 (JP, A) (58) Fields investigated ( Int.Cl. 6 , DB name) H01L 21/28-21/288 H01L 21/336 H01L 21/44-21/445 H01L 29/40-29/51 H01L 29/78
Claims (1)
備えたMOSトランジスタにおいて、前記多結晶膜は、結
晶粒径が、前記ゲート電極の裏面側において小さく、表
面側において大きい単層膜であることを特徴とするMOS
トランジスタ。1. A MOS transistor having a gate electrode made of a polycrystalline silicon film, wherein the polycrystalline film is a single-layer film having a small crystal grain size on the back surface side of the gate electrode and a large crystal grain size on the front surface side. MOS characterized by the following
Transistor.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1138612A JP2944103B2 (en) | 1989-05-31 | 1989-05-31 | MOS transistor |
| JP34705098A JPH11238871A (en) | 1989-05-31 | 1998-12-07 | Semiconductor device |
| JP34705198A JPH11238872A (en) | 1989-05-31 | 1998-12-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1138612A JP2944103B2 (en) | 1989-05-31 | 1989-05-31 | MOS transistor |
Related Child Applications (5)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17294898A Division JP2951319B2 (en) | 1998-06-19 | 1998-06-19 | Method for manufacturing semiconductor device |
| JP10172947A Division JP2983963B2 (en) | 1998-06-19 | 1998-06-19 | Semiconductor device |
| JP10347052A Division JP3054614B2 (en) | 1998-12-07 | 1998-12-07 | Semiconductor device |
| JP34705098A Division JPH11238871A (en) | 1989-05-31 | 1998-12-07 | Semiconductor device |
| JP34705198A Division JPH11238872A (en) | 1989-05-31 | 1998-12-07 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH033365A JPH033365A (en) | 1991-01-09 |
| JP2944103B2 true JP2944103B2 (en) | 1999-08-30 |
Family
ID=15226153
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1138612A Expired - Lifetime JP2944103B2 (en) | 1989-05-31 | 1989-05-31 | MOS transistor |
| JP34705198A Pending JPH11238872A (en) | 1989-05-31 | 1998-12-07 | Semiconductor device |
| JP34705098A Pending JPH11238871A (en) | 1989-05-31 | 1998-12-07 | Semiconductor device |
Family Applications After (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34705198A Pending JPH11238872A (en) | 1989-05-31 | 1998-12-07 | Semiconductor device |
| JP34705098A Pending JPH11238871A (en) | 1989-05-31 | 1998-12-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (3) | JP2944103B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0543268A3 (en) * | 1991-11-19 | 1993-08-11 | Texas Instruments Incorporated | Transistor device with a gate structure and method of forming the same |
| JPH11150195A (en) | 1997-11-19 | 1999-06-02 | Nec Corp | Semiconductor device and manufacture thereof |
| JP2000031475A (en) | 1998-07-10 | 2000-01-28 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| KR100308133B1 (en) * | 1999-01-12 | 2001-09-26 | 김영환 | Method for fablicating a MOS transistor having dual gate |
| KR100571424B1 (en) | 2004-12-30 | 2006-04-14 | 동부아남반도체 주식회사 | Method for forming stable transistor by double step source/drain implantion |
-
1989
- 1989-05-31 JP JP1138612A patent/JP2944103B2/en not_active Expired - Lifetime
-
1998
- 1998-12-07 JP JP34705198A patent/JPH11238872A/en active Pending
- 1998-12-07 JP JP34705098A patent/JPH11238871A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11238871A (en) | 1999-08-31 |
| JPH11238872A (en) | 1999-08-31 |
| JPH033365A (en) | 1991-01-09 |
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