JPS59138382A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase the withstand voltage of the second gate oxide film by a method wherein the first insulation film is adhered on the surface of the element region of a semiconductor substrate of one conductivity type, and a non-single crystal Si film serving as a floating gate is deposited thereon, thereafter, before forming the second insulation film there, the non-single crystal Si film is kept irradiated with a laser beam, etc. CONSTITUTION:A thick field oxide film 22 is formed in the periphery of a P<-> type Si substrate 21, a thin oxide film 23 is adhered on the surface of the substrate 21 surrounded by said film, and the first polycrystalline Si film 24 for the floating gate having a fixed seat resistance value is deposited over the entire surface including said film. Next, the entire surface is covered with a thick oxide film 25, the film 24 is irradiated with an Ar laser through said film, thereafter the film 25 is removed, and then an oxide film 26 and the second polycrystalline film 27 are laminated and adhered on the film 24. Afterwards, the mask of a photo resist 28 is provided at the center on the film 27, the lamination fim around said mask is all removed by etching, thus leaving only an oxide film 29, the floating gate 30, the second gate oxide film 31, and a control gate 32.

Description

[Detailed description of the invention] [Technical field of invention] TECHNICAL FIELD The present invention relates to a method for manufacturing a hemiconductor memory device.

[Technical background of the invention and its problems]

Conventionally, EPRO Ivi (Electric
ally programmable read onl
y memory ) is manufactured as follows.

First, a first thermal oxide film is formed on the surface of an island-shaped element region surrounded by a field oxide film (not shown) of a P-type silicon substrate 1, and then a first polycrystalline silicon film is formed as a floating r-) on the entire surface. Deposit the film. Next, for example, 1000℃
After a second thermal oxide film is formed on the surface of the first polycrystalline silicon film by performing the following low-temperature oxidation, a second polycrystalline silicon film that will become a control gate is deposited on the entire surface. Next, a second polycrystalline silicon film and a second polycrystalline silicon film are formed by photolithography.
The thermal oxide film, the first polycrystalline silicon film, and the first thermal oxide film are sequentially etched to form the first dirt oxide film 2, floating chip 9-3, second dirt oxide film 4, and control dirt 5. Form. Next, using these as a mask, N-type impurity, for example, Asf ions are implanted. Subsequently, thermal conversion is performed to form a post-oxide film 6 on the surface of the control dirt 5, the side surface of the floating gate 3, and the exposed surface of the substrate 1, and activate the As ion implantation layer to form the N++ source and drain. A region 7°8 is formed. After depositing, for example, a PSG film 9t on the entire surface as a passivation film,
Contact holes 10 and 10'f are formed by selectively etching a part of the G film 9 and the thermal oxide film 6, and an At-8t film is further deposited on the entire surface, followed by patterning to form the source electrode 1. and drain electrode 12 are formed to form an EPROM.
Manufacture cells.

The above-mentioned FPROM is a device that performs writing by applying a high positive voltage to the N+ type drain region 8 and control gate 5 of the cell transistor to inject electrons into the floating gate 3.

However, if a high positive voltage is applied to the control gate 5 after writing, there is a drawback that the electrons injected into the floating gate 3 escape to the control gate 5, and the memory may not be maintained.

This is due to the breakdown voltage deterioration of the second gates #g and 4 due to aging, and the cause is considered to be as follows.

In other words, since the first polycrystalline silicon film that becomes the floating dirt is composed of duplexes with various plane orientations, the second polycrystalline silicon film, which becomes the floating dirt, is difficult to see through the low-temperature observation hole below 1000°C.
When the second thermal oxide film is formed as an oxide film, surface asperity is generated at the interface between the floating gate 3 and the second dirt Iff film 4, leading to pressure deterioration of the second dirt oxide film 4. .

This phenomenon can be alleviated by still temperature processing at 1100°C or higher, but high temperature processes change the position of pre-formed bonds and cause warping of the wafer.
This is not an effective countermeasure because it will completely degrade the performance of the de-guiss and reduce the yield.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and
The present invention aims to provide a method that can improve the breakdown voltage of the second dirt-barrel film without reducing the yield of semiconductor devices, and can fully assemble semiconductor memory devices with good memory retention characteristics.

[Summary of the invention]

The method for manufacturing a semiconductor memory device of the present invention includes forming a first insulating film on the surface of an element region of a semiconductor substrate of a first conductivity type, and depositing a sample of first non-single crystal silicon serving as a 70-chip gate on the entire surface. After the deposition, before forming a second insulating film (thermal oxide film) on the surface of the first non-single crystal silicon film, irradiating the first non-single crystal silicon film with a laser beam or an electron beam. The main points are as follows.

When the first non-single-crystal silicon film is irradiated with the beam in this manner, the dale size of the non-single-crystal silicon can be extremely increased, and furthermore, depending on the beam irradiation conditions, the non-single-crystal silicon can be made into a single crystal. As a result, even if the second insulating film (thermal oxide film) is formed on the surface region of the first non-alcoptic silicon film by low-temperature annealing, the second insulating film (thermal oxide film) and the first The surface asperity at the interface with the non-single-crystal silicon film can be reduced by 1, and the second loquat can significantly increase the withstand voltage of the film (thermal oxidation: 1).

An example will be described with reference to FIGS. 2 0-(g).

, specific resistance IO ~ 2oΩ-m1 plane orientation (911: P
A filled silica film 22 with a thickness of 1.2 μm was formed on the long surface of the - type silicon/substrate 2) using a conventional selective oxidation technique (
FIG. 2(a) diagram).

Next, thermal oxidation was performed to form a first thermal oxidation i1Q 2 :t having a thickness of 500× on the surface of the island-shaped element region surrounded by the field-forming film 22. Next, by CVD method, the thickness is 3500, which becomes floating darts on the entire surface.
The first multiplicity of X1. After depositing the crystalline silicon film 24, p
oct, exposed to an atmosphere at 1000°C for 10 minutes, and the sheet resistance was set to 1 direct rho = 20Ω/mouth (as shown in the same figure (b))
.

Next, a CVD film 25 with a thickness of 1.0 μm was applied to the entire surface.
After depositing, a CW (continuous wave)-Ar laser beam with a beam diameter of 50 μmφ was applied to the mother wharf to IOW.

Irradiation was performed at a scan speed of 101 M/see.

If the first polycrystalline silicon film 24 is directly scanned with a laser beam, there is a possibility that the surface will be uneven.
The CVD oxide film 26 has the role of preventing the occurrence of unevenness 10 by applying pressure to the first polycrystalline silicon layer 24 (as shown in FIG. 1C).

Next, after removing the CVD oxide film 25,
A second thermally oxidized INK 26f6 with a thickness of 500^ is thermally oxidized at 0°C.
A second polycrystalline silicon layer 27 was deposited to serve as a control gate with 0X, ρ, = 20Ω/gate. Continuing,
A photorenograph 1 and a pattern 28 were partially formed on this second polycrystalline silicon film 27 (as shown in FIG. 1 (d''1)).

Using this photorenost turf 28 as a mask, the second polycrystalline silicon film 27 is heated to a second temperature.
g 2 e, the first polycrystalline silicon group 25 and the first heat 11 and the first silicon group 24 are sequentially and mother-turned to form the first goo)
A 1+Z film 29, a floating gate 3θ, a second dirt Y film 31, and a control gate 32 were formed. Next, As” has an energy of 60 keV,
Ion implantation was performed at a dose i of 2.5×10 cm (as shown in the figure).

Next, after removing the Photorenost-ZoTurf 28, thermal oxidation was carried out at 1000° C. to form a post-oxide film 33 having a thickness of 500×. At this time, the Ag ion-implanted layer was activated to form N+ type source and drain regions 34.35 with ρ=30-4°Ω/gate and xj=0.4 μm.

Next, the thickness of the nonossipation film is 0.8μ?
A PSG film 36 of n was deposited (as shown in FIG. 3(f)).

Next, the PSG I pattern 36 and a part of the post-oxide film 33 are selectively etched to form a contact hole 537.
．． 37f: Holes are opened, and the entire surface is covered with At with a thickness of 1-011 m.
- After depositing the exchange material, it is patterned to form the source.
Edge 38.1: The rain electrode 39 was formed and an EPROM cell was manufactured (as shown in Figure 3(g)).According to the method of the present invention, the first After irradiating the polycrystalline silicon v24 with a laser beam to increase the particle size of the polycrystalline silicon, the surface of the first polycrystalline silicon film 24 is converted into a second thermal oxide film 26 by 1000 Even at low temperature oxidation of ℃, the second thermal oxide film 26
and the first polycrystalline silicon reflector 24 (
5surface ll5perity) f can be reduced. As a result, the EPRO shown in FIG. 2(g)
Even if a high positive voltage is applied to the control gate 32 of M, the withstand voltage of the second dirt oxide film 3 can be increased, and memory can be maintained well. Since the map ζ and low-temperature growth are employed, there is no problem that the yield of half-quad memory devices is lowered due to the occurrence of wafer curling, etc.

Incidentally, in the above practical pr# example, the first polycrystalline silicon film 24 was modified by a laser beam in the step shown in FIG.
Even if irradiation is performed under the conditions of φ, 0.5 to l tnk, 20 keys, and scan speed of 10 m/see, similar young fruits can be chewed.

In addition, in the above-mentioned projection example, after the first polycrystalline silicon film 24f is deposited on the entire surface in the step shown in FIG.
C) Depositing a CVD p-oxide film 25 on the entire surface in the illustrated step,
After irradiation with a laser beam, the first polycrystalline silicon layer was deposited and then Zeturned to form a polycrystalline silicon film pattern with a larger area than the floating gate to be formed and a dirt electrode of the peripheral transistor. , a CVDr112 film was deposited on the entire surface, and beam irradiation was performed.
It is also possible to modify the R-turn of the polycrystalline silicon film which becomes the 0-electrode gate and the gate electrode of the peripheral transistor.

Furthermore, not only polycrystalline silicon but also amorphous silicon may be used.

〔Effect of the invention〕

As described in detail above, according to the present invention, the OiIII of the second gate oxide film can be
The present invention can provide a method for manufacturing a semiconductor memory device with improved memory retention characteristics.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional EFROM cell, Figure 2 (-)
-(g) are cross-sectional views showing a method of manufacturing an EFROM cell in an example of the present invention. 21... PW silicon substrate, 22... Field oxide film, 23... First thermal oxide film, 24... First polycrystalline silicon film, 25... CVD oxide film, 26...
・Second thermal oxidation 1 film, 27... Second polycrystalline silicon film, 28... Photorenost pattern, 29... First
Kate conversion Jl'A, so... Floating dart, 31... 2nd r-toe conversion film, :t, 2.
... Control case, 33 ... Post-oxidation film, 34
．． 35...N+ type source and drain region, 36...
PSG film, 37... Contact hole, 38... Source electrode, -'79... Drain conductivity. 1iiFi person patent attorney name Takehiko E
1 Figure 2 R

Claims (4)

[Claims] (1) After forming a first insulating film on the surface of an element region of a 12th #-type semiconductor substrate, a step of depositing a first non-single crystal silicon film on the entire surface; a step of irradiating a silicon film with a beam; a step of forming a second insulating film on the surface of the first non-single crystal silicon film; and a step of forming a second non-single crystal silicon film on the entire surface; A process of sequentially patterning a non-single crystalline silicon film, a second insulating film, a first non-single crystalline silicon film, and a first insulating film, and using these patterns as a mask, ion-implanting a second dielectric type impurity. 1. A method of manufacturing a semiconducting memory device, comprising the step of forming source and drain regions of a second diagonal voltage type. ′ (2) As a pattern of the first non-single crystal silicon film, the pattern of the second non-single crystal silicon film is
Take control of your turn! I:f
2. The method for manufacturing a semiconductor memory device according to item 1. (3) The method of manufacturing a semiconductor memory device according to claim 1, wherein the beam irradiated to the first non-single crystal silicon film is a Rayleigh' beam. (4) The method for manufacturing a semiconductor memory device according to claim 1, wherein the beam irradiated to the first non-single crystal silicon film is an electron beam.