JPH0467336B2 - - Google Patents
Info
- Publication number
- JPH0467336B2 JPH0467336B2 JP55084885A JP8488580A JPH0467336B2 JP H0467336 B2 JPH0467336 B2 JP H0467336B2 JP 55084885 A JP55084885 A JP 55084885A JP 8488580 A JP8488580 A JP 8488580A JP H0467336 B2 JPH0467336 B2 JP H0467336B2
- Authority
- JP
- Japan
- Prior art keywords
- crystal semiconductor
- single crystal
- semiconductor layer
- insulating film
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 26
- 239000013078 crystal Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000002425 crystallisation Methods 0.000 claims description 3
- 230000008025 crystallization Effects 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
- H01L29/78657—SOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Recrystallisation Techniques (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、多結晶シリコン或いは非晶質シリコ
ンをレーザ線或いは粒子線でアニールして単結晶
シリコンとなし、そこに素子を形成する構成の半
導体装置を製造する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device in which polycrystalline silicon or amorphous silicon is annealed with a laser beam or a particle beam to form single crystal silicon, and elements are formed therein. .
近年、絶縁物の上に形成された多結晶シリコン
或いは非晶質シリコンをレーザ線或いは粒子線で
アニールすることに依り単結晶化し、そこに素子
を形成してSOS（Silicon On Sapphire）形式の
半導体装置と類似の半導体装置を製造することが
できるようになつた。 In recent years, polycrystalline silicon or amorphous silicon formed on an insulator is made into a single crystal by annealing it with laser beams or particle beams, and elements are formed thereon to form SOS (Silicon On Sapphire) type semiconductors. It has become possible to manufacture semiconductor devices similar to the device.
しかしながら、レーザ線等で多結晶シリコン等
を広範囲に単結晶化することは容易ではない。従
つて、現段階では、その技術に対応した新しい構
造の半導体装置を製造する方法が考えられなけれ
ばならない。 However, it is not easy to convert polycrystalline silicon into a single crystal over a wide area using a laser beam or the like. Therefore, at this stage, a method for manufacturing a semiconductor device with a new structure compatible with this technology must be considered.
本発明は、多結晶シリコン或いは非晶質シリコ
ンにレーザ・ビーム等を照射し、広範囲に亘つて
容易に単結晶化できる構造の半導体装置を製造す
る方法を提供するものであり、以下これを詳細に
説明する。 The present invention provides a method for manufacturing a semiconductor device having a structure that can be easily made into a single crystal over a wide range by irradiating polycrystalline silicon or amorphous silicon with a laser beam, etc. This will be described in detail below. Explain.
第１図乃至第３図は本発明一実施例を説明する
為の工程要所における半導体装置の要部側断面説
明図であり、次に、これ等の図を参照しつつ記述
する。 1 to 3 are side cross-sectional views of main parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention.Next, the description will be made with reference to these figures.
第１図参照
(1) n+型シリコン半導体基板１に例えば窒化シ
リコン膜をマスクとする選択的熱酸化法を適用
して二酸化シリコン膜２を形成する。この二酸
化シリコン膜２は通常の半導体装置とは逆に活
性領域の大部分が位置すべき部分に在る。従つ
て、基板１の表面が露出している部分は殆んど
フイールド領域となる。Refer to FIG. 1 (1) A silicon dioxide film 2 is formed on an n + type silicon semiconductor substrate 1 by applying a selective thermal oxidation method using, for example, a silicon nitride film as a mask. This silicon dioxide film 2 is present in a portion where most of the active region should be located, contrary to a normal semiconductor device. Therefore, most of the exposed surface of the substrate 1 becomes a field region.
第２図参照
(2) 化学気相成長法を適用し、多結晶シリコン膜
３を厚さ例えば0.4〔μm〕程度に形成する。Refer to FIG. 2 (2) Applying the chemical vapor deposition method, the polycrystalline silicon film 3 is formed to a thickness of, for example, about 0.4 [μm].
(3) レーザ・ビームを照射して、多結晶シリコン
膜３の溶融及び再結晶化を行ない、ｐ型単結晶
シリコン層に変換する。この単結晶化は、二酸
化シリコン膜２の開口に露出されている単結晶
シリコン半導体基板１の表面一部を核として行
なわれるので安定且つ確実に行なわれる。(3) Laser beam irradiation melts and recrystallizes the polycrystalline silicon film 3, converting it into a p-type single crystal silicon layer. This single crystallization is performed stably and reliably because the part of the surface of the single crystal silicon semiconductor substrate 1 exposed through the opening of the silicon dioxide film 2 is used as a core.
(4) 例えば窒化シリコン膜をマスクとする選択的
熱酸化法を適用し、フイールド酸化膜４を形成
する。このフイールド酸化膜４はそのエツジが
二酸化シリコン膜２のエツジと衝合している。(4) For example, by applying a selective thermal oxidation method using a silicon nitride film as a mask, a field oxide film 4 is formed. The edges of this field oxide film 4 abut against the edges of the silicon dioxide film 2.
(5) 例えばイオン注入法にて硼素イオンの導入を
行なう。(5) For example, boron ions are introduced by ion implantation.
第３図参照
(6) 熱酸化法を適用して薄い酸化膜を形成し、そ
の上に、化学気相成長法を適用して多結晶シリ
コン膜を形成する。See Figure 3 (6) A thin oxide film is formed by thermal oxidation, and a polycrystalline silicon film is formed thereon by chemical vapor deposition.
(7) フオト・リソグラフイ技術にて前記多結晶シ
リコン膜及び薄い酸化膜のパターニングを行な
い、シリコン・ゲート電極６及びゲート酸化膜
５とする。(7) The polycrystalline silicon film and thin oxide film are patterned using photolithography technology to form a silicon gate electrode 6 and a gate oxide film 5.
(8) イオン注入法を適用して例えば燐イオンの注
入を行ない、n+型ドレイン領域７及びn+型ソ
ース領域８を形成する。ソース領域８は共通に
基板１とコンタクトしている。(8) For example, phosphorus ions are implanted using an ion implantation method to form an n + type drain region 7 and an n + type source region 8. Source region 8 is in common contact with substrate 1 .
(9) この後、通常の技法にて、絶縁膜の形成、電
極コンタクト窓の形成、電極の形成などを行な
つて完成させる。(9) Thereafter, the insulating film, electrode contact windows, and electrodes are formed using conventional techniques to complete the process.
以上の説明で判るように、本発明に依れば、単
結晶半導体基板の表面に選択的に酸化膜が形成さ
れ、その間から基板の一部が露出された構造を形
成できるようにしている。従つて、その上に多結
晶シリコン層或いは非晶質シリコン層を形成し、
前記酸化膜の間に露出されている単結晶半導体基
板の一部表面を核としてレーザ・アニール或いは
粒子線アニールを行なつて前記多結晶シリコン層
などの単結晶化をすることができる。核となる単
結晶半導体基板はフイールドとなる部分を露出さ
せて利用するものであるから、半導体ウエハに多
数存在した状態に在り、通常レーザ・アニール或
いは粒子線アニールによつて一つの核から単結晶
化される領域が１〜２素子分の領域になつてしま
うにもかかわらずそのアニール範囲は核から然程
離れることはないので良好な単結晶化が行なわれ
るものである。そして、完成された装置は、素子
領域下方が酸化膜で覆われた構造になつている
為、SOS形式の半導体装置と同様の機能を有する
ものであり、また、基板側から素子領域に電圧・
電流を供給することが可能である。 As can be seen from the above description, according to the present invention, an oxide film is selectively formed on the surface of a single crystal semiconductor substrate, and a structure in which a part of the substrate is exposed through the oxide film can be formed. Therefore, a polycrystalline silicon layer or an amorphous silicon layer is formed thereon,
Laser annealing or particle beam annealing can be performed using a part of the surface of the single crystal semiconductor substrate exposed between the oxide films as a core to form a single crystal of the polycrystalline silicon layer or the like. Since the single-crystal semiconductor substrate serving as the nucleus is used by exposing the part that will become the field, a large number of them exist on the semiconductor wafer, and usually a single crystal is formed from one nucleus by laser annealing or particle beam annealing. Even though the area to be annealed is equivalent to one or two elements, the annealing range is not far away from the nucleus, so that good single crystallization can be achieved. The completed device has a structure in which the lower part of the element region is covered with an oxide film, so it has the same function as an SOS type semiconductor device.
It is possible to supply current.
第１図乃至第３図は本発明一実施例の工程を説
明する為の工程要所に半導体装置の要部側断面説
明図である。
図に於いて、１は基板、２は二酸化シリコン
膜、３は多結晶シリコン層、４は酸化膜、５はゲ
ート酸化膜、６はゲート電極、７はドレイン領
域、８はソース領域である。
FIGS. 1 to 3 are side cross-sectional views of essential parts of a semiconductor device at key process points for explaining the steps of an embodiment of the present invention. In the figure, 1 is a substrate, 2 is a silicon dioxide film, 3 is a polycrystalline silicon layer, 4 is an oxide film, 5 is a gate oxide film, 6 is a gate electrode, 7 is a drain region, and 8 is a source region.
Claims (1)
点在して絶縁膜を形成する工程と、 次いで、前記絶縁膜表面を含む全面に非単結晶
半導体層を形成する工程と、 次いで、前記非単結晶半導体層にビームを照射
して前記一導電型単結晶半導体基板を核とする単
結晶化を行つて前記非単結晶半導体層を単結晶半
導体層に変換する工程と、 次いで、前記単結晶半導体層に選択的熱酸化法
を適用して前記絶縁膜の周辺に接すると共に所要
の活性領域を定めるフイールド酸化膜を形成する
工程と、 次いで、前記絶縁膜上に在る前記単結晶半導体
層の部分にゲート絶縁膜を介するゲート電極を形
成する工程と、 次いで、前記絶縁膜上にあつて且つ前記フイー
ルド酸化膜で画定されている前記単結晶半導体層
の部分に一導電型ドレイン領域を、そして、一部
が前記絶縁膜上にあつて且つ他部は前記一導電型
単結晶半導体基板と一体化している前記単結晶半
導体層の部分に共通の一導電型ソース領域をそれ
ぞれ形成する工程と が含まれてなることを特徴とする半導体装置の製
造方法。[Claims] 1. A step of forming an insulating film selectively scattered on the surface of a single-crystal semiconductor substrate of one conductivity type, and then forming a non-single-crystal semiconductor layer over the entire surface including the surface of the insulating film. and then converting the non-single crystal semiconductor layer into a single crystal semiconductor layer by irradiating the non-single crystal semiconductor layer with a beam to perform single crystallization using the single conductivity type single crystal semiconductor substrate as a core. and then applying a selective thermal oxidation method to the single crystal semiconductor layer to form a field oxide film in contact with the periphery of the insulating film and defining a required active region; forming a gate electrode via a gate insulating film on a portion of the single crystal semiconductor layer located on the insulating film and defined by the field oxide film; a conductivity type drain region, and a one conductivity type source region common to a portion of the single crystal semiconductor layer, a part of which is on the insulating film and the other part is integrated with the one conductivity type single crystal semiconductor substrate. 1. A method for manufacturing a semiconductor device, comprising the steps of forming each of the following steps:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8488580A JPS5710267A (en) | 1980-06-23 | 1980-06-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8488580A JPS5710267A (en) | 1980-06-23 | 1980-06-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5710267A JPS5710267A (en) | 1982-01-19 |
| JPH0467336B2 true JPH0467336B2 (en) | 1992-10-28 |
Family
ID=13843210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8488580A Granted JPS5710267A (en) | 1980-06-23 | 1980-06-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5710267A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58153850A (en) * | 1982-03-08 | 1983-09-13 | 極東鋼弦コンクリ−ト振興株式会社 | Block for tensioning and fixing ring- shaped pc steel material |
| US5962869A (en) * | 1988-09-28 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor material and method for forming the same and thin film transistor |
| US5753542A (en) * | 1985-08-02 | 1998-05-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for crystallizing semiconductor material without exposing it to air |
| US5264720A (en) * | 1989-09-22 | 1993-11-23 | Nippondenso Co., Ltd. | High withstanding voltage transistor |
| JPH06151859A (en) * | 1992-09-15 | 1994-05-31 | Canon Inc | Semiconductor device |
| JP2891325B2 (en) * | 1994-09-01 | 1999-05-17 | 日本電気株式会社 | SOI semiconductor device and method of manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5513947A (en) * | 1978-07-17 | 1980-01-31 | Seiko Epson Corp | Semiconductor integrated circuit device |
-
1980
- 1980-06-23 JP JP8488580A patent/JPS5710267A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5513947A (en) * | 1978-07-17 | 1980-01-31 | Seiko Epson Corp | Semiconductor integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5710267A (en) | 1982-01-19 |
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