JPH0147897B2 - - Google Patents
Info
- Publication number
- JPH0147897B2 JPH0147897B2 JP21209981A JP21209981A JPH0147897B2 JP H0147897 B2 JPH0147897 B2 JP H0147897B2 JP 21209981 A JP21209981 A JP 21209981A JP 21209981 A JP21209981 A JP 21209981A JP H0147897 B2 JPH0147897 B2 JP H0147897B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- silicon layer
- layer
- single crystal
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000011253 protective coating Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 30
- 235000012239 silicon dioxide Nutrition 0.000 description 15
- 239000000377 silicon dioxide Substances 0.000 description 15
- 239000012535 impurity Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 235000013405 beer Nutrition 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- MUJOIMFVNIBMKC-UHFFFAOYSA-N fludioxonil Chemical group C=12OC(F)(F)OC2=CC=CC=1C1=CNC=C1C#N MUJOIMFVNIBMKC-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Recrystallisation Techniques (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は、立体的構造を有する半導体装置を製
造するのに好適な方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method suitable for manufacturing a semiconductor device having a three-dimensional structure.
近年、多結晶或いは非晶質のシリコンにレー
ザ・ビームを照射してアニールを行ない該シリコ
ンを単結晶化する技術が開発され、これに依ると
絶縁物上に単結晶シリコン層を得ることができる
ので、所謂SOS（silicon on saphire）構造と類
似の構造が安価に得られること、単結晶シリコン
層を絶縁層を介して多層に形成して装置を立体的
に構成できることなど多くの利点があるとされて
いる。 In recent years, a technology has been developed in which polycrystalline or amorphous silicon is irradiated with a laser beam and annealed to make the silicon into a single crystal. According to this technology, a single crystal silicon layer can be obtained on an insulator. Therefore, it has many advantages, such as the ability to obtain a structure similar to the so-called SOS (silicon on saphire) structure at low cost, and the ability to form devices three-dimensionally by forming multiple single-crystal silicon layers with insulating layers in between. has been done.
ところで、前記のように半導体装置を立体的に
構成するには単結晶シリコン層を介して多層に形
成し、それ等の単結晶シリコン層をビア・ホール
（via hole）を通して電気的に結合しなければら
ない。この実例が第１図に表わされている。 By the way, in order to configure a semiconductor device three-dimensionally as described above, it is necessary to form multiple layers with single crystal silicon layers interposed therebetween, and to electrically connect these single crystal silicon layers through via holes. It doesn't fall apart. An example of this is depicted in FIG.
第１図は従来技術を説明する為の半導体装置の
要部断面図である。 FIG. 1 is a sectional view of a main part of a semiconductor device for explaining the prior art.
図に於いて、１は基板、２は二酸化シリコン絶
縁体、３は第１層目単結晶シリコン層、３Ａは二
酸化シリコン絶縁領域、４は第１層目二酸化シリ
コン絶縁縁層、４Ａはビア・ホール、５はn+型
シリコン、６は第２層目単結晶シリコン層、６Ａ
は拡散領域をそれぞれ示す。 In the figure, 1 is a substrate, 2 is a silicon dioxide insulator, 3 is a first-layer single-crystal silicon layer, 3A is a silicon dioxide insulating region, 4 is a first-layer silicon dioxide insulating edge layer, 4A is a via. Hole, 5 is n + type silicon, 6 is second single crystal silicon layer, 6A
indicate the diffusion area, respectively.
図から明らかなように、第１層目単結晶シリコ
ン層３と第２層目単結晶シリコン層６とは第１層
目二酸化シリコン絶縁層４に形成されたビア・ホ
ール４Ａに充填されたn+型シリコン５に依つて
結合されている。尚、n+型シリコン５としては、
通常、多結晶シリコンを使用しているが、このよ
うなシリコンに代えて金属シリサイドも使用され
ている。 As is clear from the figure, the first monocrystalline silicon layer 3 and the second monocrystalline silicon layer 6 are formed by filling the via hole 4A formed in the first silicon dioxide insulating layer 4. They are coupled via + type silicon 5. In addition, as n + type silicon 5,
Usually, polycrystalline silicon is used, but metal silicide is also used instead of such silicon.
ところで、前記のように、ビア・ホール４Ａを
n+型シリコン５で充填した後、第２層目多結晶
シリコン層６を形成するには、先ず、例えば
CVD法にて多結晶シリコン層を形成し、それに
レーザ・ビームなどのエネルギ線を照射してアニ
ーリングを行なうことに依り単結晶化するもので
あるが、その際、ビア・ホール４Ａ内のn+型シ
リコン５も溶融することになるので、そこに含有
されているｎ型不純物が第２層目単結晶化シリコ
ン層６内に拡散され領域６Ａが形成されてしま
う。尚、液状シリコン中での不純物拡散速度は固
体中のそれに比較して著しく速い。 By the way, as mentioned above, via hole 4A
After filling with n + type silicon 5, in order to form the second polycrystalline silicon layer 6, first, for example,
A polycrystalline silicon layer is formed using the CVD method, and is made into a single crystal by annealing it by irradiating it with an energy beam such as a laser beam . Since the type silicon 5 is also melted, the n-type impurity contained therein is diffused into the second monocrystalline silicon layer 6, forming a region 6A. Note that the impurity diffusion rate in liquid silicon is significantly faster than that in solid silicon.
このような不所望の拡散が行なわれ、しかも、
その拡散は非制御状態の下でなされるものである
から、どの程度に広がつているのか予測すること
もできず、第２層目単結晶シリコン層６に素子を
形成する際に大きな障害になる。これは、ビア・
ホール４Ａに金属シリサイドを充填した場合にも
金属が第２層目単結晶シリコン層６中に拡散され
るので同様な欠点を生ずる。 This kind of undesired diffusion takes place, and furthermore,
Since the diffusion occurs under uncontrolled conditions, it is impossible to predict the extent to which it has spread, and this can be a major hindrance when forming elements in the second monocrystalline silicon layer 6. Become. This is beer
Even when the hole 4A is filled with metal silicide, the metal is diffused into the second monocrystalline silicon layer 6, resulting in a similar drawback.
本発明は、多層の単結晶シリコン層に素子を形
成した立体構造の半導体装置を製造する際にビ
ア・ホールに充填された材料の含有物質が前記単
結晶シリコン層中に不所望に拡散されることを防
止し、特性良好な半導体装置を得られるようにす
るもので、以下これを詳細に説明する。 The present invention provides a method for manufacturing a semiconductor device having a three-dimensional structure in which elements are formed in a multi-layered single-crystal silicon layer, in which substances contained in a material filled in a via hole are undesirably diffused into the single-crystal silicon layer. This will be explained in detail below.
第２図は本発明一実施例を説明する為の工程要
所に於ける半導体装置の要部断面図であり、第１
図に関して説明した部分と同部分を同記号で指示
してある。 FIG. 2 is a sectional view of a main part of a semiconductor device at key points in the process for explaining one embodiment of the present invention.
The same parts as those explained in relation to the figures are indicated by the same symbols.
本実施例では、第１層目二酸化シリコン絶縁層
４にビア・ホール４Ａを形成し、次に、例えば化
学気相堆積法にて不純物含有多結晶シリコン層を
形成し、次に、ビア・ホール４Ａ内に充填された
n+型シリコン５を残して他を全てエツチングす
ることに依り除去し、次に、n+型シリコン５の
表面に例えば熱酸化法にて二酸化シリコン膜７を
形成し、次に、再び化学気相堆積法にて多結晶シ
リコン層を成長させ、これにレーザ・ビームを照
射してアニールすることに依り単結晶シリコン層
６とするものである。 In this example, a via hole 4A is formed in the first silicon dioxide insulating layer 4, and then an impurity-containing polycrystalline silicon layer is formed by, for example, chemical vapor deposition. filled in 4A
Leaving the n + type silicon 5, all the others are removed by etching, then a silicon dioxide film 7 is formed on the surface of the n + type silicon 5 by, for example, a thermal oxidation method, and then again by chemical oxidation. A polycrystalline silicon layer is grown by a phase deposition method, and a single crystalline silicon layer 6 is formed by annealing it by irradiating it with a laser beam.
このようにすると、n+型シリコン５は二酸化
シリコン膜７で覆われているので、レーザ・ビー
ムのアニールを行なつてもｎ型不純物が単結晶シ
リコン層６中に拡散されることはない。尚、二酸
化シリコン膜７は熱酸化法でなく、化学気相堆積
法にて形成することができ、また、窒化シリコン
膜で代替しても良い。 In this way, since the n + -type silicon 5 is covered with the silicon dioxide film 7, n-type impurities will not be diffused into the single-crystal silicon layer 6 even if laser beam annealing is performed. Note that the silicon dioxide film 7 can be formed by a chemical vapor deposition method instead of a thermal oxidation method, and a silicon nitride film may be used instead.
さて、この後、素子の形成には種々の技法を採
ることができ、その一例を第３図について説明す
る。 Now, various techniques can be used to form the element, one example of which will be explained with reference to FIG.
第３図に於いて、第２層目単結晶シリコン層６
をパターニングしてメサ部を形成する。尚、単結
晶シリコン層６は適当な段階、例えばレーザ・ア
ニール時にｐ型化されているものとする。 In FIG. 3, the second single crystal silicon layer 6
is patterned to form a mesa part. It is assumed that the single crystal silicon layer 6 has been made p-type at an appropriate stage, for example, during laser annealing.
熱酸化法にて薄い二酸化シリコン絶縁膜を形成
し、次に、化学気相堆積法にて多結晶シリコン膜
を形成する。 A thin silicon dioxide insulating film is formed by thermal oxidation, and then a polycrystalline silicon film is formed by chemical vapor deposition.
フオト・リソグラフイ技術にて前記多結晶シリ
コン膜をパターニングしてシリコンン・ゲート電
極８を形成し、それをマスクにして前記薄い二酸
化シリコン膜のパターニングを行ないゲート絶縁
膜９を形成する。尚、この際同時に二酸化シリコ
ン膜７を除去し、多結晶シリコン５の表面を露出
する。 The polycrystalline silicon film is patterned using photolithography to form a silicon gate electrode 8, and using this as a mask, the thin silicon dioxide film is patterned to form a gate insulating film 9. Incidentally, at this time, the silicon dioxide film 7 is also removed to expose the surface of the polycrystalline silicon 5.
適宜の技法、例えばイオン注入法、気相拡散法
などに依りｎ型不純物の導入を行ない、ソース領
域いはドレイン領域となるn+型領域１０，１１
を形成する。 N type impurities are introduced by an appropriate technique such as ion implantation or vapor phase diffusion to form n + type regions 10 and 11 which will become source regions or drain regions.
form.
通常の技法にて、アルミニウムなどの金属電極
１２，１３を形成する。尚、電極１２は領域１０
と多結晶シリコン５を結んでいる。 Metal electrodes 12, 13, such as aluminum, are formed using conventional techniques. Note that the electrode 12 is in the region 10
and polycrystalline silicon 5.
第４図は素子形成する場合の他の実施例を表わ
すものであり、第３図に関して説明した部分と同
部分は同記号で指示してある。 FIG. 4 shows another embodiment in which elements are formed, and the same parts as those explained with reference to FIG. 3 are indicated by the same symbols.
この実施例では、電界効果トランジスタ部分を
メサ状にしていない。従つて、第２図に見られる
二酸化シリコン膜７を除去する為には第２層目単
結晶シリコン層６に窓を形成し、それを介して行
なわなければならない。そして、二酸化シリコン
膜７の除去が終つた後、窓には多結晶シリコン１
２を充填しておくものとする。 In this embodiment, the field effect transistor portion is not mesa-shaped. Therefore, in order to remove the silicon dioxide film 7 shown in FIG. 2, it is necessary to form a window in the second monocrystalline silicon layer 6 and perform the process through the window. After the silicon dioxide film 7 is removed, the window is filled with polycrystalline silicon 1.
2 shall be filled.
以上の説明で判るように、本発明に依れば、絶
縁層に形成されたビア・ホールを導電性材料で埋
め、それ等の上に多結晶或いは非晶質のシリコン
層を形成し、そのシリコン層にレーザ・ビームを
照射して単結晶化するに際し、前記導電材料表面
を該材料の含有物質が外方拡散を防止する被膜で
覆つてあるので、単結晶化されたシリコン層中に
不所望の物質が拡散されることは皆無であり、従
つて、該シリコン層には設計通りの素子を再現性
良く作り込むことができる。 As can be seen from the above description, according to the present invention, via holes formed in an insulating layer are filled with a conductive material, and a polycrystalline or amorphous silicon layer is formed on top of the via holes. When a silicon layer is irradiated with a laser beam to form a single crystal, the surface of the conductive material is covered with a coating that prevents out-diffusion of substances contained in the material. There is no possibility that the desired substance will be diffused, and thus designed elements can be fabricated in the silicon layer with good reproducibility.
第１図は従来技術を説明する為の半導体装置の
要部断面図、第２図乃至第４図は本発明を説明す
る為の半導体装置の要部断面図である。
図に於いて、１は基板、２は絶縁体、３は第１
層目単結晶シリコン層、３Ａは絶縁領域、４は第
１層目二酸化シリコン絶縁領域、５は多結晶シリ
コン、６は第２層目単結晶シリコン層、７は二酸
化シリコン膜である。
FIG. 1 is a sectional view of a main part of a semiconductor device for explaining the prior art, and FIGS. 2 to 4 are sectional views of main parts of a semiconductor device for explaining the present invention. In the figure, 1 is the substrate, 2 is the insulator, and 3 is the first
3A is an insulating region, 4 is a first silicon dioxide insulating region, 5 is polycrystalline silicon, 6 is a second single crystal silicon layer, and 7 is a silicon dioxide film.
Claims (1)
ルを有する絶縁層を形成し、次に、該ビア・ホー
ルを導電材料で埋め、次に、該導電材料の表面を
該導電材料の外方拡散防止被膜で覆い、次に、多
結晶或いは非晶質のシリコン層を形成し、次に、
該シリコン層にレーザ・ビームを照射して単結晶
化する工程が含まれてなることを特徴とする半導
体装置の製造方法。1. An insulating layer having via holes is formed on the underlying single crystal silicon layer, the via holes are then filled with a conductive material, and the surface of the conductive material is covered with out-diffusion of the conductive material. Cover with a protective coating, then form a polycrystalline or amorphous silicon layer, and then
A method for manufacturing a semiconductor device, comprising the step of irradiating the silicon layer with a laser beam to form a single crystal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21209981A JPS58116764A (en) | 1981-12-30 | 1981-12-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21209981A JPS58116764A (en) | 1981-12-30 | 1981-12-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58116764A JPS58116764A (en) | 1983-07-12 |
| JPH0147897B2 true JPH0147897B2 (en) | 1989-10-17 |
Family
ID=16616859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21209981A Granted JPS58116764A (en) | 1981-12-30 | 1981-12-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58116764A (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8950862B2 (en) * | 2011-02-28 | 2015-02-10 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus for an ophthalmic lens with functional insert layers |
| US10451897B2 (en) | 2011-03-18 | 2019-10-22 | Johnson & Johnson Vision Care, Inc. | Components with multiple energization elements for biomedical devices |
| US8857983B2 (en) | 2012-01-26 | 2014-10-14 | Johnson & Johnson Vision Care, Inc. | Ophthalmic lens assembly having an integrated antenna structure |
| US9793536B2 (en) | 2014-08-21 | 2017-10-17 | Johnson & Johnson Vision Care, Inc. | Pellet form cathode for use in a biocompatible battery |
| US10361405B2 (en) | 2014-08-21 | 2019-07-23 | Johnson & Johnson Vision Care, Inc. | Biomedical energization elements with polymer electrolytes |
| US9715130B2 (en) | 2014-08-21 | 2017-07-25 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus to form separators for biocompatible energization elements for biomedical devices |
| US10381687B2 (en) | 2014-08-21 | 2019-08-13 | Johnson & Johnson Vision Care, Inc. | Methods of forming biocompatible rechargable energization elements for biomedical devices |
| US9599842B2 (en) | 2014-08-21 | 2017-03-21 | Johnson & Johnson Vision Care, Inc. | Device and methods for sealing and encapsulation for biocompatible energization elements |
| US10361404B2 (en) | 2014-08-21 | 2019-07-23 | Johnson & Johnson Vision Care, Inc. | Anodes for use in biocompatible energization elements |
| US9941547B2 (en) | 2014-08-21 | 2018-04-10 | Johnson & Johnson Vision Care, Inc. | Biomedical energization elements with polymer electrolytes and cavity structures |
| US9383593B2 (en) | 2014-08-21 | 2016-07-05 | Johnson & Johnson Vision Care, Inc. | Methods to form biocompatible energization elements for biomedical devices comprising laminates and placed separators |
| US10627651B2 (en) | 2014-08-21 | 2020-04-21 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus to form biocompatible energization primary elements for biomedical devices with electroless sealing layers |
| US10345620B2 (en) | 2016-02-18 | 2019-07-09 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus to form biocompatible energization elements incorporating fuel cells for biomedical devices |
-
1981
- 1981-12-30 JP JP21209981A patent/JPS58116764A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58116764A (en) | 1983-07-12 |
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