JPH02864B2 - - Google Patents
Info
- Publication number
- JPH02864B2 JPH02864B2 JP56160546A JP16054681A JPH02864B2 JP H02864 B2 JPH02864 B2 JP H02864B2 JP 56160546 A JP56160546 A JP 56160546A JP 16054681 A JP16054681 A JP 16054681A JP H02864 B2 JPH02864 B2 JP H02864B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon film
- electrode
- polycrystalline
- electrode pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 9
- 238000010894 electron beam technology Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 239000013078 crystal Substances 0.000 description 11
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
- 230000010354 integration Effects 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920002554 vinyl polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置の電極配線の集積密度を
飛躍的に向上させる半導体装置の製造方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device that dramatically improves the integration density of electrode wiring in the semiconductor device.
近年、半導体装置の集積密度を高めるために、
絶縁基体表面に、もしくは半導体基体上に設けた
絶縁膜の表面に、多結晶もしくは非晶質のシリコ
ン膜を設け、当該膜にレーザー光もしくは電子ビ
ームを照射する等の手段によりこれを単結晶化す
る所謂SOI（silicon on insulator）技術が提案さ
れている。当該法によれば、単結晶層が多層に形
成できることから、装置の集積密度向上が期待で
きる。しかし、半導体装置においては、電極配線
に占める面積は全体の40％以上であり、SOI技術
を用いてトランジスタの能動領域を高密度化でき
たとしても配線の占める面積を低減できなければ
装置の高集積化は実現できない。 In recent years, in order to increase the integration density of semiconductor devices,
A polycrystalline or amorphous silicon film is provided on the surface of an insulating substrate or on the surface of an insulating film provided on a semiconductor substrate, and the film is made into a single crystal by irradiating the film with a laser beam or an electron beam. A so-called SOI (silicon on insulator) technology has been proposed. According to this method, since a single crystal layer can be formed into multiple layers, it is expected that the integration density of the device will be improved. However, in semiconductor devices, the area occupied by electrode wiring accounts for more than 40% of the total area, and even if it is possible to increase the density of the active area of a transistor using SOI technology, if the area occupied by wiring cannot be reduced, the device will become expensive. Integration is not possible.
従つて、装置の高集積化には配線を高密度化す
ることが不可欠である。 Therefore, it is essential to increase the density of wiring in order to increase the degree of integration of devices.
かかる目的のため、従来は配線パターンを２層
もしくは複数層に分けて形成することが行われて
いる。しかし、かかる方法は、半導体基板の表面
で、配線パターンを複数層に分けて行うことか
ら、集積密度をさらに高める。あるいは複雑なロ
ジツクを構成する等、大量の配線を行わなければ
ならない場合には装置の面積に限りがあることか
ら、配線パターンの幅を狭くする手法による外な
いのが現状である。 For this purpose, a wiring pattern has conventionally been formed in two or more layers. However, in this method, the wiring pattern is formed in multiple layers on the surface of the semiconductor substrate, which further increases the integration density. Alternatively, when a large amount of wiring is required, such as when configuring a complex logic, the area of the device is limited, so currently the only method available is to narrow the width of the wiring pattern.
しかし最近絶縁基体もしくは半導体基体表面に
設けられた絶縁膜の表面に、多結晶シリコン膜を
設け、これをレーザー光もしくは電子ビームの照
射等の手段で瞬間的に溶融し当該膜を単結晶化す
る技術が検討されており、かかる手段を用いて当
該単結晶膜の下層に配設パターンが埋め込まれれ
ば、従来の半導体装置にみられた配線形成の困難
さを改善できると本発明者は考えた。以下、本発
明をMOSトランジスタに適用した場合を例とし
て、図を用いて説明する。 However, recently, a polycrystalline silicon film is provided on the surface of an insulating film provided on the surface of an insulating substrate or a semiconductor substrate, and this is instantaneously melted by means such as laser light or electron beam irradiation to turn the film into a single crystal. The present inventor believes that the difficulty of wiring formation seen in conventional semiconductor devices can be improved if the technology is being studied and the arrangement pattern is embedded in the lower layer of the single crystal film using such means. . Hereinafter, an example in which the present invention is applied to a MOS transistor will be explained with reference to the drawings.
第１図は、本発明の一実施例を説明するための
図であり、各主要工程における半導体装置の断面
図である。図において、１は絶縁体基体、２は第
１の電極、３１，３２，３３は絶縁膜、３５はコ
ンタクトスルーホール、４は多結晶半導体膜、４
５は単結晶半導体膜、４７は不純物領域、５はレ
ーザ光もしくは電子ビームの照射方向、６１，６
５はイオンの飛来方向、７は第２の電極を、８は
第３の電極をそれぞれ示す。 FIG. 1 is a diagram for explaining one embodiment of the present invention, and is a cross-sectional view of a semiconductor device at each main step. In the figure, 1 is an insulating substrate, 2 is a first electrode, 31, 32, 33 are insulating films, 35 is a contact through hole, 4 is a polycrystalline semiconductor film, 4
5 is a single crystal semiconductor film, 47 is an impurity region, 5 is a laser beam or electron beam irradiation direction, 61, 6
Reference numeral 5 indicates the ion flying direction, 7 indicates the second electrode, and 8 indicates the third electrode.
今、一例としてＮチヤネルトランジスタを作る
場合について説明する。また絶縁体基体１とし
て、非晶質石英基板を使用して、製造工程を順を
追つて説明する。まず、第１図ａの如く基体１上
に第１の電極２が通常のフオトエツチング技術を
用いて形成される。当該電極の材質としては、リ
ン、ヒ素等のＮ型不純物を高濃度に含むポリシリ
コンもしくはタングステン、モリブデン、チタ
ン、白金等の少くとも1000℃の熱処理に耐え得る
いずれか一種もしくは複数の金属を用いるのが好
ましい。 Now, as an example, the case of manufacturing an N-channel transistor will be described. Further, the manufacturing process will be explained step by step using an amorphous quartz substrate as the insulating substrate 1. First, as shown in FIG. 1a, a first electrode 2 is formed on a substrate 1 using a conventional photoetching technique. The material used for the electrode is polysilicon containing a high concentration of N-type impurities such as phosphorus and arsenic, or one or more metals that can withstand heat treatment at at least 1000°C, such as tungsten, molybdenum, titanium, and platinum. is preferable.
次にSiO2もしくはSi3N4等の物質からなる非晶
質絶縁膜３１が、前記基体１および電極２の表面
に設けられた後、電極２の表面の絶縁膜３１の所
望の一部が選択的に除去され、コンタクトホール
３５が形成される（第１図ｂ）。 Next, an amorphous insulating film 31 made of a substance such as SiO 2 or Si 3 N 4 is provided on the surfaces of the base 1 and the electrode 2, and then a desired part of the insulating film 31 on the surface of the electrode 2 is removed. It is selectively removed to form a contact hole 35 (FIG. 1b).
次に、MOSトランジスタのアクテイブ領域を
形成するべく、少くとも前記のコンタクトホール
３５をおおう領域に、多結晶もしくは非晶質シリ
コン膜４が選択的に設けられ、続いて当該シリコ
ン膜４の表面もしくは当該シリコン膜４を含む前
記半導体基体１の表面に、レーザー光もしくは電
子ビーム５が照射され、シリコン膜４が再結晶化
し、単結晶もしくは単結晶に近いシリコン膜４５
になる（第１図ｃ）。当該シリコン膜４の好まし
い膜厚は0.3〜0.5ミクロンである。当該膜厚に対
するレーザー光の好ましい波長は0.5〜１ミクロ
ンであり、シリコン膜４の光吸収効率を増加する
べく、当該膜表面にSiO2等の膜を設けても良く、
また電極２が溶融もしくはシリコン膜４と反応す
る等の場合には、電極２をおおう表面領域にもシ
リコン膜４を設け、単結晶化する処理を行つた後
に不要のシリコン膜領域を選択除去すれば良い。
また電子ビームを照射する場合、チヤージアツプ
を防止するためシリコン膜４の表面に絶縁膜を介
して導電性電極を設けると良い結果を得る。 Next, in order to form an active region of the MOS transistor, a polycrystalline or amorphous silicon film 4 is selectively provided at least in a region covering the contact hole 35, and then a polycrystalline or amorphous silicon film 4 is selectively provided on the surface of the silicon film 4 or The surface of the semiconductor substrate 1 including the silicon film 4 is irradiated with a laser beam or an electron beam 5, and the silicon film 4 is recrystallized to form a single-crystal or near-single-crystal silicon film 45.
(Figure 1c). The preferred thickness of the silicon film 4 is 0.3 to 0.5 microns. The preferred wavelength of the laser beam for the film thickness is 0.5 to 1 micron, and in order to increase the light absorption efficiency of the silicon film 4, a film such as SiO 2 may be provided on the surface of the film.
In addition, if the electrode 2 melts or reacts with the silicon film 4, a silicon film 4 is also provided on the surface area covering the electrode 2, and the unnecessary silicon film area is selectively removed after the single crystallization process is performed. Good.
Further, when irradiating with an electron beam, good results can be obtained by providing a conductive electrode on the surface of the silicon film 4 with an insulating film interposed therebetween in order to prevent charge up.
さらに、シリコン膜４が基体１の表面全域に設
けられた後にレーザー光もしくは電子ビームを照
射し、当該膜を単結晶もしくはこれに近い膜と成
し、続いて選択的にパターンを形成して良いこと
は言うまでもない。 Furthermore, after the silicon film 4 is provided over the entire surface of the substrate 1, a laser beam or an electron beam may be irradiated to form the film into a single crystal or a film close to this, and then a pattern may be selectively formed. Needless to say.
コンタクトホール３５を介して単結晶シリコン
膜４５の電極２に接する部分は単結晶とはなり難
いため、MOSトランジスタのゲート領域は当該
コンタクトホールから２〜３ミクロン程度離れた
位置に形成するのが好ましい。 Since the portion of the single crystal silicon film 45 in contact with the electrode 2 through the contact hole 35 is unlikely to be a single crystal, the gate region of the MOS transistor is preferably formed at a position approximately 2 to 3 microns away from the contact hole. .
次に、単結晶シリコン膜４５の表面に絶縁膜３
２が形成されると共に、当該シリコン膜４５の不
純物濃度を制御するべくボロンイオン６１がイオ
ン打込みされ、続いて熱処理が行われる。（図
ｄ）。 Next, an insulating film 3 is formed on the surface of the single crystal silicon film 45.
2 is formed, boron ions 61 are implanted to control the impurity concentration of the silicon film 45, and then heat treatment is performed. (Figure d).
当該絶縁膜３２は単結晶シリコン膜４５を酸化
したSiO2を用いるのが最も簡単で良い結果を得
る。また、当該ボロンイオン打込みは、多結晶も
しくは非晶質シリコン膜４の形成時に所望量のボ
ロンを導入すれば省くことができる。 It is simplest to use SiO 2 obtained by oxidizing the single crystal silicon film 45 as the insulating film 32 and obtain good results. Further, the boron ion implantation can be omitted by introducing a desired amount of boron when forming the polycrystalline or amorphous silicon film 4.
次に第３の電極７が通常のフオトエツチング技
術を用いて形成され、続いて当該電極７をマスク
として単結晶膜４５にリン、ヒ素等のＮ型不純物
６５がイオン打込みされ（図ｅ）熱処理を経て前
記単結晶シリコン膜４５の一部にソース・ドレン
となるNT領域４７が形成される（図ｆ）。電極７
の材質としては、多結晶シリコンもしくはこれを
単結晶化せしめた膜、もしくはモリブデン、チタ
ン、白金、タングステン等の金属のいずれかを用
いることができる。 Next, a third electrode 7 is formed using a normal photoetching technique, and then, using the electrode 7 as a mask, N-type impurities 65 such as phosphorus and arsenic are ion-implanted into the single crystal film 45 (Fig. e) and heat treated. After that, an N T region 47 which becomes a source/drain is formed in a part of the single crystal silicon film 45 (FIG. f). Electrode 7
As the material, polycrystalline silicon, a single crystallized film of polycrystalline silicon, or a metal such as molybdenum, titanium, platinum, or tungsten can be used.
次に、絶縁膜３３が設けられた後に、電極７お
よびN+領域４７の表面の当該絶縁膜の一部が選
択的に除去され、続いて第３の電極８が形成され
ｎチヤネルMOSトランジスタが形成される（図
ｇ）。理解を深めるために、第１図ｇに示す構造
のトランジスタを平面図にすると例えば第２図に
示す如くなる。図において、第１図と同記号は同
一物質を示しており、第１図ｇに示された構造は
当該図の一点鎖線にそつた断面を示している。 Next, after the insulating film 33 is provided, a portion of the insulating film on the surfaces of the electrode 7 and the N + region 47 is selectively removed, and then the third electrode 8 is formed and the n-channel MOS transistor is formed. formed (Figure g). For better understanding, a plan view of the transistor having the structure shown in FIG. 1g is shown in FIG. 2, for example. In the figure, the same symbols as in FIG. 1 indicate the same materials, and the structure shown in FIG. 1g shows a cross section taken along the dashed line in the figure.
第１図、第２図で説明した半導体装置は、絶縁
基体表面に第１の電極２を形成した後にトランジ
スタの能動領域となる単結晶もしくはこれに近い
シリコン膜を形成するのが特徴であり、トランジ
スタのソースもしくはドレンとなるN+領域４７
の少くとも一方は第１の電極２を用いて接続され
るため、当該構造から成る半導体装置の表面での
配線の自由度が大幅に改善されることは明らかで
ある。 The semiconductor device described in FIGS. 1 and 2 is characterized in that after forming the first electrode 2 on the surface of the insulating substrate, a single crystal silicon film or a silicon film close to this is formed to become the active region of the transistor. N + region 47 that becomes the source or drain of the transistor
Since at least one of them is connected using the first electrode 2, it is clear that the degree of freedom in wiring on the surface of the semiconductor device having this structure is greatly improved.
また上記説明では絶縁基体として、非晶質石英
を用いたが、表面に非晶質絶縁膜もしくは
Al2O3、マグネシアスビネル等の単結晶絶縁膜を
設けた単結晶シリコンを基体として用いても、本
発明が適用できることは明らかである。 In addition, in the above explanation, amorphous quartz was used as the insulating substrate, but the surface may have an amorphous insulating film or
It is clear that the present invention can be applied even if single crystal silicon provided with a single crystal insulating film of Al 2 O 3 , magnesia vinyl, etc. is used as the substrate.
第１図は、本発明の一実施例を説明するための
主要工程における半導体装置の断面図を示す。ま
た第２図は第１図ｇの平面図を示す。
図において、１は絶縁体基体、２は第１の電
極、３１，３２，３３は絶縁膜、３５はコンタク
トスルーホール、４は多結晶半導体膜、４５は単
結晶半導体膜、４７は不純物領域、５はレーザー
光もしくは電子ビームの照射方向、６１，６５は
イオンの飛来方向、７は第２の電極、８は第３の
電極をそれぞれ示す。
FIG. 1 shows a cross-sectional view of a semiconductor device in main steps for explaining an embodiment of the present invention. FIG. 2 also shows a plan view of FIG. 1g. In the figure, 1 is an insulating substrate, 2 is a first electrode, 31, 32, 33 are insulating films, 35 is a contact through hole, 4 is a polycrystalline semiconductor film, 45 is a single crystal semiconductor film, 47 is an impurity region, Reference numeral 5 indicates the irradiation direction of laser light or electron beam, 61 and 65 indicate the direction in which ions fly, 7 indicates the second electrode, and 8 indicates the third electrode.
Claims (1)
該電極パターン表面もしくは該電極パターンを含
む前記絶縁基体表面に絶縁膜を設け、次いで電極
パターン上の絶縁膜の一部を選択除去しコンタク
トスルーホールを形成し、続いて該コンタクトス
ルーホールに少くとも重なるべく前記電極パター
ン上もしくは前記電極パターンを含む絶縁体基体
表面に、多結晶もしくは非晶質シリコンから成る
膜を設け、これをパターン化し、続いてレーザー
光もしくは電子ビームを照射し前記多結晶もしく
は非晶質シリコン膜を再結晶化するか、あるいは
前記多結晶もしくは非晶質シリコンから成る膜を
設けた後レーザー光もしくは電子ビームを照射し
前記多結晶もしくは非晶質シリコン膜を再結晶化
し、これをパターン化することを特徴とする半導
体装置の製造方法。1. Form an electrode pattern on an insulating substrate, then provide an insulating film on the surface of the electrode pattern or the surface of the insulating substrate including the electrode pattern, and then selectively remove a part of the insulating film on the electrode pattern to form a contact through hole. Then, a film made of polycrystalline or amorphous silicon is provided on the electrode pattern or the surface of the insulator substrate including the electrode pattern so as to overlap at least with the contact through hole, and this is patterned. Either the polycrystalline or amorphous silicon film is recrystallized by irradiation with a laser beam or an electron beam, or the polycrystalline or amorphous silicon film is irradiated with a laser beam or an electron beam after the polycrystalline or amorphous silicon film is provided. A method for manufacturing a semiconductor device, characterized by recrystallizing a crystalline or amorphous silicon film and patterning it.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56160546A JPS5878455A (en) | 1981-10-08 | 1981-10-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56160546A JPS5878455A (en) | 1981-10-08 | 1981-10-08 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5878455A JPS5878455A (en) | 1983-05-12 |
| JPH02864B2 true JPH02864B2 (en) | 1990-01-09 |
Family
ID=15717317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56160546A Granted JPS5878455A (en) | 1981-10-08 | 1981-10-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5878455A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6054425A (en) * | 1983-09-05 | 1985-03-28 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
| JPS60200564A (en) * | 1984-03-24 | 1985-10-11 | Mitsubishi Electric Corp | Thin film semiconductor element integrated circuit device |
| JPS6163018A (en) * | 1984-09-04 | 1986-04-01 | Agency Of Ind Science & Technol | Manufacture of semiconductor thin film crystal layer |
| JPS61234088A (en) * | 1985-04-10 | 1986-10-18 | Agency Of Ind Science & Technol | Laser light irradiating device |
| JPH0824193B2 (en) * | 1990-10-16 | 1996-03-06 | 工業技術院長 | Manufacturing method of semiconductor device for driving flat plate type light valve |
| KR101594335B1 (en) * | 2007-12-03 | 2016-02-16 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and manufacturing method thereof |
-
1981
- 1981-10-08 JP JP56160546A patent/JPS5878455A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5878455A (en) | 1983-05-12 |
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