JPS6163018A - Manufacture of semiconductor thin film crystal layer - Google Patents
Manufacture of semiconductor thin film crystal layerInfo
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- JPS6163018A JPS6163018A JP59183730A JP18373084A JPS6163018A JP S6163018 A JPS6163018 A JP S6163018A JP 59183730 A JP59183730 A JP 59183730A JP 18373084 A JP18373084 A JP 18373084A JP S6163018 A JPS6163018 A JP S6163018A
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- thin film
- semiconductor thin
- film
- semiconductor
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
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- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
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Abstract
Description
【発明の詳細な説明】
〔発明の技術分野)
本発明は、絶縁膜上に半導体薄膜結晶層を製造する方法
に係わり、特にビームアニール技術を用いた半導体薄膜
結晶層の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor thin film crystal layer on an insulating film, and more particularly to a method of manufacturing a semiconductor thin film crystal layer using beam annealing technology.
近年、SO8基板に代わるものとして5ol(絶縁膜上
のシリコン)基板が提案されている。In recent years, a 5OL (silicon on insulating film) substrate has been proposed as an alternative to the SO8 substrate.
このSol基板は、5osi板の特徴を有しながらサフ
ァイア等の高価な基板を用いる必要もないので、大面積
のものも安価に形成することができる。また、3次元I
Cへの応用にも有効であり、将来のVLS Iの一旦を
担うものとして注目されている。Although this Sol substrate has the characteristics of a 5OSI board, it does not require the use of an expensive substrate such as sapphire, so it can be formed with a large area at low cost. Also, three-dimensional I
It is also effective in application to C, and is attracting attention as something that will play a role in future VLSI.
ところで、上記のSOI構造は最近発達したビームアニ
ール法によって部分的に可能となっている。即ち、Si
を例にとると、単結晶Si基板を酸化してSiO2膜を
形成した後、この一部を除去して開孔部を設け、次いで
全面に多結晶S + n9を被着しSi基板表面からS
iO2膜上まで多結晶Si膜を連続して延在させる。次
に、多結晶Sillに電子ビームやレーザビーム等のエ
ネルギービームを照射走査すると、基板表面で溶融した
多結晶S1膜が基板から液相エピタキシャル成長によっ
て単結晶化し、さらにビームの走査方向に沿ってS i
02 II上の多結晶Si膜もそれに引き続き単結晶
化されることになる。By the way, the above-mentioned SOI structure is partially made possible by the recently developed beam annealing method. That is, Si
For example, after oxidizing a single-crystal Si substrate to form a SiO2 film, a portion of this is removed to form an opening, and then polycrystalline S+N9 is deposited on the entire surface and the film is grown from the surface of the Si substrate. S
The polycrystalline Si film is continuously extended onto the iO2 film. Next, when the polycrystalline Sill is irradiated and scanned with an energy beam such as an electron beam or a laser beam, the polycrystalline S1 film melted on the substrate surface becomes a single crystal by liquid phase epitaxial growth from the substrate, and then the Sill is further grown along the beam scanning direction. i
Subsequently, the polycrystalline Si film on 02 II will also be made into a single crystal.
しかしながら、この種の方法にあっては次のような問題
があった。即ち、開孔部上に被着した多結晶Si膜を溶
融せしめるのに必要なエネルギーはSi0211上での
それと比較して高くなり、SiQ2膜上の多結晶Sil
llをアニールするに必要なエネルギーでは開孔部上の
多結晶Sillが十分にアニールされず良質の結晶は得
られない。これはSiの熱伝導率がSiO2のそれより
も大きいため、開孔部上の多結晶Si!!!では熱が基
板下方に伝導していく割合いが大きくなり、基板表面近
くの温度がSiQz腹上の多結晶S1膜よりも同一エネ
ルギー条件の下では低くなるからである。However, this type of method has the following problems. That is, the energy required to melt the polycrystalline Si film deposited on the opening is higher than that on Si0211, and
The polycrystalline Sill above the opening is not sufficiently annealed by the energy required to anneal Sill, and a high-quality crystal cannot be obtained. This is because the thermal conductivity of Si is higher than that of SiO2, so the polycrystalline Si above the opening! ! ! This is because the rate at which heat is conducted downward to the substrate increases, and the temperature near the substrate surface becomes lower than that of the polycrystalline S1 film on the SiQz anode under the same energy conditions.
これを解決するために、エネルギーを大きく(開孔部上
の多結晶S:膜も十分にアニールされる程度に)すると
、Si0211上の多結晶Silllが加熱され過ぎて
蒸発を起こし、Si0211!上に形成される単結晶s
rs表面の平滑性が失われる現象が見られる。このため
、従来の方法では、結晶性及び表面平滑性の優れた単結
晶層を(qることは困難であった。To solve this problem, if the energy is increased (to the extent that the polycrystalline S: film on the opening is also sufficiently annealed), the polycrystalline Sill on Si0211 is heated too much and evaporates, causing Si0211! Single crystal s formed on
A phenomenon in which the smoothness of the rs surface is lost is observed. Therefore, with conventional methods, it has been difficult to form a single crystal layer with excellent crystallinity and surface smoothness.
(発明の目的〕
本発明の目的は、絶縁膜上に結晶性及び表面平滑性の優
れた単結晶半導体111層を形成することができ、3次
元IC等の製造に好適する半導体薄膜結晶層の製造方法
を提供することにある。(Object of the Invention) The object of the present invention is to form a semiconductor thin film crystal layer that can form a single crystal semiconductor layer with excellent crystallinity and surface smoothness on an insulating film, and is suitable for manufacturing three-dimensional ICs. The purpose is to provide a manufacturing method.
本発明の骨子は、単結晶形成の種部となる開孔部の基板
上に該基板よりも融点の低い半導体を予め形成し、開孔
部でのアニールに必要なエネルギーを低く抑えることに
ある。The gist of the present invention is to form in advance a semiconductor having a melting point lower than that of the substrate on the substrate in the opening, which serves as a seed for single crystal formation, and to suppress the energy required for annealing in the opening. .
即ち本発明は、絶縁膜上に半導体1腹結晶層を製造する
方法において、単結晶半導体基板上に一部開孔部が設け
られた絶縁膜したのち、上記開孔部に露出した基板上に
該基板よりも融点の低い第1の半導体薄膜を選択的にエ
ピタキシャル成長し、次いで全面に第2の半導体コ膜を
形成し、しかるのち上記第2の半導体薄膜にエネルギー
ビームを照射して該半導体薄膜を溶融再結晶化するよう
にした方法である。That is, the present invention provides a method for manufacturing a semiconductor first crystal layer on an insulating film, in which an insulating film is formed on a single-crystal semiconductor substrate in which a portion of an opening is formed, and then a layer is formed on the substrate exposed in the opening. A first semiconductor thin film having a melting point lower than that of the substrate is selectively grown epitaxially, a second semiconductor film is then formed on the entire surface, and then an energy beam is irradiated to the second semiconductor thin film to form the semiconductor thin film. This method involves melting and recrystallizing.
本発明によれば、開孔部にある第1の半導体薄膜が第2
の半導体薄膜よりも先に溶融するので、開孔部上の第2
の半導体薄膜の溶融・再結晶化に必要なビームのエネル
ギーを低く抑えることができる。このため、絶縁膜上の
半導体薄膜をビームアニールするに必要なエネルギーで
開孔部上の第2の半導体薄膜を十分にアニールすること
ができる。従って、開孔部上の半導体′a膜のアニール
不足や絶縁股上の半導体薄膜の蒸発等を防止することが
でき、絶縁膜上に形成する単結晶半導体薄膜層の結晶性
及び表面平滑性の向上をはかり得る。According to the present invention, the first semiconductor thin film in the opening portion is replaced by the second semiconductor thin film.
Since the semiconductor thin film melts earlier than the second semiconductor thin film above the opening,
The beam energy required for melting and recrystallizing semiconductor thin films can be kept low. Therefore, the second semiconductor thin film on the opening can be sufficiently annealed with the energy necessary for beam annealing the semiconductor thin film on the insulating film. Therefore, it is possible to prevent insufficient annealing of the semiconductor'a film on the opening and evaporation of the semiconductor thin film on the insulating film, improving the crystallinity and surface smoothness of the single crystal semiconductor thin film layer formed on the insulating film. can be measured.
以下、本発明の詳細を図示の実施例によって説明する。 Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第1図乃至第4図は本発明の一実施例に係わる半導体薄
膜結晶層の製造工程を示す断面図である。1 to 4 are cross-sectional views showing the manufacturing process of a semiconductor thin film crystal layer according to an embodiment of the present invention.
まず、第1図に示す如<(100)面方位の単結晶S’
+基板(単結晶半導体基板)1を前記化して基板1上に
厚さI EumコのS i 02膜(絶all)2を形
成した後、SiOzll12の一部に開孔部3を形成し
た。次いで、所定の前処理を施し、上記試料を気相成長
装置に入れ、水素ガス雰囲気中にGeCl 4ガス、H
CIガスを添加し、基板温度800 [”C]において
第2図に示す如く開孔部3の基板1上のみにGe膜(第
1の半導体重11)4を選択エピタキシャル成長せしめ
た。ここで、GeはSiよりも溶融温度の低い半導体で
ある。次いで、M3図に示す如く全面に多結晶SIII
i(M2の半導体薄膜)5を気相成長”法により0.6
[μ′rrL]の厚さに被着した。First, as shown in FIG.
After the substrate (single-crystal semiconductor substrate) 1 was prepared as described above and an Si02 film (all) 2 having a thickness of I Eum was formed on the substrate 1, an opening 3 was formed in a part of the SiOzll12. Next, a predetermined pretreatment is performed, and the sample is placed in a vapor phase growth apparatus, and GeCl 4 gas, H
CI gas was added and a Ge film (first semiconductor layer 11) 4 was selectively epitaxially grown only on the substrate 1 in the opening 3 as shown in FIG. 2 at a substrate temperature of 800 [''C].Here, Ge is a semiconductor with a lower melting temperature than Si.Next, as shown in the M3 diagram, polycrystalline SIII is formed on the entire surface.
i (semiconductor thin film of M2) 5 to 0.6 by vapor phase growth method
It was deposited to a thickness of [μ′rrL].
次に、第4図に示す如く試料表面に電子ビーム6を照射
し、多結晶S1腹5及びQe膜4を溶融−固化すること
により、開孔部3から横方向へエピタキシャル成長I!
(単結晶3il)7を成長させた。用いた電子ビームは
CW型であり、ビーム照射時に基板温度を500 [”
C]とした。ここで、上記ビームアニールに際し、開孔
部3上の多結晶S i Ml 5は下地のGe114が
十分に溶融しているので、3iを十分アニールするに必
要なエネルギーがなくてもエピタキシャル成長が可能で
ある。Next, as shown in FIG. 4, the surface of the sample is irradiated with an electron beam 6 to melt and solidify the polycrystalline S1 film 5 and the Qe film 4, thereby causing epitaxial growth I! from the opening 3 in the lateral direction.
(single crystal 3il) 7 was grown. The electron beam used was a CW type, and the substrate temperature was kept at 500 ["
C]. Here, during the beam annealing described above, since the base Ge 114 of the polycrystalline S i Ml 5 on the opening 3 is sufficiently melted, epitaxial growth is possible without the energy required to sufficiently anneal 3i. be.
このため、SiOzB!2上の多結晶Si膜5をアニー
ルするに必要なエネルギービームで開孔部3上の多結晶
Silll15をエピタキシャル成長させることが可能
となる。For this reason, SiOzB! It becomes possible to epitaxially grow the polycrystalline Si film 15 on the opening 3 with the energy beam necessary to anneal the polycrystalline Si film 5 on the opening 3.
このように本実施例方法によれば、SiO2膜2の開孔
部3にSiよりも融点の低いQe膜4を選択形成してお
くことにより、SiO211I2上の多結晶3i膜5を
ビームアニールするに必要なエネルギーで開孔部3上の
多結晶Si膜5を十分にエピタキシャル成長させること
ができる。このため、S ! 021[*2上に結晶性
及び表面平滑性の優れた単結晶3i層7を形成すること
ができる。As described above, according to the method of this embodiment, by selectively forming the Qe film 4 having a lower melting point than Si in the opening 3 of the SiO2 film 2, the polycrystalline 3i film 5 on the SiO211I2 is beam annealed. The polycrystalline Si film 5 on the opening 3 can be sufficiently epitaxially grown with the energy required for this. For this reason, S! A single crystal 3i layer 7 having excellent crystallinity and surface smoothness can be formed on 021[*2.
なお、本発明は上述した実施例に限定されるものではな
い。例えば、前記開孔部の基板上に形成する第1の半導
体簿膜はQ’eに限るものではなく、基板よりも融点の
低い半導体で選択エピタキシャル成長可能なものであれ
ばよい。また、第2の半導体薄膜は多結晶Siに限るも
のではなく、非晶質3iであってもよく、ざらに各種の
半導体を用いることが可能である。また、エネルギービ
ームとしては、電子ビームの代りにレーザビームを用い
ることが可能である。ざらに、カーボンヒータを用い、
このヒータを走査するようにしてもよい。Note that the present invention is not limited to the embodiments described above. For example, the first semiconductor film formed on the substrate in the opening is not limited to Q'e, but may be any semiconductor having a lower melting point than the substrate and capable of selective epitaxial growth. Further, the second semiconductor thin film is not limited to polycrystalline Si, but may be amorphous 3i, and various semiconductors can be used. Further, as the energy beam, a laser beam can be used instead of an electron beam. Roughly, using a carbon heater,
This heater may be scanned.
その他、本発明の要旨を逸脱しない範囲で、種々変形し
て実施することができる。In addition, various modifications can be made without departing from the gist of the present invention.
第1図乃至第4図は本発明の一実施例に係わる半導体1
IP1結晶層の製造工程を示す断面図である。
1・・・単結晶Si基板(単結晶半導体基板)、2・・
・SiOz膜(絶縁膜)、3・・・開孔部、4・・・G
el1lI(第1の半導体薄膜)、5・・・多結晶Si
ll!(第2の半導体薄膜)、6・・・電子ビーム、7
・・・エピタキシャル成長層。1 to 4 show a semiconductor 1 according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of an IP1 crystal layer. 1... Single crystal Si substrate (single crystal semiconductor substrate), 2...
・SiOz film (insulating film), 3...opening part, 4...G
el1lI (first semiconductor thin film), 5... polycrystalline Si
ll! (second semiconductor thin film), 6...electron beam, 7
...Epitaxial growth layer.
Claims (4)
縁膜を形成する工程と、上記開孔部に露出した基板上に
該基板よりも融点の低い第1の半導体薄膜を選択的にエ
ピタキシャル成長する工程と、次いで全面に第2の半導
体薄膜を形成する工程と、上記第2の半導体薄膜にエネ
ルギービームを照射し該半導体薄膜を溶融再結晶化する
工程とを含むことを特徴とする半導体薄膜結晶層の製造
方法。(1) A step of forming an insulating film partially provided with an opening on a single crystal semiconductor substrate, and selecting a first semiconductor thin film having a melting point lower than that of the substrate on the substrate exposed in the opening. the second semiconductor thin film, and the second semiconductor thin film is irradiated with an energy beam to melt and recrystallize the semiconductor thin film. A method for manufacturing a semiconductor thin film crystal layer.
iであることを特徴とする特許請求の範囲第1項記載の
半導体薄膜結晶層の製造方法。(2) The semiconductor substrate and the second semiconductor thin film are S
2. The method for manufacturing a semiconductor thin film crystal layer according to claim 1, wherein: i.
とする特許請求の範囲第1項又は第2項記載の半導体薄
膜結晶層の製造方法。(3) The method for manufacturing a semiconductor thin film crystal layer according to claim 1 or 2, wherein the first semiconductor thin film is made of Ge.
レーザビームを用いたことを特徴とする特許請求の範囲
第1項記載の半導体薄膜結晶層の製造方法。(4) The method for manufacturing a semiconductor thin film crystal layer according to claim 1, wherein an electron beam or a laser beam is used as the energy beam.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59183730A JPS6163018A (en) | 1984-09-04 | 1984-09-04 | Manufacture of semiconductor thin film crystal layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59183730A JPS6163018A (en) | 1984-09-04 | 1984-09-04 | Manufacture of semiconductor thin film crystal layer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6163018A true JPS6163018A (en) | 1986-04-01 |
JPH0236052B2 JPH0236052B2 (en) | 1990-08-15 |
Family
ID=16140962
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59183730A Granted JPS6163018A (en) | 1984-09-04 | 1984-09-04 | Manufacture of semiconductor thin film crystal layer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6163018A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6336514A (en) * | 1986-07-30 | 1988-02-17 | Sony Corp | Manufacture of thin single-crystal semiconductor film |
JPH0283915A (en) * | 1988-09-20 | 1990-03-26 | Ricoh Co Ltd | Manufacture of semiconductor single crystal thin film |
KR100518922B1 (en) * | 1996-01-30 | 2006-01-27 | 세이코 엡슨 가부시키가이샤 | Formation method of crystalline film and manufacturing method of thin film electronic device |
JP2013505578A (en) * | 2009-09-16 | 2013-02-14 | アプライド マテリアルズ インコーポレイテッド | A method for solid-phase recrystallization of thin films using pulse train annealing. |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5878455A (en) * | 1981-10-08 | 1983-05-12 | Nec Corp | Manufacture of semiconductor device |
JPS5893222A (en) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | Preparation of semiconductor single crystal film |
-
1984
- 1984-09-04 JP JP59183730A patent/JPS6163018A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5878455A (en) * | 1981-10-08 | 1983-05-12 | Nec Corp | Manufacture of semiconductor device |
JPS5893222A (en) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | Preparation of semiconductor single crystal film |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6336514A (en) * | 1986-07-30 | 1988-02-17 | Sony Corp | Manufacture of thin single-crystal semiconductor film |
JPH0283915A (en) * | 1988-09-20 | 1990-03-26 | Ricoh Co Ltd | Manufacture of semiconductor single crystal thin film |
KR100518922B1 (en) * | 1996-01-30 | 2006-01-27 | 세이코 엡슨 가부시키가이샤 | Formation method of crystalline film and manufacturing method of thin film electronic device |
JP2013505578A (en) * | 2009-09-16 | 2013-02-14 | アプライド マテリアルズ インコーポレイテッド | A method for solid-phase recrystallization of thin films using pulse train annealing. |
Also Published As
Publication number | Publication date |
---|---|
JPH0236052B2 (en) | 1990-08-15 |
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