JPS63291416A - Semiconductor substrate - Google Patents

Abstract

PURPOSE:To improve the mechanical strength and thermal conductivity of a substrate and have a favorable insulation property by forming a single crystal compound semiconductor layer on an insulation layer where a semiconductor substrate consisting of a single element is dielectrically isolated through a semiconductor layer which has the same quality as that of a very thin filmed substrate. CONSTITUTION:After forming an insulating layer 2 consisting of amorphous SiO2 on a silicon substrate 1, an opening 3 for seeding is formed at the prescribed position of the insulating layer 2 with a photolithographical technique by using a resist formed on the insulating layer 2 as a mask. Then, after forming a silicon layer 4 having a 5000 Angstrom film thickness with a LPCVD technique and the like on the insulating layer 2 including the inside of the opening 3, this layer is crystallized to form a single crystal by a melting recrystallization technique using a laser or an electron beam. And then, the oxidation of a silicon single crystal layer in an atmosphere of dry oxygen at a temperature of 1100 deg.C allows a thermal oxide film 5 to grow about 9500 Angstrom film thickness at the silicon layer 4 and its film 5 is removed by etching with an etchant of buffer hydrofluoric acid (HF+NH4F) and the silicon layer 4 having the desired very thin film remains on the insulating layer 2. Further, this approach grows compound semiconductors such as GaAs, InP and the like on the very thin filmed silicon layer 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor substrate, and more particularly to a semiconductor substrate having a composite structure of a semiconductor substrate made of a single element and a compound semiconductor layer.

[Conventional technology] Compound semiconductors, especially ■-V group compound semiconductors, are superior to silicon semiconductors in terms of high speed, low power consumption, low noise, etc., and the development of devices that take advantage of these characteristics has been actively promoted recently. It is being

However, these compound semiconductors are expensive, it is difficult to obtain large-area substrates, and they also have problems such as mechanical brittleness and low thermal conductivity.

From this background, QaΔS etc.
(3) Technology for heteroepitaxial growth of compound semiconductors (III-Yon 3i) is rapidly progressing.

[Problems to be Solved by the Invention] In order to use the conventional heteroepitaxial substrate as described above for high-speed devices, it is necessary to compare it with a conventional element formed on a semi-insulating bulk substrate of a single compound semiconductor. This has the following problems.

Due to the low resistance of the silicon substrate that is the base of the heteroepitaxial substrate, (1) characteristics such as propagation loss and propagation delay deteriorate, and (2) isolation characteristics between elements deteriorate.

This invention was made to solve this problem, and even with such a HedeO epitaxial structure,
The aim is to effectively increase the resistance of the substrate and provide a semiconductor substrate suitable for application to ultra-high-speed devices, integrated circuits, etc.

[Means for Solving the Problems] A semiconductor substrate according to the present invention includes a single-crystal semiconductor layer made of a single element and a single-crystal semiconductor layer having the same quality as the semiconductor substrate, with an amorphous insulating layer interposed therebetween. is formed, and a single crystal compound semiconductor layer is further formed thereon, and the thickness of the semiconductor layer is made sufficiently smaller than the thickness of the compound semiconductor layer.

[Function] In this invention, the low-resistance semiconductor substrate and the compound semiconductor layer are separated by an insulating layer, and since the semiconductor layer on the insulating layer is sufficiently thinner than the compound semiconductor layer, the high-resistance characteristics of the compound semiconductor can be maintained. Don't lower it.

[Example] It is desirable that single crystal silicon serving as a substrate in the examples described below has as high a resistivity as possible. In other words, in order to reduce conduction loss due to coupling between wiring resistance and capacitance and coupling between carriers in the board and 7tfm waves, the thickness should be set to H (μm) and resistivity ρ (Ω).
am), it is preferable to satisfy the relationship ρ·H≧104. Further, for the same reason, it is desirable that the thickness h (μIl) of the amorphous insulating layer be as thick as the growth method allows.

Furthermore, it is preferable that the single crystal silicon layer formed on the amorphous insulating layer also has as high resistance as possible.

This single crystal silicon layer is formed by a melt recrystallization method, but its resistance is usually 10 to 100ΩCl, which is about 1QS to 106 lower than that of conventional semi-insulating m-■ compounds. This causes propagation loss and propagation delay. In the present invention, in order to prevent this, the single crystal silicon layer is made into an ultra-thin film. Here, ultra-thin film means 1
This means a film thickness of 000A or less, preferably about 100A.

In order for the silicon single crystal layer to be able to reduce propagation loss and propagation delay, it is necessary that its sheet resistance has a value equivalent to that of a semi-insulating ■-v compound, and the above film thickness is It satisfies the following.

FIGS. 1A to 1D are schematic manufacturing process diagrams showing one embodiment of the present invention.

The manufacturing method will be described below with reference to the drawings.

First, the thickness is 300 μm and the specific resistance is 100 to 1000 Ωcm.
A p-type silicon substrate 1 (100) having a diameter of 2 inches is prepared. The compound semiconductor layer formed as the top layer will be a single crystal that inherits the crystallinity of this silicon substrate 1, but in order to make it a single domain high quality crystal, the silicon substrate 1 is 56 It is useful to use one with an inclined surface. APCVDSLPCVD or 75X' on silicon substrate 1?
An insulating layer 2 made of amorphous S10□ with a thickness of 1 to 4 μm is formed by a CVD method or the like, and an opening 3 for seeding is formed in a photolithography process using the resist formed thereon as a mask.
is formed at a predetermined position on the insulating layer 2. Next, a #5000A silicon layer 4 is formed on the insulating layer 2 including inside the opening 3 by the Lpcvo method or the like, and then In is crystallized by a melting recrystallization method using a laser or an electron beam. In this embodiment, the silicon layer 4 is irradiated with a scanning electron beam of 10 KeV, heated to 1400° C. or higher to melt it, and then recrystallized to form a single crystal silicon layer 4. There is. Note that it is desirable to maintain the substrate temperature in this step at about 400 to 500°C.

With such a method, a silicon single crystal layer with a large area can be obtained relatively easily by the lateral seeding method using the openings 3 that serve as poled portions.

In this case, whether a good single crystal can be obtained depends on how appropriately the shape of the opening 3 of the poled portion can be selected. For example, good melting and recrystallization can be achieved by forming the openings in a line shape with a width of 5 μm and arranging them parallel to each other at intervals of 10 to 100 μm.
It has an m-square dot shape. This is because the dot-shaped openings with minute areas prevent the heat from molten silicon from escaping rapidly from the openings to the silicon substrate during the melting and recrystallization process, while maintaining the seeding mechanism. This is because it helps prevent sudden temperature changes and destabilization of the melt recrystallization process.

In this example, the openings are 5 μm square dots arranged planarly at intervals of 200×300 μl1, and a single crystal silicon layer 4 with a large area on the order of 1×11 is well formed (first A (see figure).

The silicon layer 4 obtained in this way has a resistance of 10 to 100Ω.
Although it has a conductivity of about Cl11, this silicon layer is then made into a super Rfil from 5000 to 20 OA. In this example, as a method for thinning the silicon single crystal layer, 11
Thermal oxidation II on the silicon layer 4 by oxidation in a dry oxygen atmosphere at 00°C! Grow I5 to a film thickness of about 9500A (
(see Figure 1B), and buffer this (HF+N1-14F
) to leave the desired ultra-thin silicon layer 4 on the insulating layer 2 (see FIG. 1C).

Note that it is also possible to make the silicon layer 4 ultra-thin by simply etching the surface of the silicon layer 4 using hot phosphoric acid or the like without using the thermal oxidation method described above.

By making the silicon layer 4 ultra-thin as described above, the silicon layer has a
A high sheet resistance of MΩ/mouth or higher can be provided.

Subsequently, QaA is deposited on the silicon layer 4, which has a thickness exceeding 1tll.
A compound semiconductor such as S, InP, etc. is grown, and the MOC:VD method or the like can be applied to this. Below, MOCV
A case will be described in which InP is heteroepitaxially grown via an intermediate layer using the D method, but it is also possible to grow InP directly on the silicon layer 4 to form a single compound semiconductor layer.

After cleaning the surface of the ultra-thin silicon layer 4 with )-IF, it is loaded into a susceptor in an MOCVD apparatus, and P
H, (50% H2 dilution) and H2 in total amount 6-7SL
While flowing M, the temperature is raised to 1000° C. and heat treatment is performed for 10 minutes. Next, with the temperature lowered to 650-700°C, TEGa (triethyl gallium) and PH,
Furthermore, H2 was introduced at the same time, 6-7 SLM was flowed with Ial, and about 50-10
A first compound semiconductor layer 6 made of QaP of 0A is formed on the silicon layer 4. Furthermore, the same flow rate and total flow rate of PH as when forming the first compound semiconductor layer 6 are fixed,
TEGa for GaP and TMIn(t-
By changing the bubbling H2 gas supply m to m* to InP and switching the gas introduction to the TMIn and TEGa reactors at intervals of 3 to 9 seconds at a growth rate of ~60X/min. A second compound semiconductor layer 7 made of a superlattice layer of /Ga 2 P is formed on the first compound semiconductor layer 6 .

Finally, fix the flow rate of PH and the total flow rate in the same way as above, and adjust T so that the growth rate is 200 to 300 A/1n.
By setting the 12 gas supply barrier to MTn, 1
A third compound semiconductor layer 8 made of lnP with a thickness of ~2 μm is epitaxially grown on the second compound semiconductor layer 7 .

As a result of the above, a high-quality InP single crystal layer having a single domain, a mirror surface, and a carrier mobility close to that of the bulk can be obtained (see FIG. 1D).

In the above embodiment, silicon is used as the single-element substrate and InPlGaP is used as the compound semiconductor, but other single-element semiconductors or other compound semiconductors may have the same function. Needless to say, it can be applied if there is a similar effect.

[Effects of the Invention] As explained above, the present invention insulates and separates a semiconductor substrate made of a single element with an insulating layer, and then forms a single crystal compound semiconductor layer via an ultra-thin semiconductor layer of the same quality as the substrate. Therefore, the mechanical strength and thermal conductivity of the substrate are improved while maintaining the excellent properties of compound semiconductors, and the semiconductor substrate has the effect of having good insulation properties.

[Brief explanation of the drawing]

FIGS. 1A to 1D are schematic manufacturing process diagrams showing an embodiment of the present invention. In the figure, 1 is a silicon substrate, 2 is an insulating layer, 3 is an opening, 4 is a silicon layer, 6 is a first compound semiconductor layer, 7 is a second compound semiconductor layer, and 8 is a third compound semiconductor layer. be. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 1A Figure 1B Figure 10

Claims (1)

[Scope of Claims] A single-crystal semiconductor substrate made of a single element, an amorphous insulating layer formed on the semiconductor substrate, and a monocrystalline semiconductor substrate formed on the insulating layer of the same quality as the semiconductor substrate. A semiconductor substrate comprising: a crystalline semiconductor layer; and a single-crystalline compound semiconductor layer formed on the semiconductor layer, wherein the thickness of the semiconductor layer is sufficiently smaller than the thickness of the compound semiconductor layer.