JPH0450746B2 - - Google Patents
Info
- Publication number
- JPH0450746B2 JPH0450746B2 JP57033339A JP3333982A JPH0450746B2 JP H0450746 B2 JPH0450746 B2 JP H0450746B2 JP 57033339 A JP57033339 A JP 57033339A JP 3333982 A JP3333982 A JP 3333982A JP H0450746 B2 JPH0450746 B2 JP H0450746B2
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- forming
- crystal semiconductor
- recess
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 57
- 239000013078 crystal Substances 0.000 claims description 38
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- -1 that is Inorganic materials 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は、絶縁性基体上に構成される半導体素
子領域を絶縁分離してなる形式の大容量のMIS電
界効果トランジスタの製造方法に関す。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a large-capacity MIS field effect transistor formed by insulating and separating a semiconductor element region formed on an insulating substrate.
(b) 従来技術と問題点
表面が例えば二酸化シリコン（SiO2）などの
絶縁物よりなる基体上に、非単結晶シリコンすな
わち多結晶シリコンもしくは非晶質シリコンより
なる半導体層を設け、該非単結晶シリコン層を単
結晶化して、SOI（Siicon On Insuator）構
造の半導体素子を形成する半導体装置の製造方法
が既に種々提案されている。(b) Prior art and problems A semiconductor layer made of non-single-crystal silicon, that is, polycrystalline silicon or amorphous silicon, is provided on a substrate whose surface is made of an insulating material such as silicon dioxide (SiO 2 ), and the non-single-crystal Various methods for manufacturing semiconductor devices have already been proposed in which a silicon layer is made into a single crystal to form a semiconductor element having an SOI (Siicon On Insuator) structure.
この種の半導体装置の製造方法において、非単
結晶シリコン層から単結晶半導体領域を形成する
方法としては、通常電子ビームもしくはレーザ光
等のエネルギ線ビームを照射することによつて、
非単結晶シリコンを加熱融解して、再結晶せしめ
ることが行われている。 In the manufacturing method of this type of semiconductor device, a method for forming a single crystal semiconductor region from a non-single crystal silicon layer is usually by irradiating an energy beam such as an electron beam or a laser beam.
Non-single crystal silicon is heated and melted to recrystallize it.
本発明者等が先に特願昭56−155513号によつて
提案した半導体装置の製造方法は、SOI構造の半
導体装置を構成する単結晶半導体領域を形成する
製造方法を提供するものであつて、その概略は次
の通りである。 The method for manufacturing a semiconductor device that the present inventors previously proposed in Japanese Patent Application No. 56-155513 provides a manufacturing method for forming a single crystal semiconductor region constituting a semiconductor device having an SOI structure. , its outline is as follows.
第１図及び第２図は前記提案の一実施例を説明
するための工程要所に於ける半導体装置の要部断
面図であり、次に、これ等の図を参照しつつ説明
する。 FIGS. 1 and 2 are sectional views of essential parts of a semiconductor device at key points in the process for explaining an embodiment of the above-mentioned proposal, and the following description will be made with reference to these figures.
第１図参照
(1) 金属、アルミナ、高純度石英等から適宜選択
した材料からなる基板１に厚さ1が例えば１
〔μm〕のSiO2からなる絶縁物層２を形成する。Refer to Figure 1 (1) A substrate 1 made of a material suitably selected from metal, alumina, high-purity quartz, etc. has a thickness of 1 , for example.
An insulator layer 2 made of SiO 2 of [μm] is formed.
基板１が例えば金属である場合、化学気相成
長法にて非晶質シリコン酸化層を形成して絶縁
物層２としてもよい。 When the substrate 1 is made of metal, for example, an amorphous silicon oxide layer may be formed as the insulating layer 2 by chemical vapor deposition.
(2) フオト・リソグラフイ技術にて、絶縁物層２
のエツチングを行ない凹所３を形成する。この
エツチングはリアクテイブ・イオン・エツチン
グが好ましい。(2) Using photolithography technology, insulator layer 2
A recess 3 is formed by etching. This etching is preferably reactive ion etching.
凹所３の大きさは、例えば30×15〔μm〕、底
部に於ける絶縁物層２の厚さ2は例えば0.1
〔μm〕、凹所３間の幅3は例えば５〔μm〕であ
る。 The size of the recess 3 is, for example, 30×15 [μm], and the thickness 2 of the insulating layer 2 at the bottom is, for example, 0.1
[μm], and the width 3 between the recesses 3 is, for example, 5 [μm].
(3) 前記基板１及び絶縁物層２よりなる基体上に
化学気相成長法にて厚さ4が例えば0.5〜１
〔μm〕である非単結晶シリコン層４を成長させ
る。(3) A thickness 4 of, for example, 0.5 to 1
A non-single crystal silicon layer 4 of [μm] is grown.
(4) 化学気相成長法にて厚さ例えば１〔μm〕程度
の燐硅酸ガラスからなるキヤツプ層５を形成す
る。これは、熱放散を抑止する為のもので、必
須のものではなく、またSiO2、窒化シリコン
（Si3N4）等を用いてもよい。(4) A cap layer 5 made of phosphosilicate glass having a thickness of, for example, about 1 [μm] is formed by chemical vapor deposition. This is for suppressing heat dissipation and is not essential, and SiO 2 , silicon nitride (Si 3 N 4 ), etc. may also be used.
(5) CWアルゴン・レーザをエネルギ17〔Ｗ〕、走
査速度10〔cm／秒〕、スポツト・サイズ50〔μm〕
φの条件で照射し、アニールを行なう。尚、こ
の際、全体を500〔℃〕程度の温度に加熱してお
くものとする。(5) CW argon laser with energy of 17 [W], scanning speed of 10 [cm/s], and spot size of 50 [μm].
Irradiation is performed under the condition of φ to perform annealing. In addition, at this time, the whole shall be heated to a temperature of approximately 500 [°C].
前記レーザ光は非単結晶シリコン層４に良く
吸収されるので非単結晶シリコン層４は融解さ
れ、それが凝結する際に単結晶化する。しか
も、融解したシリコンは全て凹所３内に引込ま
れて単結晶になるので凹所３内にのみ単結晶半
導体領域が形成される。 Since the laser beam is well absorbed by the non-single-crystal silicon layer 4, the non-single-crystal silicon layer 4 is melted, and when it condenses, it becomes a single crystal. Moreover, since all of the melted silicon is drawn into the recess 3 and becomes a single crystal, a single crystal semiconductor region is formed only within the recess 3.
第２図参照
(6) 前記のように、凹所３内に単結晶半導体領域
６Ａ，６Ｂ，６Ｃ……を形成してからキヤツプ
層５を除去する。See FIG. 2 (6) As described above, after forming the single crystal semiconductor regions 6A, 6B, 6C, . . . in the recess 3, the cap layer 5 is removed.
(7) この後、通常の技法にて、半導体領域６Ａ，
６Ｂ……に半導体素子を形成すれば良い。(7) After this, the semiconductor region 6A,
A semiconductor element may be formed on 6B...
ところで、前記工程に於いて、非単結晶シリ
コン層４をレーザ・アニールした際、凹所３内
に融解したシリコンが引込まれてそこに単結晶
シリコンが堆積する理由としては次のように考
えることができる。即ち、二酸化シリコンの熱
伝導率は例えばシリコンと比較すると1/10程度
である為、その熱保特性は極めて高い。しか
し、前記したように凹所３を形成すると、絶縁
物層２の表面と凹所３の底面とでは放熱の度合
がかなり相違し、底面では温度が低くなる。従
つて、前記のようにアニールを行なうと、凹所
３の底面に接している融解したシリコンが先ず
凝結して単結晶シリコン化する過程に於いて絶
縁物層２の表面に在つて未だ融解状態にあるシ
リコンを凹所３に引込んで単結晶化してゆくも
のである。 By the way, in the above process, when the non-single crystal silicon layer 4 is laser annealed, the reason why the molten silicon is drawn into the recess 3 and single crystal silicon is deposited there can be considered as follows. I can do it. That is, since the thermal conductivity of silicon dioxide is about 1/10 that of silicon, for example, its heat retention properties are extremely high. However, when the recess 3 is formed as described above, the degree of heat radiation is considerably different between the surface of the insulating layer 2 and the bottom of the recess 3, and the temperature becomes lower at the bottom. Therefore, when annealing is performed as described above, the molten silicon that is in contact with the bottom surface of the recess 3 first condenses to form single crystal silicon, and the silicon that is present on the surface of the insulating layer 2 remains in a molten state. The silicon present in the silicon is drawn into the recess 3 and becomes a single crystal.
前記のようにして、絶縁物層２の凹所３内を
単結晶シリコンで充満させることは非単結晶シ
リコン層４の膜厚を選択することに依り極めて
容易に実現することができ、これを実験的に確
認することは簡単である。 Filling the recess 3 of the insulator layer 2 with monocrystalline silicon as described above can be achieved extremely easily by selecting the thickness of the non-single crystal silicon layer 4. It is easy to confirm experimentally.
尚、前記実施例では加熱エネルギ源としてレ
ーザ光を使用したが、その他、キセノン・ラン
プやハロゲン・ランプの光を集光して使用する
こともできる。 Although laser light was used as the heating energy source in the above embodiment, it is also possible to use condensed light from a xenon lamp or a halogen lamp.
以上説明した製造方法は通常の場合には良好な
結果が得られる優れた方法であるが、例えば大容
量のMOS電界効果トランジスタ（MOS FET）
などを構成するために、大きい単結晶半導体領域
を形成する場合には、前記凹所３内に形成された
単結晶半導体領域６Ａ等の厚さが、その中央部に
おいて薄くなり、コンタクトマスクを用いて形成
されたパターンの乱れや、不純物拡散の際に半導
体の薄い位置において横方向拡散が大きいなどの
不都合を生ずる。第３図は中央部が薄くなつた単
結晶半導体領域の一例６Ｄを示す断面図、第４図
はMOS FETのゲート電極７のパターン等に乱
れを生じた一例を示す平面図である。 The manufacturing method described above is an excellent method that can usually yield good results.
When forming a large single-crystal semiconductor region 6A, etc., formed in the recess 3, the thickness of the single-crystal semiconductor region 6A, etc. formed in the recess 3 becomes thinner in the center, and a contact mask is used to form a large single-crystal semiconductor region 6A. This results in disadvantages such as disturbances in the pattern formed during impurity diffusion, and large lateral diffusion in thin areas of the semiconductor during impurity diffusion. FIG. 3 is a cross-sectional view showing an example of a single crystal semiconductor region 6D in which the central portion is thinned, and FIG. 4 is a plan view showing an example in which the pattern of the gate electrode 7 of a MOS FET is disturbed.
(c) 発明の目的
本発明は、表面が絶縁物よりなる基体上に設け
られた前記の如き不純物拡散やパターンの乱れが
なく、再現性よく形成される大容量のMIS FET
を含む半導体装置の製造方法を提供することを目
的とする。(c) Object of the Invention The present invention provides a large-capacity MIS FET that is formed on a substrate whose surface is made of an insulating material and is formed with good reproducibility without impurity diffusion or pattern disturbance as described above.
An object of the present invention is to provide a method for manufacturing a semiconductor device including the following.
(d) 発明の構成
本発明の目的は、絶縁性表面を有する基板の該
表面に互いに平行に延在する複数の凹所を形成し
たのち、該表面に非単結晶半導体層を形成し、該
非単結晶半導体層に加熱エネルギー線を照射して
該非単結晶半導体層を融解し再結晶化することに
より該複数の凹所の各々に孤立した単結晶半導体
領域を形成する工程を含む半導体装置の製造方法
であつて、該表面方向における該凹所の寸法を、
該凹所内における該単結晶半導体領域の層厚を均
一に為し得る寸法に設定する工程と、該複数の凹
所を横切つて該複数の単結晶半導体領域上にゲー
ト絶縁膜を介して延在するゲート電極を形成する
工程と、該複数の単結晶半導体領域の各々にソー
スおよびドレインを形成する工程と、各々の該単
結晶半導体領域に形成されたソースおよびドレイ
ンをソース毎およびドレイン毎に共通接続する一
対の配線を形成する工程が含まれてなることを特
徴とする半導体装置の製造方法によつて実現され
る。(d) Structure of the Invention The object of the present invention is to form a plurality of recesses extending parallel to each other on the surface of a substrate having an insulating surface, and then to form a non-single crystal semiconductor layer on the surface. Manufacturing a semiconductor device including the step of forming an isolated single crystal semiconductor region in each of the plurality of recesses by irradiating the single crystal semiconductor layer with heating energy rays to melt and recrystallize the non-single crystal semiconductor layer. The method comprises: determining the dimensions of the recess in the surface direction;
a step of setting the layer thickness of the single crystal semiconductor region in the recess to a size that can be made uniform; and a step of extending the layer across the plurality of recesses onto the plurality of single crystal semiconductor regions via a gate insulating film. a step of forming a gate electrode in each of the plurality of single crystal semiconductor regions, a step of forming a source and a drain in each of the plurality of single crystal semiconductor regions, and a step of forming the source and drain formed in each of the single crystal semiconductor regions for each source and each drain This is achieved by a method for manufacturing a semiconductor device characterized by including a step of forming a pair of interconnects that are commonly connected.
(e) 発明の実施例
以下本発明を実施例により図面を参照して具体
的に説明する。(e) Embodiments of the Invention The present invention will be specifically explained below using embodiments with reference to the drawings.
第５図及び第６図は本発明の一実施例を説明す
るための、単結晶半導体領域形成工程における半
導体装置の要部断面図、第７図は形成された
MOS FETの平面図である。 5 and 6 are cross-sectional views of essential parts of a semiconductor device in a process of forming a single crystal semiconductor region, for explaining one embodiment of the present invention, and FIG. 7 is a cross-sectional view of a semiconductor device formed
FIG. 3 is a plan view of a MOS FET.
第５図参照
(1) 先に述べた従来技術と同様な材料からなる基
板１１に厚さが例えば１〔μm〕のSiO2からな
る絶縁物層１２を形成する。Refer to FIG. 5 (1) An insulating layer 12 made of SiO 2 having a thickness of 1 [μm], for example, is formed on a substrate 11 made of the same material as in the prior art described above.
(2) 絶縁物層１２に凹所１３を形成する。凹所１
３の長辺が40乃至50〔μm〕程度以上となると
き、ここに形成される単結晶半導体領域の中央
部が先に述べた如く薄くなるために、本実施例
においては約25×12〔μm〕とし、底部における
絶縁物層の厚さは約0.1〔μm〕とした。(2) Forming a recess 13 in the insulator layer 12. recess 1
When the long side of 3 is about 40 to 50 [μm] or more, the central part of the single crystal semiconductor region formed there becomes thin as described above, so in this example, it is about 25 × 12 [μm]. μm], and the thickness of the insulating layer at the bottom was approximately 0.1 μm.
(3) 絶縁物層１２上に非単結晶シリコン層１４を
成長させる。なおキヤツプ層は本実施例におい
ては省略している。(3) A non-single crystal silicon layer 14 is grown on the insulator layer 12. Note that the cap layer is omitted in this embodiment.
第６図参照
(4) エネルギ線照射を前記従来技術と同様に実施
して単結晶半導体領域１５Ａ，１５Ｂ，１５
Ｃ，１５Ｄ，……を形成する。先に述べた如く
凹所１３の大きさが選択されているために、そ
の厚さが均一とみなし得る半導体領域１５Ａ等
が得られる。Refer to FIG. 6 (4) Energy beam irradiation is performed in the same manner as in the prior art to form single crystal semiconductor regions 15A, 15B, 15.
C, 15D, . . . are formed. Since the size of the recess 13 is selected as described above, a semiconductor region 15A etc. whose thickness can be considered to be uniform is obtained.
第７図参照
(5) 既に知られている製造方法を応用し、半導体
領域１５Ａ等にMOS FETを形成する。See FIG. 7 (5) Applying a known manufacturing method, MOS FETs are formed in the semiconductor region 15A and the like.
ただし、本実施例においては、ゲート電極１
６は４個よりなる一群の単結晶半導体領域１５
Ａ，１５Ｂ，１５Ｃ，１５Ｄに共通に設けら
れ、該一群の単結晶半導体領域１５Ａ，１５
Ｂ，１５Ｃ，１５Ｄに設けられたソース及びド
レイン１８はそれぞれアルミニウム（Ａ）な
どによる配線１９及び２０によつて並列に接続
されている。 However, in this embodiment, the gate electrode 1
6 is a group of four single crystal semiconductor regions 15;
A, 15B, 15C, and 15D are provided in common, and the group of single crystal semiconductor regions 15A, 15
The sources and drains 18 provided in B, 15C, and 15D are connected in parallel by wirings 19 and 20 made of aluminum (A) or the like, respectively.
以上説明した本発明の製造方法によつて製造さ
れた第７図に示す如き一群のMOS FETは、大
きい単結晶半導体領域に形成されたMOS FET
の如く、先に述べた不都合を生ずることなく、大
容量の単一のMOS FETに相当する動作を与え、
かつ、製造工程中の制御、管理も容易であつて良
い再現性が確保される。 A group of MOS FETs as shown in FIG. 7 manufactured by the manufacturing method of the present invention explained above are MOS FETs formed in a large single crystal semiconductor region.
As shown in FIG.
Moreover, control and management during the manufacturing process is easy and good reproducibility is ensured.
(f) 発明の効果
本発明はSOI構造のMIS FETを、絶縁物層に
設けた凹所に加熱エネルギ線照射によつて堆積さ
れた単結晶半導体領域に形成する半導体装置の製
造方法を発展せしめて、該MIS FETが大容量で
あることが必要である場合に、これを一群の複数
の単結晶半導体領域に形成する半導体装置の製造
方法を提案するものであつて、容易な制御、管理
により良い再現性が得られ、SOI構造、三次元構
造の半導体集積回路等に大きく寄与する。(f) Effects of the Invention The present invention develops a method for manufacturing a semiconductor device in which a MIS FET with an SOI structure is formed in a single crystal semiconductor region deposited in a recess provided in an insulating layer by irradiation with heating energy beams. Therefore, when the MIS FET needs to have a large capacity, we propose a method for manufacturing a semiconductor device in which the MIS FET is formed in a group of multiple single crystal semiconductor regions, and can be easily controlled and managed. It provides good reproducibility and greatly contributes to semiconductor integrated circuits with SOI structures and three-dimensional structures.
第１図乃至第３図は従来技術の実施例の断面
図、第４図は従来技術の実施例の平面図、第５図
及び第６図は本発明の実施例の断面図、第７図は
本発明の実施例の平面図である。
図において、１は基板、２は絶縁物層、３は凹
所、４は非単結晶シリコン層、５はキヤツプ層、
６Ａ，６Ｂ，６Ｃ及び６Ｄは単結晶半導体領域、
７はゲート電極、１１は基板、１２は絶縁物層、
１３は凹所、１４は非単結晶シリコン層、１５
Ａ，１５Ｂ，１５Ｃ及び１５Ｄは単結晶半導体領
域、１６はゲート電極、１７はソース、１８はド
レイン、１９及び２０は配線を示す。
1 to 3 are sectional views of the embodiment of the prior art, FIG. 4 is a plan view of the embodiment of the prior art, FIGS. 5 and 6 are sectional views of the embodiment of the present invention, and FIG. 1 is a plan view of an embodiment of the present invention. In the figure, 1 is a substrate, 2 is an insulating layer, 3 is a recess, 4 is a non-single crystal silicon layer, 5 is a cap layer,
6A, 6B, 6C and 6D are single crystal semiconductor regions,
7 is a gate electrode, 11 is a substrate, 12 is an insulating layer,
13 is a recess, 14 is a non-single crystal silicon layer, 15
A, 15B, 15C and 15D are single crystal semiconductor regions, 16 is a gate electrode, 17 is a source, 18 is a drain, and 19 and 20 are wirings.
Claims (1)
行に延在する複数の凹所を形成したのち、該表面
に非単結晶半導体層を形成し、該非単結晶半導体
層に加熱エネルギー線を照射して該非単結晶半導
体層を融解し再結晶化することにより該複数の凹
所の各々に孤立した単結晶半導体領域を形成する
工程を含む半導体装置の製造方法であつて、 該表面方向における該凹所の寸法を、該凹所内
における該単結晶半導体領域の層厚を均一に為し
得る寸法に設定する工程と、 該複数の凹所を横切つて該複数の単結晶半導体
領域上にゲート絶縁膜を介して延在するゲート電
極を形成する工程と、 該複数の単結晶半導体領域の各々にソースおよ
びドレインを形成する工程と、 各々の該単結晶半導体領域に形成されソースお
よびドレインをソース毎およびドレイン毎に共通
接続する一対の配線を形成する工程 が含まれてなることを特徴とする半導体装置の製
造方法。[Claims] 1. After forming a plurality of recesses extending parallel to each other on the surface of a substrate having an insulating surface, forming a non-single crystal semiconductor layer on the surface, and forming a non-single crystal semiconductor layer on the surface. A method for manufacturing a semiconductor device, comprising a step of forming an isolated single crystal semiconductor region in each of the plurality of recesses by melting and recrystallizing the non-single crystal semiconductor layer by irradiating with a heating energy beam, setting the dimensions of the recess in the surface direction to dimensions that can make the layer thickness of the single crystal semiconductor region uniform within the recess; forming a gate electrode extending over the semiconductor region via a gate insulating film; forming a source and a drain in each of the plurality of single crystal semiconductor regions; 1. A method of manufacturing a semiconductor device, comprising the step of forming a pair of wirings that connect a source and a drain in common for each source and each drain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3333982A JPS58151042A (en) | 1982-03-03 | 1982-03-03 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3333982A JPS58151042A (en) | 1982-03-03 | 1982-03-03 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58151042A JPS58151042A (en) | 1983-09-08 |
| JPH0450746B2 true JPH0450746B2 (en) | 1992-08-17 |
Family
ID=12383803
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3333982A Granted JPS58151042A (en) | 1982-03-03 | 1982-03-03 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58151042A (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4011344B2 (en) | 2001-12-28 | 2007-11-21 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP4387099B2 (en) * | 2001-12-28 | 2009-12-16 | 株式会社半導体エネルギー研究所 | Semiconductor device production method |
| TW200302511A (en) | 2002-01-28 | 2003-08-01 | Semiconductor Energy Lab | Semiconductor device and method of manufacturing the same |
| TWI261358B (en) | 2002-01-28 | 2006-09-01 | Semiconductor Energy Lab | Semiconductor device and method of manufacturing the same |
| US7749818B2 (en) | 2002-01-28 | 2010-07-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
| JP2004006644A (en) * | 2002-01-28 | 2004-01-08 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its fabricating method |
| JP4137460B2 (en) * | 2002-02-08 | 2008-08-20 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP4137461B2 (en) * | 2002-02-08 | 2008-08-20 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| US6906343B2 (en) * | 2002-03-26 | 2005-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
| JP4503246B2 (en) * | 2002-06-25 | 2010-07-14 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5658269A (en) * | 1979-10-17 | 1981-05-21 | Seiko Epson Corp | Mos type semiconductor device |
-
1982
- 1982-03-03 JP JP3333982A patent/JPS58151042A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5658269A (en) * | 1979-10-17 | 1981-05-21 | Seiko Epson Corp | Mos type semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58151042A (en) | 1983-09-08 |
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