JPH0376017B2 - - Google Patents
Info
- Publication number
- JPH0376017B2 JPH0376017B2 JP56111867A JP11186781A JPH0376017B2 JP H0376017 B2 JPH0376017 B2 JP H0376017B2 JP 56111867 A JP56111867 A JP 56111867A JP 11186781 A JP11186781 A JP 11186781A JP H0376017 B2 JPH0376017 B2 JP H0376017B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- single crystal
- semiconductor region
- silicon
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 25
- 239000013078 crystal Substances 0.000 claims description 11
- 238000001953 recrystallisation Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000010408 film Substances 0.000 description 24
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 238000002425 crystallisation Methods 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000001678 irradiating effect Effects 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- -1 that is Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、特に絶縁基板
面上の分離された非単結晶半導体領域をエネルギ
線の照射により単結晶化する方法に関す。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of monocrystalizing a separated non-single crystal semiconductor region on an insulating substrate surface by irradiating an energy beam.
表面が絶縁物よりなる基板上に島状に分離され
た半導体素子を形成するSOI（Silicon on
Insulating Substrate）構造の半導体装置の製造
工程において、絶縁基板面上の非単結晶シリコン
すなわち多結晶シリコン或いは非結晶シリコンに
より形成された島状に分離された薄膜状半導体領
域を単結晶化する熱処理を実施する場合に、特に
対策を講じない限り、各半導体領域の端部がその
中央部分に比較して低温となり、再結晶化は周辺
部分より始まるために多結晶となり易く、単結晶
化の目的を達成するためには各半導体領域の中央
附近の一個所に温度の最低点を設けて、再結晶化
をこの位置より開始させることが必要とされてい
る。 SOI (Silicon on
In the manufacturing process of semiconductor devices with an insulating substrate structure, heat treatment is performed to single-crystallize thin-film semiconductor regions separated into islands formed of non-single-crystal silicon, that is, polycrystalline silicon or amorphous silicon, on the surface of an insulating substrate. Unless special measures are taken, the edges of each semiconductor region will be at a lower temperature than the center, and recrystallization will begin from the periphery, resulting in polycrystalline formation, which will defeat the purpose of single crystallization. In order to achieve this, it is necessary to provide the lowest temperature point at a location near the center of each semiconductor region and to start recrystallization from this location.
本発明は、前記の単結晶化のためのエネルギ線
すなわち波動或いは粒子ビーム照射による熱処理
において、再結晶化を一個所より開始せしめる具
体的でかつ確実な方法を得ることを目的とする。 An object of the present invention is to obtain a specific and reliable method for starting recrystallization from one location in the heat treatment using energy beams, that is, wave or particle beam irradiation for single crystallization.
本発明は、非単結晶半導体領域の一部分と基板
下面との間の熱抵抗を、非単結晶半導体領域の他
の部分と基板下面との間の熱抵抗より小ならしめ
て、エネルギ線の照射後結晶化温度に最初に到達
する位置を各半導体領域内に、通常は中央附近に
設定することにより達成される。 The present invention makes the thermal resistance between a part of the non-single crystal semiconductor region and the lower surface of the substrate smaller than the thermal resistance between the other part of the non-single crystal semiconductor region and the lower surface of the substrate, and This is achieved by setting the location within each semiconductor region where the crystallization temperature first is reached, usually near the center.
以下本発明を実施例により図面を用いて詳細に
説明する。第１図ａ及びｂは第一の実施例を示す
平面図及び断面図である。本実施例においてはシ
リコン基板１の表面に二酸化シリコン（SiO2）
よりなる絶縁膜２を熱酸化法により形成するにあ
たり、予め基板１上に窒化シリコン（Si3N4）等
よりなるマスクを配設することにより、各半導体
領域形成位置に一個所づつ、2μｍ×2μｍ程度の
面積を有する酸化を阻止された部分３を設けて厚
さ約1μｍの二酸化シリコン膜を形成し、次いで
前記マスクを除去して更に酸化を行ない、先の酸
化を阻止された部分３において厚さ50nｍの二酸
化シリコン膜４を形成した。これが本発明の特徴
とする絶縁基板の一例である。なお二酸化シリコ
ン膜４に代えて、窒素シリコン膜等を形成しても
よい。 The present invention will be explained in detail below using examples and drawings. Figures 1a and 1b are a plan view and a sectional view showing a first embodiment. In this embodiment, silicon dioxide (SiO 2 ) is deposited on the surface of the silicon substrate 1.
When forming the insulating film 2 by thermal oxidation, a mask made of silicon nitride (Si 3 N 4 ) or the like is placed on the substrate 1 in advance to form a 2 μm×2 insulating film 2 at each semiconductor region formation position. A silicon dioxide film with a thickness of about 1 μm is formed by providing a portion 3 where oxidation is prevented and having an area of about 2 μm, and then the mask is removed and further oxidation is performed. A silicon dioxide film 4 with a thickness of 50 nm was formed. This is an example of an insulating substrate that is a feature of the present invention. Note that instead of the silicon dioxide film 4, a nitrogen silicon film or the like may be formed.
以上の如き絶縁基板上に化学蒸着法等により非
単結晶シリコン層を厚さ約400nｍに形成し、島
状に分離された非単結晶シリコン領域５を形成す
べき部分に窒化シリコンよりなるマスクを用いて
熱酸化処理を行なう。この熱酸化処理は隣接する
領域との中間の部分の非単結晶シリコン層が完全
に酸化されるまで行ない、分離された非単結晶シ
リコン領域５を形成する。 A non-single-crystal silicon layer is formed to a thickness of about 400 nm on the insulating substrate as described above by chemical vapor deposition, etc., and a mask made of silicon nitride is applied to the portions where the island-shaped non-single-crystal silicon regions 5 are to be formed. Thermal oxidation treatment is performed using This thermal oxidation treatment is performed until the non-single-crystal silicon layer in the intermediate portion between adjacent regions is completely oxidized, thereby forming isolated non-single-crystal silicon regions 5.
この基板をレーザ光等の波動或いは電子その他
の粒子ビームを照射することにより加熱して非単
結晶シリコン領域５を融解温度以上とし、主とし
て基板側より冷却する。このとき、非単結晶シリ
コン領域５より基板１への熱伝導は二酸化シリコ
ン膜２及び４を介して行なわれるが、二酸化シリ
コンの熱比抵抗はシリコンに比較して大略10倍程
度であるために、二酸化シリコン膜厚の薄い第一
の酸化を阻止された部分３に対応する位置が非単
結晶シリコン領域５内で最も低温となり、この位
置が最初に再結晶温度に到達して再結晶化はこの
位置より始まり次第に周囲に拡がるために単結晶
を得る。 This substrate is heated by irradiating waves such as laser light or particle beams such as electrons to bring the non-single-crystal silicon region 5 to a melting temperature or higher, and the substrate is cooled mainly from the substrate side. At this time, heat conduction from the non-single crystal silicon region 5 to the substrate 1 is carried out via the silicon dioxide films 2 and 4, but since the thermal resistivity of silicon dioxide is about 10 times that of silicon, , the position corresponding to the first oxidation-blocked portion 3 where the silicon dioxide film is thin becomes the lowest temperature in the non-single crystal silicon region 5, and this position reaches the recrystallization temperature first, and recrystallization does not occur. Starting from this position and gradually expanding to the surroundings, a single crystal is obtained.
以上の如く形成された島状に分離された単結晶
シリコン領域が配設された基板面上にＮ−MOS
電界効果トランジスタ（Ｎ−MOS FET）を形
成した実施例を第１図ｃ及びｄに示す。第１図ｃ
は平面図であつて、ゲート電極６、ソース領域
７、ドレイン領域８、及びゲート電極６への配線
９、ソース領域７への配線１０、ドレイン領域８
への配線１１及び各配線のコンタクトのための層
間絶縁膜の開口及び第一の酸化を阻止された部分
３のみを示し、第１図ｄは第１図ｃのＡ−Ａ断面
図である。 N-MOS
An embodiment in which a field effect transistor (N-MOS FET) is formed is shown in FIGS. 1c and 1d. Figure 1c
is a plan view showing a gate electrode 6, a source region 7, a drain region 8, a wiring 9 to the gate electrode 6, a wiring 10 to the source region 7, and a drain region 8.
FIG. 1d is a cross-sectional view taken along the line AA in FIG. 1c, showing only the openings in the interlayer insulating film for contacting the wirings 11 and the respective wirings, and the portion 3 where the first oxidation is prevented.
第１図ａ乃至ｄに示した実施例においては第一
の酸化を阻止された部分３はＮ−MOSFETのソ
ース領域７の下に位置したが、半導体素子の形成
に際して、絶縁膜の薄い第一の酸化を阻止された
部分３の直上を避けることも可能である。即ち第
２図ａに示す如く、第１図ｂに示した第一の実施
例と同様に基板２１の表面に絶縁膜２２及び絶縁
膜の薄い部分２３を形成後、非単結晶シリコン層
を形成し、パターニングを行つて島状に分離され
た非単結晶シリコン領域を得、次いでレーザ光等
の波動或いは電子その他の粒子ビームを照射する
ことにより加熱して非単結晶シリコン領域融解
し、これを冷却するとき絶縁膜の薄い部分２３の
効果により単結晶シリコン領域２４を得る。この
単結晶シリコン領域２４の上面の絶縁膜の薄い部
分２３の真上を避けた適当な部分に窒化シリコン
等によるマスク２５を形成して熱酸化することに
より、前記単結晶シリコン領域２４のうち、絶縁
膜の薄い部分２３を含むマスク２５の被覆しない
部分は酸化され、新たな単結晶シリコン領域２６
を得る。或いは、前記マスク２５に代つてホトリ
ソグラフイ用マスク２５′を形成し、絶縁膜の薄
い部分２３の真上部等を選択的に除去して新たな
単結晶シリコン領域を得る。 In the embodiment shown in FIGS. 1a to 1d, the first oxidation-blocked portion 3 is located under the source region 7 of the N-MOSFET. It is also possible to avoid directly above the portion 3 where the oxidation of the oxidation is prevented. That is, as shown in FIG. 2a, after forming an insulating film 22 and a thin part 23 of the insulating film on the surface of a substrate 21, a non-monocrystalline silicon layer is formed as in the first embodiment shown in FIG. 1b. Then, patterning is performed to obtain non-single-crystal silicon regions separated into islands, and then heated by irradiation with waves such as laser light or electron or other particle beams to melt the non-single-crystal silicon regions. During cooling, a single crystal silicon region 24 is obtained due to the effect of the thin portion 23 of the insulating film. A mask 25 made of silicon nitride or the like is formed on an appropriate portion of the upper surface of the single crystal silicon region 24, avoiding directly above the thin portion 23 of the insulating film, and thermal oxidation is performed to form a mask 25 on the upper surface of the single crystal silicon region 24. The uncovered portions of the mask 25, including the thin portions 23 of the insulating film, are oxidized to form new single crystal silicon regions 26.
get. Alternatively, a photolithography mask 25' is formed in place of the mask 25, and a portion directly above the thin portion 23 of the insulating film is selectively removed to obtain a new single crystal silicon region.
以上の実施例においては、基板をシリコン、基
板上の絶縁膜を二酸化シリコンとしたが、基板及
び絶縁膜を形成する物質は前記例に限定されるも
のではなく、基板を形成する物質の熱化抵抗が絶
縁膜を形成する物質の熱比抵抗より小となる組合
せを選択し、単結晶化する領域のうち、再結晶化
を開始した11点の下部において絶縁膜を薄くすれ
ばよい。 In the above embodiments, the substrate is silicon and the insulating film on the substrate is silicon dioxide, but the materials forming the substrate and the insulating film are not limited to the above examples, and thermalization of the material forming the substrate It is sufficient to select a combination in which the resistance is smaller than the thermal specific resistance of the substance forming the insulating film, and to thin the insulating film below the 11 points where recrystallization has started in the region to be single-crystallized.
更に熱抵抗の小なる部分を形成する他の方法と
しては、基板より熱比抵抗が小である物質、例え
ばモリブデン（Mo）による点状パターンをシリ
コン基板上に配設し、しかる後に化学蒸着法等に
より絶縁膜を形成すれば、点状パターンが埋設さ
れた位置は熱抵抗が低くなる。 Another method for forming a portion with even lower thermal resistance is to arrange a dot-like pattern on a silicon substrate using a material whose thermal resistivity is lower than that of the substrate, such as molybdenum (Mo), and then apply a chemical vapor deposition method. If an insulating film is formed by the above method, the thermal resistance will be lowered at the position where the dotted pattern is buried.
また、基板が半導体、例えばシリコンよりなり
その比抵抗が20ohm−cmであるとき、放熱路を配
設する位置のみに選択的に多量のイオン注入を行
ない、例えば砒素イオン（As+）濃度を４×
1021／cm3程度とする。このとき電気抵抗とともに
この位置の熱抵抗もイオン注入しない領域に比較
して相対的に低下する。 Furthermore, when the substrate is made of a semiconductor, for example silicon, and its resistivity is 20 ohm-cm, a large amount of ions are selectively implanted only in the position where the heat dissipation path is to be provided, for example, the arsenic ion (As + ) concentration is increased to 40 ohm-cm. ×
It should be about 10 21 /cm 3 . At this time, not only the electrical resistance but also the thermal resistance at this position is relatively reduced compared to the region where ions are not implanted.
本発明は以上説明した如く、SOI構造の半導体
装置の製造工程において、絶縁基板上の非単結晶
シリコンにより形成された半導体領域をエネルギ
線すなわち波動或いは粒子ビーム照射により加熱
融解し再結晶せしめて単結晶化するに際し、半導
体領域の一部分と基板下面との間の熱抵抗を、半
導体領域の他の部分と基板下面との間の熱抵抗よ
り小とすることにより、半導体領域内に設定され
た一点が最初に再結晶温度に到達してこの点より
再結晶化が開始されることにより単結晶化を確実
ならしめる効果を有する。 As explained above, in the manufacturing process of a semiconductor device having an SOI structure, the present invention heats and melts a semiconductor region formed of non-single crystal silicon on an insulating substrate by irradiating it with an energy beam, that is, a wave or a particle beam, and recrystallizes it into a single crystal. When crystallizing, the thermal resistance between a part of the semiconductor region and the bottom surface of the substrate is made smaller than the thermal resistance between the other part of the semiconductor region and the bottom surface of the substrate, so that a single point is set in the semiconductor region. reaches the recrystallization temperature first, and recrystallization starts from this point, which has the effect of ensuring single crystallization.
第１図ａ及びｃは本発明の実施例を示す要部平
面図、第１図ｂ及びｄはそれぞれ第１図ａ或いは
ｃに対応する断面図であり、第２図ａ及びｂは他
の実施例を示す断面図である。
図において、１は基板、２は絶縁膜、３は第一
の酸化を阻止された部分、４は絶縁膜、５はシリ
コン領域、６はゲート電極、７はソース領域、８
はドレイン領域、９は配線、１０は配線、１１は
配線、２１は基板、２２は絶縁膜、２３は絶縁膜
の薄い部分、２４はシリコン領域、２５はマス
ク、２６はシリコン領域を示す。
Figures 1a and 1c are plan views of essential parts showing an embodiment of the present invention, Figures 1b and d are sectional views corresponding to Figure 1a or c, respectively, and Figures 2a and b are sectional views of other parts. It is a sectional view showing an example. In the figure, 1 is a substrate, 2 is an insulating film, 3 is a portion where the first oxidation is prevented, 4 is an insulating film, 5 is a silicon region, 6 is a gate electrode, 7 is a source region, and 8
1 is a drain region, 9 is a wiring, 10 is a wiring, 11 is a wiring, 21 is a substrate, 22 is an insulating film, 23 is a thin part of the insulating film, 24 is a silicon region, 25 is a mask, and 26 is a silicon region.
Claims (1)
晶半導体領域を配設し、エネルギ線の照射により
該非単結晶半導体領域を単結晶半導体領域に変換
し、該単結晶半導体領域に半導体素子を形成する
半導体装置の製造方法において、１個の該非単結
晶半導体領域の周縁から離隔した単一部分と該基
板下面との間の熱抵抗を、該非単結晶半導体領域
の他の部分と該基板下面との間の熱抵抗より小な
らしめて、該エネルギ線照射を行い、該単一部分
において最初に再結晶化を開始せしめることを特
徴とする半導体装置の製造方法。1. An island-shaped non-single crystal semiconductor region is provided on an insulating film formed on a substrate, the non-single crystal semiconductor region is converted into a single crystal semiconductor region by irradiation with an energy beam, and a semiconductor is formed in the single crystal semiconductor region. In a method of manufacturing a semiconductor device forming an element, the thermal resistance between a single portion spaced apart from the periphery of one non-single crystal semiconductor region and the bottom surface of the substrate is determined by comparing the thermal resistance between another portion of the non-single crystal semiconductor region and the substrate. A method for manufacturing a semiconductor device, characterized in that the energy beam irradiation is performed while the thermal resistance is made smaller than the thermal resistance between the lower surface and the single portion, and recrystallization is started first in the single portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11186781A JPS5814525A (en) | 1981-07-17 | 1981-07-17 | Manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11186781A JPS5814525A (en) | 1981-07-17 | 1981-07-17 | Manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5814525A JPS5814525A (en) | 1983-01-27 |
| JPH0376017B2 true JPH0376017B2 (en) | 1991-12-04 |
Family
ID=14572149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11186781A Granted JPS5814525A (en) | 1981-07-17 | 1981-07-17 | Manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5814525A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59147425A (en) * | 1983-02-10 | 1984-08-23 | Seiko Instr & Electronics Ltd | Formation of semiconductor crystal film |
| JPS6017911A (en) * | 1983-07-11 | 1985-01-29 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
| JPS60210833A (en) * | 1984-04-05 | 1985-10-23 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
| JPH0656014B2 (en) * | 1984-09-22 | 1994-07-27 | 輝夫 小井 | How to build foundation piles |
-
1981
- 1981-07-17 JP JP11186781A patent/JPS5814525A/en active Granted
Non-Patent Citations (1)
| Title |
|---|
| APPL PHYS LETT * |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5814525A (en) | 1983-01-27 |
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