JPS5837916A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5837916A
JPS5837916A JP56136676A JP13667681A JPS5837916A JP S5837916 A JPS5837916 A JP S5837916A JP 56136676 A JP56136676 A JP 56136676A JP 13667681 A JP13667681 A JP 13667681A JP S5837916 A JPS5837916 A JP S5837916A
Authority
JP
Japan
Prior art keywords
film
crystal silicon
substrate
silicon film
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56136676A
Other languages
Japanese (ja)
Inventor
Junji Sakurai
桜井　潤治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56136676A priority Critical patent/JPS5837916A/en
Publication of JPS5837916A publication Critical patent/JPS5837916A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain an even, non-defect (i.e., with no breakaway, etc.) SOI structure having the desired crystal direction by patterning a non-singlecrystal Si film into an island including the parts in contact with the substrate and single- crystallizing the island by means of the energy beam irradiation. CONSTITUTION:On a singlecrystal Si substrare 11 an insulating film 12 such as an SiO2 film is selectively formed and a polycrystalline Si film 13 is formed on the entire surface of the substrate. The crystal direction of the substrate 11 must be the same as that of a single crystal Si region to be formed. Then, on the polycrystalline Si film 13 are formed, as a covering layer, an Si3N4 film 14 and a PSG film 15, etc. The non-singlecrystal Si film 13 on the insulating film 12 is patterned so that it forms an island that includes the parts in contact with the substrate, and the polycrystalline Si film 13 is converted to a singlecrystal Si film by subjecting it to the energy beam irradiation.

Description

【発明の詳細な説明】 本発明はＳ　ＯＩ　（５ｉｌｉｃｏｎ　ｏｎ　Ｉｎａｕ
Ｉｊａｔｉｎｇ　Ｓｕ　−ｂｓｔｒａｔｅ　）構造の半
導体装置の製造方法に関す。DETAILED DESCRIPTION OF THE INVENTION The present invention is based on S OI
The present invention relates to a method of manufacturing a semiconductor device having a structure of

基板上に絶縁膜を設け、該絶縁膜上に島状に分離された
半導体素子を形成するＳＯＩ構造の半導体装置の製造方
法において、半導体素子を形成する単結晶シリコン領域
を形成するために、化学蒸着法によって形成した非単結
晶シリコン領域を、レーザ光或いは電子線ビーム等のエ
ネルギ綜照射によって一旦融解して結晶化せしめ単結晶
シリコンとすることが一般に知られている。In a method for manufacturing a semiconductor device with an SOI structure in which an insulating film is provided on a substrate and semiconductor elements separated into islands are formed on the insulating film, chemical It is generally known that a non-single-crystal silicon region formed by vapor deposition is once melted and crystallized by energy irradiation such as a laser beam or an electron beam to form single-crystal silicon.

しかしながら、本製造方法において以下に述べる如く三
つの問題点がある。However, this manufacturing method has three problems as described below.

第一の問題点として、前記絶縁膜が二酸化シリコン（５
ｉＯｚ）により形成されている場合に、融解状態のシリ
コンと二酸化シリコン面との濡れの悪さ又は、融解シリ
コンの底面張力から杏結晶したシリコンは液滴状の形状
となり、或いはその上に面に凹凸を生ずる傾向をもち、
半導体素子形成の障害と麦る。The first problem is that the insulating film is silicon dioxide (5
(iOz), the apricot crystallized silicon becomes droplet-like due to poor wetting between the molten silicon and the silicon dioxide surface or the bottom surface tension of the molten silicon, or there are irregularities on the surface. have a tendency to cause
It is considered an obstacle in the formation of semiconductor devices.

第二の問題点として、第一の問題点と同一の理由によシ
、前記エネルギ線照射によシ形成された単結ムシリコン
領域と前記絶縁膜との付着力が不光分であり、単結晶シ
リコン領域の縁端部等において絶縁膜からの剥離を生ず
ることがある０又、第三の問題点として前記の方法によ
って形成される単結晶シリコンを所定の結晶方位とする
制御がある。The second problem, for the same reason as the first problem, is that the adhesion force between the monocrystalline silicon region formed by the energy beam irradiation and the insulating film is opaque. Peeling from the insulating film may occur at the edges of the silicon region.A third problem involves controlling the single crystal silicon formed by the above method to have a predetermined crystal orientation.

前記第−及び第二の問題点の対策として、第１図に断面
図を示す如く、二酸化クリコンよりなる絶縁Ｍｌ上に多
結晶シリコン膜２ｔｌ−形成後、窒化シリコｙ（−８ｉ
ｓＮａ）もしくは二酸化シリコン又はこれらを積層した
被覆層３を形成し、被覆層３及び多結晶シリコン膜２を
選択的に除去し多結晶シリコン領域を形成して、前記エ
ネルギ線照射を実施する方法かある。本方法によれば、
前記第−及び第二の問題点は解決されるが、第三の問題
点である結晶方位の制御は不可能である。As a countermeasure for the above-mentioned first and second problems, as shown in the cross-sectional view in FIG.
sNa) or silicon dioxide, or a coating layer 3 in which these are laminated, selectively removing the coating layer 3 and the polycrystalline silicon film 2 to form a polycrystalline silicon region, and performing the energy beam irradiation. be. According to this method,
Although the first and second problems mentioned above are solved, the third problem, which is the control of crystal orientation, is not possible.

第三の問題点の対策として、更に前記方法を加えて、第
２図に断面図を示す如く、求める単結晶シリコン領域の
結晶方位と同一の結晶方位を有する単結晶シリコン基板
４上に選択的に二酸化シリコンよシなるパッド５を形成
し、次いで多結晶シリコン膜６及び前記方法と同様な１
１４！１層７を形成後前記エネルギ線照射を実施する方
法が塾る。本方決によれば多結晶シリコン膜６の融解後
の結晶化は単結晶シリコン基板４との接触部を核として
エピタキシャルに進行するために前記第三の問題点は解
決される。また被覆層７の効果として、形成された単結
晶シリコン領域の中央部の上表面は平担であって、第一
の問題点も解決されている。As a countermeasure for the third problem, the above-mentioned method is further added, and as shown in the cross-sectional view of FIG. A pad 5 made of silicon dioxide is formed on the surface, followed by a polycrystalline silicon film 6 and a pad 5 made of silicon dioxide.
14! A method of performing the energy beam irradiation after forming the first layer 7 is taught. According to this solution, the third problem is solved because the crystallization of the polycrystalline silicon film 6 after melting progresses epitaxially using the contact portion with the single crystal silicon substrate 4 as a nucleus. Further, as an effect of the covering layer 7, the upper surface of the central portion of the formed single crystal silicon region is flat, and the first problem is also solved.

しかしながら、パッド５の縁端部近傍等において、単結
晶シリコン領域がパッド５からの剥離を生ずる傾向があ
り、前記第二の問題点を残している。However, the single-crystal silicon region tends to peel off from the pad 5 near the edge of the pad 5, leaving the second problem.

本発明は５ｏＩＩＩ造の半導体装置形成のための単結晶
シリコン領域を、エネルギ線照射によって非単結晶領域
から形成する、前記三つの問題点全解決した製造方法を
得ることを目的とする。The object of the present invention is to provide a manufacturing method that solves all of the above three problems, in which a single crystal silicon region for forming a 5oIII semiconductor device is formed from a non-single crystal region by irradiation with energy beams.

本発明の前記目的は、求める単結晶シリコン領域の結晶
方位と同一の結晶方位を有する単結晶シリコン基板上に
選択的に二酸化シリコンよシなるパッドを形成し、次い
で非単結晶シリコン膜及び高耐熱絶縁物よりなる被覆層
を形成後、ノクツド外周の非単結晶シリコン展が基板に
接触する部分を含む島状に分離した形状に被覆層及び非
単結晶シリコン膜をパターニングし、しかる後にエネル
ギ線照射を実施することにより達成される。The object of the present invention is to selectively form a pad made of silicon dioxide on a single crystal silicon substrate having the same crystal orientation as that of a desired single crystal silicon region, and then form a non-single crystal silicon film and a high heat resistant pad. After forming the covering layer made of an insulator, the covering layer and the non-single crystal silicon film are patterned into island-like shapes including the part where the non-single crystal silicon around the outer periphery of the nodule contacts the substrate, and then irradiated with energy beams. This is achieved by implementing the following.

以下に本発明を実施例によ）第３図（ａ）及び（ｂ）を
参照して、具体的に説明する。The present invention will be specifically described below by way of example with reference to FIGS. 3(a) and 3(b).

１Ｍ３図（ａ）は本発明の実施例のエネルギ線照射前の
状態を示す断面図である。１１は単結晶シリコン基板で
あって、その結晶方位蝶形成せんとする単結晶シリコン
領域に求める結晶方位と同一である。この基板１１上の
単結晶シリコン領域を形成せんとする位置に選択的に熱
酸化法により厚さ０６乃至１μｍ程度の二酸化シリコン
よ勺なるパッド１２を形成する。次いで基板全面にモノ
シラン（５ｉＨ４）の熱分解による化学蒸着法により厚
さ０．３乃至０５μｆｎ程度に多結晶シリコン膜１３を
成長せしめる。FIG. 1M3 (a) is a cross-sectional view showing the state of the embodiment of the present invention before energy beam irradiation. Reference numeral 11 denotes a single-crystal silicon substrate whose crystal orientation is the same as the crystal orientation required for the single-crystal silicon region in which the butterfly formation is to be performed. Pads 12 made of silicon dioxide and having a thickness of about 0.6 to 1 μm are selectively formed on the substrate 11 at positions where single-crystal silicon regions are to be formed by thermal oxidation. Next, a polycrystalline silicon film 13 is grown on the entire surface of the substrate to a thickness of approximately 0.3 to 05 μfn by chemical vapor deposition using thermal decomposition of monosilane (5iH4).

更に被覆層として、化学蒸着法によって厚さ５０ｎｍ程
度の窒化シリーン膜１４及び厚さ１μｍＳ度のＰ　Ｓ　
Ｇ　（Ｐｈｏｓｐｈｏ　−８ｉｌｉｃａｔｅ　ＧＡ！ａ
ｓｓ）膜１５を形成する。この被覆層は二酸化シリコン
膜によりて形成しても同等の効果が得られる。Further, as a covering layer, a silicon nitride film 14 with a thickness of about 50 nm and a P S film with a thickness of 1 μm S are formed by chemical vapor deposition.
G (Phospho-8ilicate GA!a
ss) forming a film 15; The same effect can be obtained even if this covering layer is formed of a silicon dioxide film.

次いで第３図（ａ）に示す如く、ノ（ラド１２の外周の
非単結晶シリコン膜１３が基板１１に＋灸触−ｒる部分
を含む島状に分離した形状に）くターニングを行なう。Next, as shown in FIG. 3(a), turning is performed so that the non-single-crystal silicon film 13 on the outer periphery of the rad 12 is separated into island shapes including the portions in contact with the substrate 11.

このバターニングを行った基板に、例えば１０Ｗ連続波
アルゴン（Ａｔ）レーザ光をビーム直径５０μｍ、５０
１オーツ（ラップとして１０ｃｍ／ｓｅｅの速度で走査
照射することにより、多結晶シ１ノコン膜１３を単結晶
とする０ここに得られた単奔吉晶領域は、その結晶方位
は基板と同一であり、）くット°１２との間の剥離等の
障害はなく、ノくツ）”　１２　ｄＥ斜′ｌ￥ｌｊとな
っている周辺部分を除いたその中央部分は平担である。For example, a 10W continuous wave argon (At) laser beam is applied to the patterned substrate with a beam diameter of 50μm and a 50%
The polycrystalline silicon film 13 is made into a single crystal by scanning irradiation at a speed of 10 cm/see as a wrap.The single crystalline region obtained here has the same crystal orientation as the substrate. There is no problem such as peeling between the 12 dE and the center part is flat except for the periphery where the 12 dE is oblique.

前記の方法によって得られた単結晶領域にＭＯ８型電界
効果トランジスタを形成した実施例を第３図（ｂ）に示
す。図において、１６はフィールド°酸イヒ膜、１７は
ゲート酸化膜、１８はゲート、１９はソース領域、２０
はドレイン領域、２１はＰＳＧ膜、２２は配線ノ；ター
ンである。なお本実施例のフィールド酸化膜１６形成に
際して、２化シリコン膜１４をＰＳＧ膜１５除去後にバ
ターニングを行ってマスクとした。FIG. 3(b) shows an example in which an MO8 field effect transistor was formed in the single crystal region obtained by the above method. In the figure, 16 is a field oxide film, 17 is a gate oxide film, 18 is a gate, 19 is a source region, and 20 is a gate oxide film.
21 is a drain region, 21 is a PSG film, and 22 is a wiring turn. In forming the field oxide film 16 of this embodiment, the silicon dioxide film 14 was patterned after removing the PSG film 15 and used as a mask.

本発明は以上説明した如く、単結晶シリコン基板上にパ
ッドを形成し、非単結晶シリコン膜及び被覆層を形成し
た後に、非単結晶シリコン膜が基板に接触する部分を含
む島状に被覆層及び非単結晶シリコン膜をバターニング
し、しかる後にエネルギ約照射による加熱を実施するこ
とによυ、基板にエピタキシャルな単結銘シリコンより
なる、平担な形状でかつ剥離尋の障害のない領域を得る
製造方法を与えるものであって、ＳＯ工構造の半導体装
置の曇、４造方法として大きい効果を有する０As described above, the present invention forms a pad on a single-crystal silicon substrate, forms a non-single-crystal silicon film and a covering layer, and then forms an island-shaped covering layer including a portion where the non-single-crystal silicon film contacts the substrate. By buttering the non-single-crystal silicon film and then heating it by irradiating it with energy, the substrate is made of epitaxial single crystal silicon, with a flat shape and no peeling problem. The present invention provides a manufacturing method for manufacturing semiconductor devices with SO structure, which has a great effect as a manufacturing method.

【図面の簡単な説明】[Brief explanation of drawings]

第１し；及び第２図は従来技前による笑施例の断面図、
第３図（ａ）及び（ｂ）は本発Ｗ１の実施例の断面図で
ある。 図において、１は絶縁膜、２は多結晶シリコン展、３は
被榎層、４Ｆｉ基板、５はパッド、６は多結晶シリコン
膜、７は被覆層、１１は基板、１２はパッド、１３は多
結晶シリコン膜、１４は＆（ヒシリコン膜、１５はＰＳ
Ｇ膜、１６はフィールド酸化膜、１７はゲート酸化膜、
１８はゲート、１９はソース領域、２０はドレイン領域
、２１はＰＳＧ膜、２２は配線）ζターンを示す。Figures 1 and 2 are cross-sectional views of a conventional example;
FIGS. 3(a) and 3(b) are cross-sectional views of an embodiment of the present invention W1. In the figure, 1 is an insulating film, 2 is a polycrystalline silicon layer, 3 is an exposed layer, 4 is a Fi substrate, 5 is a pad, 6 is a polycrystalline silicon film, 7 is a covering layer, 11 is a substrate, 12 is a pad, and 13 is a Polycrystalline silicon film, 14 &(hysilicon film, 15 PS
G film, 16 is a field oxide film, 17 is a gate oxide film,
18 is a gate, 19 is a source region, 20 is a drain region, 21 is a PSG film, and 22 is a wiring) ζ turn.

Claims (1)

【特許請求の範囲】[Claims] 単結晶シリコン基板上に絶縁膜及び非単結晶シリコン膜
を順次形成し、エネルギ線の照射によシ核非単結晶シリ
コン膜を単結晶シリコン膜に変換し、該単結晶シリコン
膜に半導体回路素子を形成する半導体装置の製造方法に
おいて、前記絶縁膜を選択的に形成し、前記非単結晶シ
リコン膜を被後する第二の絶縁層を形成後、該第二の絶
縁層及び該非単結晶シリコン膜を、該非単結晶シリコン
膜が前記基板に接触する部分を含む島状にパターニング
を実施し、しかる後に前記エネルギ線の照射を実施する
ことを特徴とする半導体装置の製造方法。An insulating film and a non-single-crystal silicon film are sequentially formed on a single-crystal silicon substrate, the non-single-crystal silicon film is converted into a single-crystal silicon film by irradiation with energy beams, and a semiconductor circuit element is formed on the single-crystal silicon film. In the method of manufacturing a semiconductor device in which the insulating film is selectively formed and a second insulating layer covering the non-single crystal silicon film is formed, the second insulating layer and the non-single crystal silicon film are formed. A method for manufacturing a semiconductor device, comprising patterning a film into an island shape including a portion where the non-single crystal silicon film contacts the substrate, and then irradiating the film with the energy beam.
JP56136676A 1981-08-31 1981-08-31 Manufacture of semiconductor device Pending JPS5837916A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56136676A JPS5837916A (en) 1981-08-31 1981-08-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56136676A JPS5837916A (en) 1981-08-31 1981-08-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5837916A true JPS5837916A (en) 1983-03-05

Family

ID=15180865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56136676A Pending JPS5837916A (en) 1981-08-31 1981-08-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5837916A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607123A (en) * 1983-06-24 1985-01-14 Nec Corp Photo heating method
US5555621A (en) * 1993-03-11 1996-09-17 Calsonic Corporation Method of producing a catalytic converter

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5687317A (en) * 1979-12-19 1981-07-15 Hitachi Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5687317A (en) * 1979-12-19 1981-07-15 Hitachi Ltd Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607123A (en) * 1983-06-24 1985-01-14 Nec Corp Photo heating method
US5555621A (en) * 1993-03-11 1996-09-17 Calsonic Corporation Method of producing a catalytic converter

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