JPH0582733B2 - - Google Patents
Info
- Publication number
- JPH0582733B2 JPH0582733B2 JP59188444A JP18844484A JPH0582733B2 JP H0582733 B2 JPH0582733 B2 JP H0582733B2 JP 59188444 A JP59188444 A JP 59188444A JP 18844484 A JP18844484 A JP 18844484A JP H0582733 B2 JPH0582733 B2 JP H0582733B2
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- film
- silicon oxide
- single crystal
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000013078 crystal Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000000926 separation method Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000010899 nucleation Methods 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 3
- 238000009751 slip forming Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 31
- 229920005591 polysilicon Polymers 0.000 description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 19
- 229910052814 silicon oxide Inorganic materials 0.000 description 19
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 208000001490 Dengue Diseases 0.000 description 1
- 206010012310 Dengue fever Diseases 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 208000025729 dengue disease Diseases 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02598—Microstructure monocrystalline
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法であつて、特に
ラテラルシーデング法を用いてSOI（Silicon on
Insulater）の形成に関するものである。[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, in particular SOI (Silicon on
This relates to the formation of the insulator.
最近、半導体装置の集積化の増大を計るため
に、素子の微細化や三次元構造化した半導体素子
の開発が盛んに進められている。 Recently, in order to increase the integration of semiconductor devices, the development of semiconductor elements with miniaturization of elements and three-dimensional structures has been actively promoted.
これらの要望に応えて半導体装置のラテラルシ
ーデング法によるSOIの形成方法が開発されてお
り、これは半導体基板の素子の分離や、又三次元
の半導体集積回路を製造する際には極めて重要な
製造方法である。 In response to these demands, a method for forming SOI using the lateral seeding method for semiconductor devices has been developed, which is extremely important for separating elements on semiconductor substrates and manufacturing three-dimensional semiconductor integrated circuits. This is the manufacturing method.
ラテラルシーデング法とは、エネルギー線の照
射によつて単結晶シリコン基板上に部分的に形成
された酸化シリコン膜上の非単結晶シリコン膜
を、単結晶シリコン基板が露出したシリコン単結
晶からエピタキシヤル成長を行つて、酸化シリコ
ン膜上のポリシリコンを単結晶化するものであ
る。このようなラテラルシーデング法によるSOI
の形成方法における問題点として、エネルギー線
を非単結晶シリコン膜に与えてエピタキシヤル成
長をさせる際に、シード部分である単結晶シリコ
ンと接している非単結晶シリコンが溶融しにく
く、一方同様にエネルギー線で走査される酸化シ
リコン膜上の非単結晶シリコンは容易に溶融する
という現象があり、この溶融の不均一が原因とな
つて、酸化シリコン膜に形成されたシリコン膜が
エネルギー線走査の際に剥離しやすいという問題
がある。 The lateral seeding method is a method in which a non-single-crystal silicon film on a silicon oxide film partially formed on a single-crystal silicon substrate by irradiation with energy rays is epitaxied from a silicon single crystal with the single-crystal silicon substrate exposed. In this method, the polysilicon on the silicon oxide film is made into a single crystal by double crystal growth. SOI by such lateral seeding method
The problem with the formation method is that when energy rays are applied to a non-single crystal silicon film to cause epitaxial growth, the non-single crystal silicon that is in contact with the single crystal silicon that is the seed part is difficult to melt; There is a phenomenon in which non-single-crystal silicon on a silicon oxide film that is scanned by an energy beam melts easily, and this non-uniform melting causes the silicon film formed on the silicon oxide film to melt when scanned by an energy beam. There is a problem that it is easy to peel off.
この溶融不均一の現象を防止するために、走査
するエネルギー線のエネルギーをそれぞれの場所
によつて変化すればよいが、実用上極めて微細な
面積上での制御は容易ではなく事実上不可能であ
り、これらの解決が要望されている。 In order to prevent this phenomenon of non-uniform melting, it is possible to change the energy of the scanning energy beam depending on the location, but in practice it is not easy to control it over an extremely minute area, and it is virtually impossible. There is a need for solutions to these issues.
第２図は従来のラテラルシーデング法による
SOIの形成方法を説明する半導体装置の断面図で
あるが、単結晶のシリコン基板１があり、その表
面の所定部分に酸化シリコン膜２が形成されてい
て、それらの表面にポリシリコン３が被覆されて
いる。
Figure 2 shows the conventional lateral seeding method.
This is a cross-sectional view of a semiconductor device for explaining a method of forming an SOI. There is a single-crystal silicon substrate 1, a silicon oxide film 2 is formed on a predetermined portion of its surface, and a polysilicon 3 is coated on those surfaces. has been done.
従つて、シード部分は単結晶のシリコン基板１
とポリシリコン３との接する接触面４の部分であ
り、酸化シリコン膜２とポリシリコン３が接する
部分との接触面５とでは、ポリシリコン膜と下地
の条件が異なる。 Therefore, the seed portion is a single crystal silicon substrate 1.
The conditions of the polysilicon film and the underlying material are different between the portion of the contact surface 4 where the silicon oxide film 2 and the polysilicon 3 are in contact, and the contact surface 5 where the silicon oxide film 2 and the polysilicon 3 are in contact.
このポリシリコン膜３の表面はレーザ６によつ
て、所定のエネルギーで矢印の方向に走査しなが
ら、ポリシリコンのエピタキシヤル成長がなされ
る。 Epitaxial growth of polysilicon is performed on the surface of this polysilicon film 3 while scanning the surface of the polysilicon film 3 in the direction of the arrow with a predetermined energy using a laser 6.
この際に、酸化シリコン膜２のポリシリコン膜
に供給されるレーザエネルギーが過飽和となり、
その結果屡々接触面５において剥離を生ずるとい
う欠点があつた。 At this time, the laser energy supplied to the polysilicon film of the silicon oxide film 2 becomes oversaturated,
As a result, the contact surface 5 often suffers from peeling.
上記の構成のものにおいて、酸化シリコン膜上
のシリコン膜がレーザ照射の際に剥離現象を起こ
す原因として、ポリシリコンの下地になつている
シード部分の単結晶シリコン基板は熱伝導が非常
に良好であり、反対に酸化シリコン膜の熱伝導は
単結晶のシリコン基板に比較して1/100程度で非
常に小であるために、一定のレーザエネルギーを
与えても、下地によつてポリシリコン膜の昇温す
る温度が異なり、シード部分上のポリシリコンが
溶融するレーザ照射条件では酸化シリコン膜上の
それに対して過飽和になると考えられる。
In the above configuration, the reason why the silicon film on the silicon oxide film peels off during laser irradiation is that the single crystal silicon substrate in the seed part, which is the base of the polysilicon, has very good thermal conductivity. On the contrary, the thermal conductivity of a silicon oxide film is very small, about 1/100 of that of a single-crystal silicon substrate, so even if a certain laser energy is applied, the thermal conductivity of a polysilicon film depends on the substrate. It is thought that under laser irradiation conditions in which the heating temperature is different and the polysilicon on the seed portion is melted, it becomes supersaturated with respect to that on the silicon oxide film.
この問題点を解決するために、ポリシリコン３
が接する下地部分の材質に無関係に、一様な溶融
状態を形成する方法を提供するものである。 In order to solve this problem, polysilicon 3
The present invention provides a method for forming a uniform molten state regardless of the material of the base portion in contact with the base material.
本発明は上記問題点を解消した半導体装置の製
造方法を提供するもので、その手段は、単結晶基
板上の一部に絶縁物を有する試料上に非単結晶膜
を形成して、ラテラルシーデング法を用いて該非
単結晶膜を単結晶化する際に、該絶縁物上にのみ
第１の非単結晶膜を形成してから、該第１の非単
結晶膜上にのみ分離層を形成し、次に該単結晶基
板上、該分離層上及びそれらの間の側壁上に連続
的に第２の非単結晶膜を形成してから、該第１及
び第２の非単結晶膜にエネルギー線のエネルギー
を供給することを特徴とする半導体装置の製造方
法によつて達成できる。
The present invention provides a method for manufacturing a semiconductor device that solves the above-mentioned problems. When the non-single crystal film is single crystallized using the Dengue method, a first non-single crystal film is formed only on the insulator, and then a separation layer is formed only on the first non-single crystal film. forming a second non-single-crystal film, then continuously forming a second non-single-crystal film on the single-crystal substrate, on the separation layer, and on the sidewall between them; This can be achieved by a method for manufacturing a semiconductor device characterized by supplying energy of energy rays to the semiconductor device.
即ち、本発明はラテラルシーデングを用いて
SOIを形成する際にポリシリコンの下地の熱伝導
の低い部分では、その部分のポリシリコンの温度
が上昇しすぎるので、そのポリシリコンの内部に
酸化シリコンと窒化シリコンの二層からなる熱の
分離層を設けることにより、この分離層と下地の
酸化シリコン膜との間にあるポリシリコンを傍熱
的に加熱して溶融状態を制御して、シード部分の
ポリシリコンとの溶融状態との溶融温度の整合を
とつてレーザ光の過飽和吸収による剥離を防止す
るように考慮したものである。
That is, the present invention uses lateral seeding to
When SOI is formed, the temperature of the polysilicon in those areas rises too much in areas with low thermal conductivity under the polysilicon, so a two-layer thermal isolation layer of silicon oxide and silicon nitride is placed inside the polysilicon. By providing a layer, the polysilicon between this separation layer and the underlying silicon oxide film is indirectly heated to control the melting state, and the melting temperature is lower than that of the polysilicon in the seed part. This is to prevent peeling due to supersaturated absorption of laser light by matching the above.
第１図は本発明の実施例を説明する断面図であ
るが、単結晶のシリコン基板１１があり、その表
面の所定部分に酸化シリコンの絶縁膜１２が形成
されていて通常この厚みは1μm程度であり、更に
その表面に第１のポリシリコン１３がCVD法に
より厚みが約4000Åに形成する。
FIG. 1 is a cross-sectional view illustrating an embodiment of the present invention. There is a single-crystal silicon substrate 11, and a silicon oxide insulating film 12 is formed on a predetermined portion of its surface, and the thickness is usually about 1 μm. Further, a first polysilicon 13 is formed on the surface by CVD to a thickness of about 4000 Å.
本発明による分離層１４は、第１のポリシリコ
ン膜１３の表面に形成されるもので、第１のポリ
シリコン１３を酸化して酸化シリコン層１５を厚
みが約360Åに形成し、更にその上に窒化シリコ
ン層１６を厚みが約800ÅでCVD法により生成し
て分離層１４を形成し、次に基板全面に第２のポ
リシリコン膜１７で被膜する。 The isolation layer 14 according to the present invention is formed on the surface of the first polysilicon film 13, and is formed by oxidizing the first polysilicon 13 to form a silicon oxide layer 15 with a thickness of about 360 Å. Next, a silicon nitride layer 16 having a thickness of about 800 Å is formed by the CVD method to form a separation layer 14, and then the entire surface of the substrate is coated with a second polysilicon film 17.
第１図で、シード部分１８は単結晶のシリコン
基板１１と第２のポリシリコン膜１７との接する
接触面の部分はシリコン基板の熱伝導が良好なた
めにポリシリコンの温度があまり上がらず、又酸
化シリコンの絶縁膜１２の表面の第１のポリシリ
コン膜１３と第２のポリシリコン膜１７との間に
ある分離層１４は熱伝導が低いために、レーザー
光線１９によつて加熱された第２のポリシリコン
膜１７から伝導される熱が第１のポリシリコン膜
１２に伝導されるのを阻止する役目をする。 In FIG. 1, the seed portion 18 is the contact surface between the single crystal silicon substrate 11 and the second polysilicon film 17, where the temperature of the polysilicon does not rise much because the silicon substrate has good thermal conductivity. Furthermore, since the separation layer 14 between the first polysilicon film 13 and the second polysilicon film 17 on the surface of the silicon oxide insulating film 12 has low thermal conductivity, This serves to prevent the heat conducted from the second polysilicon film 17 from being conducted to the first polysilicon film 12.
このことは従来方法による、酸化シリコンの絶
縁膜１２の熱伝導が低いためにポリシリコンの溶
融温度が上がり過ぎることを制御するものであ
り、実用上、この分離層の材質や厚みを可変にす
ることで熱伝導の条件を自由に制御することが可
能である。 This is to prevent the melting temperature of polysilicon from rising too high due to the low thermal conductivity of the silicon oxide insulating film 12 in the conventional method, and in practice, the material and thickness of this separation layer can be varied. This allows the conditions of heat conduction to be freely controlled.
以上詳細に説明したように本発明のラテラルシ
ーデングを用いてSOIを形成する製造方法を採用
することにより、剥離のない高信頼性の半導体装
置が実現でき効果大なるものがある。
As explained in detail above, by employing the manufacturing method of forming SOI using lateral seeding of the present invention, a highly reliable semiconductor device without peeling can be realized, which is highly effective.
第１図は本発明のエピタキシヤル成長を説明す
る断面図、第２図は従来のエピタキシヤル成長を
説明する断面図である。
図において、１１はシリコン基板、１２は酸化
シリコンの絶縁膜、１３は第１のポリシリコン、
１４は分離層、１５は酸化シリコン層、１６は窒
化シリコン層、１７は第２のポリシリコン膜、１
８はシード部分、１９はレーザー光線を示してい
る。
FIG. 1 is a sectional view illustrating epitaxial growth according to the present invention, and FIG. 2 is a sectional view illustrating conventional epitaxial growth. In the figure, 11 is a silicon substrate, 12 is a silicon oxide insulating film, 13 is a first polysilicon,
14 is a separation layer, 15 is a silicon oxide layer, 16 is a silicon nitride layer, 17 is a second polysilicon film, 1
Reference numeral 8 indicates a seed portion, and reference numeral 19 indicates a laser beam.
Claims (1)
に非単結晶膜を形成して、ラテラルシーデング法
を用いて該非単結晶膜を単結晶化する際に、該絶
縁物上にのみ第１の非単結晶膜を形成してから、
該第１の非単結晶膜上にのみ分離層を形成し、次
に該単結晶基板上、該分離層上及びそれらの間の
側壁上に連続的に第２の非単結晶膜を形成してか
ら、該第１及び第２の非単結晶膜にエネルギー線
のエネルギーを供給することを特徴とする半導体
装置の製造方法。1. When forming a non-single-crystal film on a sample that has an insulator on a part of the single-crystal substrate and monocrystallizing the non-single-crystal film using the lateral seeding method, After forming the first non-single crystal film,
A separation layer is formed only on the first non-single crystal film, and then a second non-single crystal film is continuously formed on the single crystal substrate, the separation layer, and the sidewalls therebetween. A method of manufacturing a semiconductor device, comprising: supplying energy of energy rays to the first and second non-single crystal films.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59188444A JPS6167219A (en) | 1984-09-07 | 1984-09-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59188444A JPS6167219A (en) | 1984-09-07 | 1984-09-07 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6167219A JPS6167219A (en) | 1986-04-07 |
| JPH0582733B2 true JPH0582733B2 (en) | 1993-11-22 |
Family
ID=16223789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59188444A Granted JPS6167219A (en) | 1984-09-07 | 1984-09-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6167219A (en) |
-
1984
- 1984-09-07 JP JP59188444A patent/JPS6167219A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6167219A (en) | 1986-04-07 |
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