JPS6091622A - Manufacture of semiconductor substrate - Google Patents

Manufacture of semiconductor substrate

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Publication number
JPS6091622A
JPS6091622A JP58199050A JP19905083A JPS6091622A JP S6091622 A JPS6091622 A JP S6091622A JP 58199050 A JP58199050 A JP 58199050A JP 19905083 A JP19905083 A JP 19905083A JP S6091622 A JPS6091622 A JP S6091622A
Authority
JP
Japan
Prior art keywords
region
manufacturing
semiconductor substrate
semiconductor
melting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58199050A
Other languages
Japanese (ja)
Inventor
Yutaka Kobayashi
裕 小林
Hiroshi Suga
須賀　博
Akira Fukami
深見　彰
Takaya Suzuki
誉也 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58199050A priority Critical patent/JPS6091622A/en
Publication of JPS6091622A publication Critical patent/JPS6091622A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Optics & Photonics (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To equalize the facial direction of a semiconductor assuring the reliability of characteristics of the element formed on the surface of semiconductor by a method wherein a part of semiconductor layer is not crystallized as a region to be melted for regrowing process. CONSTITUTION:Polycrystalline Si layer 2 is formed on the surface of an optically ground quartz substrate 1 by CVD process later to form an Si island by dry etching process. Furthermore Si is etched excluding the region on the end of the side wherein recrystalization is to be started. The residual Si island and the exposed part of the substrate 1 is coated with the Si2 film 6. The substrate 1 thus formed may be melted to be regrown by means of zone-melting regrowing device.

Description

【発明の詳細な説明】 〔発明の利用分封〕 本発明は絶縁基板あるいは絶縁膜上に半導体単結晶薄膜
を形成してなる半導体基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Uses of the Invention] The present invention relates to a method for manufacturing a semiconductor substrate in which a semiconductor single crystal thin film is formed on an insulating substrate or an insulating film.

〔発明の背景〕[Background of the invention]

従来、絶縁基板として単結晶サファイヤあるいはマピネ
ル等を用い、この基板上に結晶化していないシリコン層
を気相成長（ＣＶ　Ｄ　：　（：’ｈｅｍｉｃａＩＶａ
ｐｏｒ　、［）ｅｐｏｓｉｔｉｏｎ　）により形成し、
それを溶融再成長によって単結晶化する半導体基板の製
造方法が知られていｆｃ、　Ｌかし、単結晶サファイヤ
あるいはスピネル等が高価な材料であるため、この構造
それ自体が一般化されるまでＫは至らなかったものであ
る。Conventionally, single-crystal sapphire or Mapinel is used as an insulating substrate, and an uncrystallized silicon layer is grown on this substrate by vapor phase growth (CVD: (:'hemicaIVa).
por, [)eposition),
A manufacturing method for semiconductor substrates is known in which semiconductor substrates are made into single crystals by melting and regrowing them.Since fc, L oak, single crystal sapphire, spinel, etc. are expensive materials, it will be difficult to manufacture semiconductor substrates until this structure itself becomes generalized. was not reached.

このため、絶縁基板として非晶質石英、ガラスあるいは
Ｓｉ上に形成した非晶質ｓ；０．膜等の廉価な材料を使
用し、この面上に結晶化されたｓｉを形成する方法が提
案されてきた。しかし、この方法の欠点は種結晶を使用
しないため、溶融再成長後の単結晶層の面方位の制御が
非常に困難な仁とである。一方、種結晶を使用する方法
として、単結晶Ｓｉ上の５ｉＱ２膜に突を形成しその上
に堆積した多結晶ｓｉを再成長させることによシ面方位
を制御する方法があるが、素子設計に自由度がなく、使
用しすらい。For this reason, an amorphous s;0. Methods have been proposed to form crystallized Si on this surface using inexpensive materials such as films. However, the drawback of this method is that since no seed crystal is used, it is very difficult to control the plane orientation of the single crystal layer after melting and regrowth. On the other hand, as a method using a seed crystal, there is a method in which the crystal plane orientation is controlled by forming protrusions in the 5iQ2 film on single crystal Si and regrowing the polycrystalline Si deposited on the protrusions. There is no freedom in using it.

〔発１．１ＩｌＪの目的〕 本発明の目的ｉ−Ｊ溶融再成長させた半導体単結晶領域
の面方位が一定となるように、シ、これにより各領域に
形成する素子の特性の信頼性を確保できる半導体基板の
製造方法を提供するにある。[1.1 Purpose of IlJ] Purpose of the present invention To make the plane orientation of the i-J melted and regrown semiconductor single crystal region constant, thereby increasing the reliability of the characteristics of the elements formed in each region. An object of the present invention is to provide a method for manufacturing a semiconductor substrate that can be manufactured with high reliability.

〔発明の概要〕[Summary of the invention]

かかる目的を奏す本発明半導体基板の製造方法の特徴と
するところは、半導体層を溶融再成長する際に半導体層
の一部に結晶化から取り残された領域を生じさせる点に
ある。A feature of the method for manufacturing a semiconductor substrate of the present invention that achieves the above object is that when the semiconductor layer is melted and regrown, a region left behind from crystallization is generated in a part of the semiconductor layer.

結晶化から取り残された領域を生じさせる具体的手段と
しては、半導体ノｄの厚さ或いは幅を他の部分よシ大き
くして熱容量を大きくすること、溶融再成長時の加熱時
間或いは加熱温度を他の部分より小さくすること、更に
はこれらの組合せによって実現できる。Specific means for creating a region left behind from crystallization include increasing the heat capacity by increasing the thickness or width of the semiconductor nozzle d compared to other parts, and increasing the heating time or heating temperature during melting and regrowth. It can be realized by making it smaller than other parts or by a combination of these parts.

結晶化から取シ残された領域は、半導体層の溶融再成長
が進行する方向の出発点付近に設けることが好ましい。The region left behind from crystallization is preferably provided near the starting point in the direction in which melting and regrowth of the semiconductor layer progresses.

また、この結晶化から取シ残された領域は、半導体層が
大面積或いは細長い場合には略等間隔に複数個形成する
のが結晶性の点で好ましい。Further, in the case where the semiconductor layer has a large area or is long and narrow, it is preferable to form a plurality of regions left after this crystallization at approximately equal intervals from the viewpoint of crystallinity.

このように結晶化から取勺残された領域を形成すると、
溶融再成長によって結晶化された領域はすべて（１００
）の面方位にできるのである。この理由は定かではない
が、数多くの実験を通して発明者らにより確認され、再
現性よ＜　（１００）の面方位を有する単結晶層が得ら
れることは事実である。By forming the region left behind from crystallization in this way,
All regions crystallized by melt regrowth are (100
). Although the reason for this is not clear, it has been confirmed by the inventors through numerous experiments that it is true that a single crystal layer having a plane orientation of <(100) can be obtained with reproducibility.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明を具体的実施例により詳細に説明する。 Hereinafter, the present invention will be explained in detail with reference to specific examples.

〔実ｍ列ｌ〕[Real m column l]

第１図において、厚さ５００μＩｎで表面を光学研摩し
た石英基板ｌ上に厚さ１μｍの多結晶５ｉＮ２をＣＶＤ
により形成しくａ八その後ドライエッチによりｌｌ’！
３０μｍ、長す８０　ｐｍ（７）Ｓ　ｒＱ）ｇＪ、３を
形成する（ｂ）。さらに再結晶化が開始する側（再結晶
方向と逆方向）の端の領域４を残し０．２５μｍだけＳ
ｉをエツチングし、０．７５μｍの厚さにする（Ｃ）。In Figure 1, polycrystalline 5iN2 with a thickness of 1 μm is deposited by CVD on a quartz substrate l with a thickness of 500 μIn and whose surface is optically polished.
After that, dry etching is performed to form ll'!
30 μm, 80 pm long (7)S rQ) gJ, 3 (b). Furthermore, a region 4 at the end on the side where recrystallization starts (in the direction opposite to the recrystallization direction) is left by 0.25 μm S.
i is etched to a thickness of 0.75 μm (C).

次に残ったＳｉ膜島及び基板の露出部を１．２μｍの５
ｊ０２１漠６により被覆する（ｄ）。このようにして形
成した基板を第２図に示すゾーンメルティング再成長装
置により溶融再成長させた。Next, the remaining Si film islands and exposed parts of the substrate were
Covered by j021 6 (d). The thus formed substrate was melted and regrown using a zone melting regrowth apparatus shown in FIG.

第２図にしいて、１１は石英管、１２はワークコイル、
１３はカーボンサセプタ、１４は石英製支持台、１５は
モーターで駆動される石英製押棒で、カーボンサセプタ
１２の上面には長手方向と直交する帯域をあけてその両
側に加熱バッファ板１６が配置され、高温領域と低温領
域が規定されている。１７は第１　区：（ｄ）に示す基
板である。この溶融再成長の結果、膜厚１．０μｍの領
域４は溶融せず膜厚０，７５μＩｎの領域５では溶融再
成長が生じた。In Figure 2, 11 is a quartz tube, 12 is a work coil,
13 is a carbon susceptor, 14 is a quartz support, 15 is a quartz push rod driven by a motor, and heating buffer plates 16 are arranged on both sides of the upper surface of the carbon susceptor 12 with a zone perpendicular to the longitudinal direction. , a high temperature region and a low temperature region are defined. 17 is the substrate shown in the first section (d). As a result of this melting and regrowth, region 4 with a film thickness of 1.0 .mu.m did not melt, but melting and regrowth occurred in region 5 with a film thickness of 0.75 .mu.In.

再成長した領域の面方位を調べたところ面方位は全て（
ｉｏｏ）而であった。さらに、この再成長Ｓｉ膜にｎチ
ャネルＭＯ８ＦＥＴ　を作製したところ、表面のチャネ
ル移動度は６００〜１０００ｃｍ”／　Ｖ−へリーク電
流１Ｏ−１３Ａ／μｍと良好な値が得られた。When we investigated the plane orientation of the regrown region, all plane orientations were (
ioo) It was. Furthermore, when an n-channel MO8FET was fabricated on this regrown Si film, a good surface channel mobility of 600 to 1000 cm''/V- leakage current of 10-13 A/μm was obtained.

〔実施例２〕 実施例１では、Ｓ’島に膜厚の厚い個所と薄い個所を形
成した場合を示したが、第３図に示すように各Ｓｉ島３
ごとに溶融再成長方向と直角をなす方向の幅の大きい部
分３１と小さい部分３２とを形成した場合に訃いても実
施例１と同様の結果が得られた。[Example 2] In Example 1, a case was shown in which thick and thin parts were formed on the S' island, but as shown in Fig. 3, each Si island 3
The same results as in Example 1 were obtained even when a wide portion 31 and a narrow portion 32 in the direction perpendicular to the melting and regrowth direction were formed in each case.

〔実施例３〕 実施例１と同様の方法Ｃ石英基板上に膜厚０．７５μｍ
の多結晶Ｓｉ膜を形成する。このＳｉ膜をドライエツチ
ングにより次に述べるパターンに加工する。素子を形成
するＳｉ島２１（本実施例では幅２０μｍ１長さ８０μ
ｍ）を書結晶の方向に幅１０μｍのＳＬ連結膜２２で連
結し、再成長が開始する画の端に幅１００μｍ１長さ２
ｒｒｓの島２３（素子を形成するＳｉ島２１よシ大きい
）を形成し、この島２３にそれぞれ素子を形成する複数
のＳｉ島２１と連結膜２２からなる複数列の条状領域全
連結する（第４図）。[Example 3] Same method as Example 1 C film thickness 0.75 μm on quartz substrate
A polycrystalline Si film is formed. This Si film is processed into the following pattern by dry etching. Si island 21 forming the element (in this example, the width is 20 μm and the length is 80 μm)
m) in the direction of the book crystal with a 10 μm wide SL connecting film 22, and a 100 μm wide 1 length 2 film at the edge of the picture where regrowth starts.
rrs islands 23 (larger than the Si islands 21 forming the elements) are formed, and on this island 23, all the striped regions of multiple rows consisting of the plurality of Si islands 21 forming the elements and the connecting film 22 are all connected ( Figure 4).

このようにして形成した多結晶Ｓｉ膜表面を膜厚１．２
μｍ（７）ＣｖＤＳｊＯｚ膜テｖｌａＥした後実施１＋
ｌ１１と同様溶融再成長を行った。その結果島２３は一
部分しか溶融せず、そこから続く連結膜２２及びＳｉ島
２１は全領域再結晶化しており、面方位を調べたところ
（１００）面に配向していた。また実施例１と同様ｎチ
ャネルｆ＼４０Ｓｌ；’ＥＴを作製したところ表面移動
度は６００〜１０００ｃｒｎ２／ｖ−８１リ一ク社流Ｉ
Ｑ−１３７１／μｍの特性が得られた。The surface of the polycrystalline Si film formed in this way has a film thickness of 1.2
μm (7) CvDSjOz membrane test performed after vlaE 1+
Melt regrowth was performed in the same manner as 111. As a result, only a portion of the island 23 was melted, and the connecting film 22 and the Si island 21 continuing therefrom were all recrystallized, and when the plane orientation was examined, it was found to be oriented in the (100) plane. In addition, when an n-channel f\40Sl;'ET was prepared in the same manner as in Example 1, the surface mobility was 600 to 1000 crn2/v-81 Riik's I
A characteristic of Q-1371/μm was obtained.

本実施例にかいては端部に幅１００μｍ長さ２闘の島２
３をもうけたが、これを素子を形成するＳｉ島２１よシ
大きな島で分割してもよい。また、基板内を複数のブロ
ックに分け、各ブロックに１つの割シ合で大きな島を形
成してもよい。In this example, the end portion has a width of 100 μm and a length of 2 pieces.
3, but this may be divided into islands larger than the Si island 21 forming the element. Alternatively, the inside of the substrate may be divided into a plurality of blocks, and one large island may be formed in each block.

〔実施例４〕 実施例１と同様の方法で膜厚１μｍの多結晶Ｓｉを形成
する。その後、素子を形成する領域のＳｔ島４１と、連
らなるＳｉ島の列で再結晶化が開始する領域の端にＳｉ
島４２を少なくとも１ヶ以上形成し、それぞれの島を幅
１０μｍのＢｔで再結晶化が進む方向に連結膜４３によ
り連結した形状にドライエッチする（第５図）。その後
、余分に形成したＳｉ島４２をのぞき他の領域４１゜４
３を０．２５μｍエツチングした後、全面を膜厚１、２
μｎｌのＣＶＤ５’Ｏｚ膜で被覆する。その後、実施例
１．３と同様溶融再成長させた。[Example 4] Polycrystalline Si having a thickness of 1 μm is formed in the same manner as in Example 1. After that, Si
At least one or more islands 42 are formed, and each island is dry-etched into a shape connected by a connecting film 43 in the direction in which recrystallization proceeds with Bt having a width of 10 μm (FIG. 5). After that, except for the extra formed Si island 42, the other regions 41°4
After etching 3 by 0.25 μm, the entire surface was etched with a film thickness of 1 and 2.
Coat with μnl of CVD 5'Oz film. Thereafter, it was melted and regrown in the same manner as in Example 1.3.

再成長させたＳｉ島４１の面方位を調べた結果、全て（
１００）面であることが分った。実施例１と同様１７）
工程テｎ　−ｃｂａｎｎｅｌ　ＭＯＳＦＥＴ　を製作し
たところ、キャリアの移動度は６００〜１２００ａｎ”
　／　Ｖ−８となシ、実施例１に比べ良好な結果が得ら
れた。この実施例４は実施例１と同様の方法で）溶ｍｌ
域を形成しているが、異なる点は）溶領域の後を細い連
結領域で連ねている点である。As a result of examining the plane orientation of the regrown Si island 41, all (
100) surface. Same as Example 117)
When a n-cbannel MOSFET was manufactured, the carrier mobility was 600 to 1200 an''.
/V-8, better results were obtained than in Example 1. This Example 4 was prepared in a similar manner to Example 1)
The difference is that the melted area is followed by a thin connecting area.

５溶領域が含まれる島は表面に垂直な方位は（１００）
となるので面方位は（１００）である。The direction perpendicular to the surface of the island containing 5 melting regions is (100)
Therefore, the surface orientation is (100).

しかし、表面に垂直な軸での回転方向の角度が異なるＡ
域が混在する。However, A with different angles of rotation about the axis perpendicular to the surface
areas are mixed.

これに比べ５溶領域を會む島からその後に続く島を連結
することにより、連結領域で優勢な面方位が選択される
。即ち、軸の回転方向の角度もそろった（１００）の単
結晶Ｓｉ島が形成できる。In contrast, by connecting the islands following the island that meets the five melting regions, the plane orientation that is dominant in the connected region is selected. In other words, single crystal Si islands with (100) angles in the rotation direction of the axes can be formed.

このため上述の如く移動度が大きく特性のばらつきも少
なかった。Therefore, as mentioned above, the mobility was large and the variation in characteristics was small.

実施例３．４にしいては、熱容量の大きな３ｉ島をチッ
プ端やウェハ端に形成したが、周９の素子に悪影響をあ
たえないならばチップ内等に形成してもよいことは明ら
かである。In Example 3.4, the 3i islands with large heat capacity were formed at the edge of the chip or the edge of the wafer, but it is clear that they may be formed inside the chip, etc., as long as they do not adversely affect the elements on the periphery 9. .

〔実施例５〕 実施例１と同様の方法で膜厚０．７５μＩｌｌの多結晶
Ｓｉを形成する。その後、素子を形成する領域とを形成
し、それぞれの島を幅１０μｍのＳｉの連結膜５３で再
結晶化が進む方向に連結した形状にドライエッチする（
第６図）。この多結晶Ｓｉ表１ｆｆｉＫＩＩ＆厚１．２
　ｐ　ｍノＣＶ　Ｄ　−Ｓ　ｊ（ｈ膜−ｔ’ｍｕする。[Example 5] A polycrystalline Si film having a thickness of 0.75 μIll is formed in the same manner as in Example 1. After that, a region where an element will be formed is formed, and each island is dry-etched into a shape in which the islands are connected in the direction of recrystallization by a Si connection film 53 with a width of 10 μm (
Figure 6). This polycrystalline Si table 1ffiKII & thickness 1.2
pm CV D - S j (h membrane - t'mu.

このようにして形成した後第２図に示す装置で溶融再結
晶するが、この時、余分のＳｉ島５２の間は高温領域の
移動速度を速く（例えば５〜１００鴫／Ｓ）するか、あ
るいは、高温領域の温度を融点以下にする。余分のＳｉ
島５２が完全に通過する前に高温領域の移動速度を従来
の速度（例えば０．０１〜２ｗｎ／ｓΣかあるいは従来
の高温領域温度（例えば１４３０〜１４７０ｔ：”　）
にすることによシ溶融再成長を開始させる。このように
することによシ溶融再成長が開始する領域が溶融しない
領域に接し実施例１．３．４と同様の効果が生じた。こ
のように形成した再結晶Ｂｉの面方位ｆｔ調べたところ
（１００）に配向していた。After being formed in this way, it is melted and recrystallized using the apparatus shown in FIG. Alternatively, the temperature of the high temperature region is lowered to below the melting point. extra Si
Before the island 52 completely passes through, the moving speed of the high temperature area is set to a conventional speed (for example, 0.01 to 2 wn/sΣ or a conventional high temperature area temperature (for example, 1430 to 1470 t:").
This causes melting and regrowth to begin. By doing this, the region where melting and regrowth starts comes into contact with the region where melting does not occur, and the same effect as in Example 1.3.4 was produced. When the plane orientation ft of the recrystallized Bi thus formed was examined, it was found to be oriented in (100).

以上示した実施例にνいて、多結晶５ｉｔ−ｓるパター
ンに形成する手段としてドライエッチフグを使用したが
、ウェットエツチングであっても、またＳｉ島間を８１
０を膜等でうめるＬＯＣＯ８（、［、ｏｃａｌ　Ｑｘｉ
ｄａｔｉｏｎ　ｏｆ　３ｉ１ｉｃｏｎ）等の技術を使用
してもよいことは明らかである。また、本実施例では非
晶質石英板上のＳｉを例にしたが、単結晶Ｓｉや多結晶
Ｓｉ上に形成したＳ’Ｏｚ膜や５ｒｓＮａ　膜上の３４
であっても同様に適用できる。In the example shown above, a dry etching blower was used as a means to form a polycrystalline 5-it-s pattern, but even wet etching can also be used to
LOCO8 (, [, ocal Qxi
It is clear that techniques such as dation of 3ilicon may also be used. In addition, in this example, Si on an amorphous quartz plate was used as an example, but the S'Oz film formed on single crystal Si or polycrystalline Si, or the
The same applies even if

被覆膜としてＣｖＤＳｊＯ＊膜を使用したが、他の形成
法例えばスパッタｓ　ｆｉｘ膜であってもよいし、また
８１ＭＮ４　膜や、５ｊ（ｈ膜とＳ＋ｓＮａ膜の複合膜
であってもよい。被覆膜としては、融点が形成する半導
体の融点以上で、しかも高温で安定な膜であればいかな
る膜であってもよい。さらに、８１ばかシでなく、（）
ｅやＧａＡＳ＋　ＧａＰ、ＩｎＰ。Although a CvDSjO* film was used as the coating film, other formation methods such as a sputter s fix film may be used, or a composite film of an 81MN4 film or a 5j(h film and an S+sNa film) may be used. The covering film may be any film as long as it has a melting point higher than the melting point of the semiconductor to be formed and is stable at high temperatures.
e, GaAS+ GaP, InP.

等のｍ　ｖ族化合物半導体や、ＪｎＱａＡｓＰ　。mv group compound semiconductors such as JnQaAsP.

Ｕ　ａ　ＡｔＡ　ｓ　＊　＜Ｊ　ａ　ＡｔＡｓ　Ｐ等の
混晶系の半導体、さらにはｕ■族半導体に適用できるこ
とは容易に分かる。It is easy to see that the present invention can be applied to mixed crystal semiconductors such as U a AtAs * < J a AtAs P, and further to u-group semiconductors.

また、溶融再成長法として、第２図に示す。高周波誘導
加熱を使用したゾーンメルティング再成長を例にしたが
、カーボンストリップヒータや、タングステンヒータお
よび水銀ランプ等を使用したゾーンメルティング再成長
法にも適用が可能であることはもらろん、レーザ光や電
子線等を使用した溶融再成長にも適用できることは明確
である。Further, a melt regrowth method is shown in FIG. 2. Although we have used zone melting regrowth using high-frequency induction heating as an example, it is of course also applicable to zone melting regrowth methods using carbon strip heaters, tungsten heaters, mercury lamps, etc. It is clear that the present invention can also be applied to melt regrowth using laser light, electron beams, etc.

〔発明の効果〕〔Effect of the invention〕

以上述べたことから明らかなように、本発明による半導
体基板の製造方法によれば再成長させた半導体の面方位
を一定にでき、これにより前記半導体面に形成する素子
の特性の信頼性を確保することができる。As is clear from the above description, according to the method for manufacturing a semiconductor substrate according to the present invention, the plane orientation of the regrown semiconductor can be made constant, thereby ensuring the reliability of the characteristics of the element formed on the semiconductor surface. can do.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す工程図、第２図は本発
明で使用する再成長装置の一例を示す概略断面図、第３
図から第６図は本発明の他の実施例を示す半導体基板の
平面図である。 拓１図 第　Ｚ　閏 拓　３　ｍFig. 1 is a process diagram showing one embodiment of the present invention, Fig. 2 is a schematic sectional view showing an example of a regrowth apparatus used in the present invention, and Fig.
6 are plan views of a semiconductor substrate showing other embodiments of the present invention. Drawing 1 Figure Z Escape 3 m

Claims (1)

【特許請求の範囲】 ■、絶縁基板あるいは絶縁膜上の所定の領域に半導体ノ
ーを形成し、この半導体ノーを溶融再成長によって結晶
化する半導体基板の製造方法において、上記半導体層を
その一部に結晶化から取り残された領域が生じるような
信性で溶融再成長させることを％敵とする半導体基板の
製造方法。 ２、特許請求の範囲第１項にしいて、上記半導体層の最
初に溶融再成長が行なわれる個所の近傍の領域の熱容量
を池より大きクシ、この領域を結晶化から取り残された
領域とすることを特徴とする半導体基板の製造方法。 ３、特許請求の範囲第２項において、上記半導体層の熱
容量の大きい領域は、他よシ厚さが大きいことを特徴と
する半導体基板の製造方法。 ４、特許請求の範囲第１項において、上記半導体層の溶
融再成長時に結晶化から取シ残される領域の加熱時間を
池の領域より短かくすることを特徴とする半導体基板の
製造方法。 ５、特許請求の範囲第１項において、上記半導体層が多
数個の島状領域からなることを特徴とする半導体基板の
製造方法。 ６、特許請求の範囲第５項において、上記半導体層の各
島状領域の最初に溶融再成長が行なわれる個所の近傍の
個所の熱容量を他より大きくシ、これによってこの個所
を結晶化から取り残された領域とすることを特徴とする
半導体基板の製造方法。 ７、特許請求の範囲第６項において、上記島状領域の熱
容量の大きい領域は、他より厚さが大きいことを特徴と
する半導体基板の製造方法。 ８、特許請求の範囲第５項、第６項或いは第７項におい
て、上記各島状領域の結晶化から取り残される領域の溶
融再成長が進行する方向と直角をなす方向の幅が曲より
大きくなっていることを特徴とする半導体基板の製造方
法。 ９、特許請求の範囲第１項において、上記半導体層が一
方向に延びる複数個の第１の領域と、第１の領域相互を
一方向の端部で連結する第２の領域とから形成し、第２
の１頂載側から溶融再成長を行ないかつ第２の領域を結
晶化から取り残された領域とすることを特徴とする半導
体基板の製造方法。 １０、特許請求の範囲第９項において、上記第２の領域
の熱容量を上記第１の領域のそれより大きくしたことを
％徴とする半導体基板の製造方法。 １１、特許請求の範囲第９項或いは第１０項において、
上記第１の領域が長手方向に沿って幅の広い部分と狭い
部分とからなっていることを特徴とする半４本基板の製
造方法。 １２、特許請求の範囲第１１項において、上記第１の領
域の幅の広い部分の一部にも結晶化から取り残された個
所が生じるような条件で溶融再成長を行なうことを特徴
とする半導体基板の製造方法。[Scope of Claims] (1) A method for manufacturing a semiconductor substrate in which a semiconductor layer is formed in a predetermined region on an insulating substrate or an insulating film, and the semiconductor layer is crystallized by melting and regrowth; A method of manufacturing semiconductor substrates that aims to melt and re-grow them with such reliability that regions left behind from crystallization occur. 2. According to claim 1, the heat capacity of the region near the point where the semiconductor layer is first melted and regrown is larger than that of the pond, and this region is the region left behind from crystallization. A method for manufacturing a semiconductor substrate, characterized by: 3. The method of manufacturing a semiconductor substrate according to claim 2, wherein the region of the semiconductor layer having a large heat capacity has a larger thickness than the other regions. 4. The method of manufacturing a semiconductor substrate according to claim 1, characterized in that the heating time of the region left behind from crystallization during melting and regrowth of the semiconductor layer is made shorter than that of the pond region. 5. The method of manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor layer is comprised of a large number of island-like regions. 6. In claim 5, the heat capacity of a portion of each island region of the semiconductor layer near the portion where melting and regrowth is first performed is made larger than other portions, thereby leaving this portion out of crystallization. 1. A method of manufacturing a semiconductor substrate, characterized in that the region is 7. The method of manufacturing a semiconductor substrate according to claim 6, wherein the region of the island-like region having a large heat capacity has a thickness larger than that of the other region. 8. Claims 5, 6, or 7, wherein the width of the region left behind from the crystallization of each of the island regions in the direction perpendicular to the direction in which melting and regrowth progresses is larger than the curve. A method for manufacturing a semiconductor substrate, characterized in that: 9. Claim 1, wherein the semiconductor layer is formed from a plurality of first regions extending in one direction and a second region connecting the first regions at ends in one direction. , second
A method for manufacturing a semiconductor substrate, characterized in that melting and regrowth is performed from the top side of the semiconductor substrate, and a second region is left behind from crystallization. 10. The method of manufacturing a semiconductor substrate according to claim 9, wherein the heat capacity of the second region is larger than that of the first region. 11. In claim 9 or 10,
A method for manufacturing a semi-quad board, characterized in that the first region consists of a wide part and a narrow part along the longitudinal direction. 12. The semiconductor according to claim 11, characterized in that the melting and regrowth is performed under conditions such that a portion of the wide portion of the first region is left behind from crystallization. Substrate manufacturing method.
JP58199050A 1983-10-26 1983-10-26 Manufacture of semiconductor substrate Pending JPS6091622A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58199050A JPS6091622A (en) 1983-10-26 1983-10-26 Manufacture of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58199050A JPS6091622A (en) 1983-10-26 1983-10-26 Manufacture of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS6091622A true JPS6091622A (en) 1985-05-23

Family

ID=16401275

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58199050A Pending JPS6091622A (en) 1983-10-26 1983-10-26 Manufacture of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS6091622A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002222959A (en) * 2001-01-29 2002-08-09 Hitachi Ltd Thin film semiconductor device as well as method and apparatus for manufacturing polycrystal semiconductor thin film
JP2008199042A (en) * 2008-03-14 2008-08-28 Hitachi Ltd Method of manufacturing image display device using thin-film semiconductor device
JP2008199041A (en) * 2008-03-14 2008-08-28 Hitachi Ltd Thin-film semiconductor device and image display device using the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002222959A (en) * 2001-01-29 2002-08-09 Hitachi Ltd Thin film semiconductor device as well as method and apparatus for manufacturing polycrystal semiconductor thin film
JP2008199042A (en) * 2008-03-14 2008-08-28 Hitachi Ltd Method of manufacturing image display device using thin-film semiconductor device
JP2008199041A (en) * 2008-03-14 2008-08-28 Hitachi Ltd Thin-film semiconductor device and image display device using the same

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