JPS59101822A - Manufacture of substrate for semiconductor device - Google Patents

Manufacture of substrate for semiconductor device

Info

Publication number
JPS59101822A
JPS59101822A JP57212219A JP21221982A JPS59101822A JP S59101822 A JPS59101822 A JP S59101822A JP 57212219 A JP57212219 A JP 57212219A JP 21221982 A JP21221982 A JP 21221982A JP S59101822 A JPS59101822 A JP S59101822A
Authority
JP
Japan
Prior art keywords
substrate
single crystal
opening
insulating film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57212219A
Other languages
Japanese (ja)
Inventor
Koichi Kugimiya
公一 釘宮
Shinichi Ogawa
真一 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57212219A priority Critical patent/JPS59101822A/en
Publication of JPS59101822A publication Critical patent/JPS59101822A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To form an excellent single crystal on the substrate and an insulating film, and to obtain the substrate, through which an element, speed thereof is changed into ultraspeed, can be realized, by generating a change into the single crystal from a single crystal region without generating it from the substrate. CONSTITUTION:An insulating oxide film 3 is formed on a silicon wafer 1, an opening 2 is formed, a silicon semiconductor layer is formed through evaporation by electron beams, and a single crystal section 8 and a polycrystalline film 7 are formed. Si Ions 9 are implanted to form an amorphous layer 30. A solid-phase epitaxial layer is moved as the arrow 31 by heating beams 11 to form the single crystal region 32, the semiconductor element requiring high speed is formed to a section on the insulating section 3, and the element to which severe leakage and dielectric resistance characteristics and the like are needed is constituted on the opening section 2, which is grown in an epitaxial manner, as a more complete single crystal region.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置用基板に関し、詳しくは少なくとも
一部の単体素子を絶縁膜上に形成し、超高速化を実現す
ることによシ、合理的に装置全体の速度を向上せしめ、
且つ、特性の向上２歩留り向上を実現する超ＬＳＩ技術
に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a substrate for a semiconductor device, and more specifically, it is possible to form at least some of the single elements on an insulating film to achieve ultra-high speed. improves the overall speed of the device,
The present invention also relates to VLSI technology that realizes improved characteristics and improved yield.

従来例の構成とその問題点 絶縁膜上に単結晶半導体層を形成する技術としては、種
々の方法が提案されている。グラフオエピタキシーによ
れば、微小な凹部内に方位の定まったある程度の単結晶
が得られるようになってきているが、単結晶自体の大き
さが小さく実用にはなっていない。また溝の形状で結晶
方位が制御されることが一部で言われているが、例えば
シリコンでＶｉ制御されておらず、又、原理的にみても
（１１ｏ）と（１−００）を区別するのは実用上非常に
難しい。Conventional Structures and Their Problems Various methods have been proposed as techniques for forming a single crystal semiconductor layer on an insulating film. According to graphoepitaxy, it has become possible to obtain a certain amount of single crystal with a fixed orientation within a minute recess, but the size of the single crystal itself is small and it has not been put to practical use. Also, it is said that the crystal orientation is controlled by the shape of the groove, but for example, in silicon, Vi is not controlled, and even in principle, (11o) and (1-00) can be distinguished. It is extremely difficult to do so in practice.

さらに、イオン注入によって非晶質化した単結晶半導体
表面を固相エピによシ、再び良質の単結晶半導体に戻せ
ることが知られているが、絶縁膜上への単結晶半導体の
成長は限度があシ、多結晶化してしまうなどの難点があ
った。即ち、第１図に示すように、先ずたとえばシリコ
ン単結晶シリコン基板１の開口部２及び絶縁部３上に、
例えばポリシリコン膜４を形成し、次にセルフイオン注
入などによシ基板１表面の膜４との界面５１で非晶質化
し、さらに５００〜７００℃に基板を加熱してポリシリ
コン膜４の単結晶化を行う訂第１図においてロコの部分
はイオン注入による非晶質化部分を示す。この方法では
基板１を種結晶として矢印のごとくポリシリコン膜４の
単結晶化が進むが、この時、図に示すように、別の場合
６から核形成が生じ、絶縁膜３上の大部分は多結晶とな
ってし１う不都合がちシ、絶縁膜３上に良質な単結晶シ
リコン層を得ることが困難である。Furthermore, it is known that the surface of a single crystal semiconductor that has been made amorphous by ion implantation can be returned to a high-quality single crystal semiconductor by solid-phase epitaxy, but there is a limit to the growth of a single crystal semiconductor on an insulating film. There were problems such as oxidation and polycrystalline formation. That is, as shown in FIG. 1, first, for example, on the opening 2 and the insulating part 3 of the silicon single crystal silicon substrate 1,
For example, a polysilicon film 4 is formed, and then the surface of the substrate 1 is made amorphous at the interface 51 with the film 4 by self-ion implantation, and the substrate is further heated to 500 to 700°C to form the polysilicon film 4. In FIG. 1, the loco portion indicates the portion made amorphous by ion implantation. In this method, the single crystallization of the polysilicon film 4 proceeds as shown by the arrow using the substrate 1 as a seed crystal. However, it is difficult to obtain a high quality single crystal silicon layer on the insulating film 3.

また、種結晶から絶縁膜上に単結晶をつづけて成長せし
める方法として、線状の加熱源によシ、多結晶材料を熔
融再結晶化する方法が提案され、ある程度の成考が伝え
られているが、本発明０者らの検討によっても、途中か
ら別の結晶′が絶縁膜壁から形成されたり、絶縁膜が溶
解し、例えば、酸素や窒素が過剰に溶解したり時には析
出し、得られる単結晶の品質が非常に悪いことが伴明し
ている。又、熔融するため表面にゆらぎが生じ、凹凸を
含む成長しまが形成されるなどの欠点がある。In addition, as a method for continuously growing single crystals from seed crystals on insulating films, a method has been proposed in which polycrystalline material is melted and recrystallized using a linear heating source, and some success has been reported. However, studies by the present inventors have shown that other crystals may be formed from the walls of the insulating film during the process, or the insulating film may dissolve, and for example, oxygen or nitrogen may be dissolved excessively or may precipitate. It has been revealed that the quality of single crystals is very poor. Furthermore, since it is melted, it has the disadvantage that the surface fluctuates and growth stripes with unevenness are formed.

又、１４００℃を越える温度に基板を局所的にかなりの
時間さらすため、基板に大きな歪が残シ、破損し易すい
などの欠点も有している。Furthermore, since the substrate is locally exposed to temperatures exceeding 1400° C. for a considerable period of time, it also has drawbacks such as leaving large strains on the substrate and being easily damaged.

ビームアニール技術によっても多結晶の熔融。Polycrystalline melting is also achieved by beam annealing technology.

再結晶化によって、絶縁膜上に単結晶を形成できるが、
結晶品質が悪く、表面には大きな凹凸が形成される等の
問題が生じている。又、この方法は基板に対する熱歪も
非常に大きいとともに、開口部や絶縁部での加熱条件が
大巾に異なる等のため結晶性が悪いといった欠点もある
。Recrystallization can form a single crystal on an insulating film, but
Problems such as poor crystal quality and the formation of large irregularities on the surface occur. Further, this method has the disadvantage that the thermal strain on the substrate is very large, and the crystallinity is poor because the heating conditions at the opening and the insulating section are widely different.

発明の目的 本発明は、良好な単結晶域を絶縁膜下に形成し、超高速
化素子の実現しうる基板を提供するとともに、同時に低
温処理にょシ、絶縁膜下の半導体基板にも単体素子を形
成しておくことが可能となシ、良質の特性をもつ素子と
の組み合せができ、合理的な半導体装置を製造すること
ができる半導体装置用基板の製造方法を提供するもので
ある。Purpose of the Invention The present invention provides a substrate on which an ultra-high-speed device can be realized by forming a good single crystal region under an insulating film. The present invention provides a method for manufacturing a substrate for a semiconductor device, in which a semiconductor device can be formed in advance, and can be combined with elements having good quality characteristics to manufacture a rational semiconductor device.

発明の構成 本発明は、半導体基板の絶縁膜上に開口部を形成し、エ
ピタキシャル法により開口部に単結晶領域を形成し絶縁
膜上には多結晶部を形成したのち、イオン注入法により
多結晶部を非晶質化するとともに、単結晶領域と基板界
面には非晶質化を及ぼさず単結晶領域の非晶質化はその
表面部分のみとし、線状のエネルギー照射により非晶質
部分を熔融せずに単結晶化するもので、単結晶化が第１
図のごとく基板１から生じることなく単結晶領域がら住
することにょシ、良質の単結晶を基板ならびに絶縁膜上
に形成する方法である。Structure of the Invention The present invention involves forming an opening on an insulating film of a semiconductor substrate, forming a single crystal region in the opening by an epitaxial method, forming a polycrystalline region on the insulating film, and then forming a polycrystalline region by an ion implantation method. In addition to making the crystal part amorphous, the interface between the single crystal region and the substrate is not made amorphous, and the amorphization of the single crystal region is limited to the surface part, and the amorphous part is made by linear energy irradiation. Single crystallization is performed without melting, and single crystallization is the first
As shown in the figure, this is a method for forming a high-quality single crystal on a substrate and an insulating film, in which the single crystal does not originate from the substrate 1 but resides in the single crystal region.

実施例の説明 以下本発明の方法を図面とともに詳細に説明する０ 本発明は固相エピタキシャル法を用いるものである。本
発明では、断面を第２図に示すように１絶縁膜３上に形
成される多結晶部７は、たとえばシリコン単結晶基板１
上の開口部２にエビ的に形成される単結晶部８の厚さよ
シ一般に薄く形成される０しかるのち、イオン９をセル
フイオン注入により注入し、非晶質化を行う。このとき
、絶縁膜ｓ上の多結晶部を完全に非晶質化しても、非晶
質領域は開口部２の単結晶部８と基板１の界面５まで到
達せず、その下の基板１に損傷を与えることなく、基板
１のその部所に素子が組み込まれても何らの影響を与え
ない。DESCRIPTION OF EMBODIMENTS The method of the present invention will be described in detail below with reference to the drawings.The present invention uses a solid phase epitaxial method. In the present invention, the polycrystalline portion 7 formed on one insulating film 3, as shown in cross section in FIG.
After that, ions 9 are injected by self-ion implantation to make it amorphous. At this time, even if the polycrystalline portion on the insulating film s is completely amorphous, the amorphous region does not reach the interface 5 between the single crystal portion 8 of the opening 2 and the substrate 1, and the substrate 1 below Even if the element is incorporated in that part of the substrate 1 without causing any damage, it will not have any effect.

次に、この状態で第３図のごとく線状のエネルギー源（
線ビーム）１１、例えばタングステンフィラメントから
のビームによって加熱し、その直下を加熱し、その部分
の非晶質部を熔融することなく結晶化してゆく。このと
き単結晶化は部分っの付近から生じる。第３図では基板
１．絶縁Ｍ３のみを示し、その上の非晶質部、単結晶部
は省略している。線ビーム１１を少しずつ移動してゆく
ことによって、固相エビを横方向へ移動せしめる。Next, in this state, as shown in Figure 3, a linear energy source (
A beam from a tungsten filament (ray beam) 11, for example, is used to heat the area immediately below the beam, and the amorphous portion of that area is crystallized without melting. At this time, single crystallization occurs near the part. In FIG. 3, substrate 1. Only the insulation M3 is shown, and the amorphous portion and single crystal portion thereon are omitted. By moving the line beam 11 little by little, the solid shrimp is moved laterally.

この時には、第１図に示すように５〜１０μｍ程度矢印
の方向へ結晶が成長した点で下の基板１の界面よシ核形
成が突然性ずるが、本発明では基板１からでなく基板か
ら遠い基板上の部分１０の付近から生ずる。さらに本発
明では望ましくは第３図に示すように線ビーム１１をゆ
っく９と移動せしめる方位に沿って、連続した開口２を
設ける。At this time, as shown in FIG. 1, the nucleation occurs suddenly at the interface of the substrate 1 below at the point where the crystal has grown about 5 to 10 μm in the direction of the arrow, but in the present invention, the nucleation occurs not from the substrate 1 but from the substrate It originates from the vicinity of portion 10 on the far substrate. Furthermore, in the present invention, as shown in FIG. 3, continuous openings 2 are preferably provided along the direction in which the line beam 11 is slowly moved 9.

そしてそれらの開口間の巾を１０μｍ以下にしておく。The width between these openings is set to 10 μm or less.

最初の固相結晶成長は例えば基板１の上方の２ａ部で生
じ、それが横方向に成長してゆく。The first solid-phase crystal growth occurs, for example, in the upper portion 2a of the substrate 1, and then grows laterally.

この時、側面２ｂからも固相成長が同時に生ずるために
、６〜１０μｍ程度の結晶成長の後に生じている前述の
ような突然の好ましくない核形成を抑制する。従って、
全域を低温で単結晶化することができる。At this time, since solid phase growth occurs simultaneously from the side surface 2b, sudden undesirable nucleation as described above that occurs after crystal growth of about 6 to 10 μm is suppressed. Therefore,
The entire area can be single crystallized at low temperatures.

さらに、また第３図にポすように、格子状に開口部を設
けることによって、さらに完全に単結晶化した良質の結
晶基板を形成できる。これは、非常にわずかの突然の異
方向の核形成が万−生じても、線ビームが例えば開口部
２ｃを通過することによって、新たにその開口部を核と
して、再び元の方位の固相エピが再開するからである。Furthermore, as shown in FIG. 3, by providing openings in a lattice pattern, it is possible to form a high-quality crystal substrate that is more completely single-crystalline. This means that even if a very small amount of sudden nucleation occurs in a different direction, the line beam will pass through the aperture 2c, for example, and will form a new solid phase with the aperture as the nucleus again. This is because the episode will restart.

又、このような固相エピを生じしめるのは、基板（ウェ
ハー）の極〈一部あればよい。即ち、第５図に示すよう
に、−テップの一部であればよい。Furthermore, it is only necessary to cause such solid-phase epitaxial growth at a very small portion of the substrate (wafer). That is, as shown in FIG. 5, it is sufficient if it is a part of the -step.

開口部をかねたスクライプライン２１で囲まれたテップ
内に、上述したような開口部２を有した絶縁部３を形成
し、この上に結晶化層をさらに形成すれば、この絶縁部
３上だけＳ○工構造となる。If an insulating part 3 having an opening 2 as described above is formed in the tip surrounded by a scribe line 21 which also serves as an opening, and a crystallized layer is further formed on this insulating part 3, Only S○ construction will be used.

したがって、この部分に高速を要する半導体素子を形成
し、厳しいリークや耐圧特性などが必要とされる素子を
エビ成長したより完全な単結晶域である開口部２上に構
成すれば、両者の特性を最大限に活かした良質の半導体
装置が形成される。Therefore, if a semiconductor element that requires high speed is formed in this part, and an element that requires severe leakage and voltage resistance characteristics is formed on the opening 2, which is a more perfect single crystal region grown with shrimp, it is possible to achieve both characteristics. A high-quality semiconductor device that takes full advantage of this is formed.

さらに、エビ成長にょシ単結晶部８．多結晶部７をする
時に、通常のエビ成長のよう１Ｃ１０５０−１１５０℃
の温度でなく、６ｏｏ’ｃから７５０℃でエビ成長が可
能な荷電粒子蒸着を行えば、低温処理であるため、例え
ば、上述の絶縁膜３の下にも素子を形成しておくことが
できる等の長所がある。Furthermore, the single crystal part 8 for shrimp growth. When forming the polycrystalline part 7, the temperature is 1C 1050-1150℃ like normal shrimp growth.
If charged particle deposition is performed at a temperature of 60°C to 750°C, which allows shrimp growth, instead of at a temperature of There are advantages such as

この時の加速電圧としては、通常５００Ｖ望ましくは３
〜７ＫＶもあればよい。The accelerating voltage at this time is usually 500V, preferably 3
~7KV is sufficient.

さらに、本発明の方法によれば、固相エピであるため、
従来のように１４２０℃を大巾に上回る温度が必要でな
く、高々、５００℃高くとも９００℃で良いため、基板
の一部にすでに素子が組み込まれていても、好ましくな
い拡散を生じしめるなどの欠点もない。Furthermore, according to the method of the present invention, since it is a solid phase epitaxial method,
There is no need for a temperature that greatly exceeds 1420°C as in the past, and a temperature of at most 500°C and 900°C is sufficient, so even if an element is already incorporated in a part of the substrate, undesirable diffusion may occur. There are no drawbacks.

本発明の効果をンリコン基板を例にとって第６図ととも
に説明する。（１００）シリコンウェハー１上に、絶縁
酸化膜３を０．５μｍ形成した後、第３図に示すような
パターンを通常の露光方法で形成し、開口部２を設けた
。開口部２の巾は約３μｍ全体の大きさは３×４ｍｍで
あり、絶縁膜３の巾は約１０μｍであった。この上に、
電子ビーム蒸発を行ってンリコン半導体層を形成し単結
晶部８多結晶膜７を形成した。この時、電子イオンシャ
ワーを用い、一部を荷電粒子として加速し、電圧５９０
Ｖをかけた。なお基板温度は７６０℃である。得られた
膜を希弗酸液によシ、エツチングした所、開口部２上で
はエツチングは殆んど生ぜず、−穴、絶縁膜３上では約
１０ＯＡ／ｍｉｎであることが分った。従って、第６図
（ａ）にも示すように開口部２上には単結晶部８が絶縁
膜３上には多結晶膜７が形成されていることが示されて
いる。この試料に対して、第６図（ｂ）に示すようにさ
らにＳ１イオン９を３００　ＫｅＶで１０１５ケ／ｃｒ
ｌ　　注入し、表面層を完生に非晶質化して非晶質層３
０とした。The effects of the present invention will be explained with reference to FIG. 6, taking a silicon substrate as an example. (100) After forming an insulating oxide film 3 with a thickness of 0.5 μm on a silicon wafer 1, a pattern as shown in FIG. 3 was formed by a normal exposure method, and an opening 2 was formed. The width of the opening 2 was about 3 μm, the overall size was 3×4 mm, and the width of the insulating film 3 was about 10 μm. On top of this
A silicon semiconductor layer was formed by electron beam evaporation, and a single crystal part 8 and a polycrystalline film 7 were formed. At this time, an electron ion shower is used to accelerate some of them as charged particles, and a voltage of 590
I applied V. Note that the substrate temperature was 760°C. When the obtained film was etched with a dilute hydrofluoric acid solution, it was found that almost no etching occurred on the opening 2, and that on the -hole and the insulating film 3, the etching rate was about 10 OA/min. Therefore, as shown in FIG. 6(a), a single crystal portion 8 is formed on the opening 2, and a polycrystalline film 7 is formed on the insulating film 3. To this sample, as shown in FIG. 6(b), S1 ions 9 were further irradiated with 1015 ions/cr at 300 KeV.
l to completely amorphize the surface layer and form an amorphous layer 3.
It was set to 0.

次に、試料を２５０’Ｃに加熱しながら、巾０．５−１
長さ１００　ｍｍのスリットよシ全光束を出すよう反射
板をもった１ＫＷのハロゲンランプを、第３図に示すよ
うに３　ｍｍ　／　ＳｅＣで移動させた。第６図（Ｃ）
に示すよう鈍加熱ビーム１１によシ、固相エピが生じ矢
印３１のように単結晶が成長し単結晶領域３２が形成さ
れる。得られた試料を前述のように希弗酸でエツチング
した所、エツチング速度は殆んどＯであった。さらに、
異方性エツチング液でテストした所、四角錐が全面に生
じ、方位が基板と同じ（１００）になっていることが認
められた。Next, while heating the sample to 250'C,
A 1 KW halogen lamp equipped with a reflector so as to emit a total luminous flux through a slit with a length of 100 mm was moved at a rate of 3 mm/SeC as shown in FIG. Figure 6 (C)
As shown in FIG. 3, solid phase epitaxial growth occurs due to the blunt heating beam 11, and a single crystal grows as shown by an arrow 31, forming a single crystal region 32. When the obtained sample was etched with dilute hydrofluoric acid as described above, the etching rate was almost O. moreover,
When tested using an anisotropic etching solution, it was found that quadrangular pyramids were formed over the entire surface, and the orientation was the same (100) as that of the substrate.

なお、これらのエツチングによって、多結晶体などで見
られる粒界は全く認められなかったことから、第６図（
ｄ）に示すように表面層全面が良好な単結晶層３２にな
っていることが分った。Furthermore, as a result of these etchings, no grain boundaries found in polycrystals were observed, as shown in Figure 6 (
As shown in d), it was found that the entire surface layer was a good single crystal layer 32.

次に第５図に示すようなパターンを用い同じ処理を行っ
た。この時、絶縁膜３と広域の開口部２にあらかじめ拡
散の速いボロンを深さ０．１μｍにイオン注入しておい
た。Next, the same process was performed using a pattern as shown in FIG. At this time, fast-diffusing boron ions were implanted in advance into the insulating film 3 and the wide opening 2 to a depth of 0.1 μm.

得られた試料表面は、前述の試料と同様に全域が良好な
単結晶になっていた。その方位は（１１１）に一致して
いた。次にＳＩＭＳによシ、ボロンの拡散を調べた所、
全く移動していないことが分った。The entire surface of the obtained sample was a good single crystal, similar to the sample described above. Its orientation coincided with (111). Next, we investigated the diffusion of boron using SIMS.
It turned out that it wasn't moving at all.

低温で行う同相エビの効果が確認された。The effectiveness of in-phase shrimp at low temperatures was confirmed.

次に同様に（１１１）シリコンを用い、１０００℃で行
う減圧エビ成長を行った。その他処理条件は前述の通シ
である。この場合においても、（１１１）に結晶面を出
した良好な単結晶が全域に生じているのが認められた。Next, vacuum shrimp growth was performed at 1000° C. using (111) silicon in the same manner. Other processing conditions are as described above. In this case as well, it was observed that a good single crystal with a (111) crystal plane was formed over the entire area.

発明の効果 本発明の方法によって、方位の制御された良質の単結晶
が、基板全面にわたって、しかも絶縁膜。Effects of the Invention By the method of the present invention, a high-quality single crystal with a controlled orientation can be grown over the entire surface of the substrate, and even as an insulating film.

開口部を問わず、簡便に形成された。しかも固相エビの
ため低温で行うことができ、熱歪も少なく、又、消費エ
ネルギーも少ない。従って、あらかじめ導入した不純物
の拡散も生じないため、素子があらかじめ存在していて
も害を与えない長所がある。さらに開口部の基板界面は
エビ成長したままであシ、必らずしも非晶質化させない
ので、あらかじめこの開口部に素子が存在しても、イオ
ン注入などによる損傷を受けることもなく、又、欠陥が
生ずることがない。以上のように、本発明の方法は、半
導体装置用基板の製造にとって種々の優れた特長を有し
ている。It can be easily formed regardless of the opening. Moreover, since the shrimp is in a solid phase, it can be carried out at low temperatures, with little thermal distortion and low energy consumption. Therefore, there is no diffusion of impurities introduced in advance, so there is an advantage that even if the element is present in advance, it will not cause any harm. Furthermore, the substrate interface at the opening remains overgrown and does not necessarily become amorphous, so even if an element exists in the opening, it will not be damaged by ion implantation, etc. Moreover, no defects occur. As described above, the method of the present invention has various excellent features for manufacturing substrates for semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の単結晶化方法を示す断面図、第２図は本
発明の単結晶化方法を示す断面図、第３図は本発明にお
ける単結晶化方法におけるエネルギー照射状態を示す平
面図、第４図は本発明における下地基板の一例を示す平
面図、第５図は本発明における下地基板の他の例を示す
部分平面図、第６図（ａ）〜（ｄ）は本発明を用いた単
結晶化方法の具体例の工程断面図である。 １・・・・・半導体基板、２・・・・・・開口部、３・
・・・・・絶縁膜、７・・・・多結晶部、８，３２・・
・・・・単結晶部、９・・・・・・注入イオン、３０・
・・・・・非晶質部。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名Ｆ＋
　　　　　　　　　　　　　　　　Ｑう綜　　　　　　
　　　味 区　　　　　　　区 寸　　　　　　　　　　０ 味　　　　　　　味FIG. 1 is a cross-sectional view showing the conventional single crystallization method, FIG. 2 is a cross-sectional view showing the single crystallization method of the present invention, and FIG. 3 is a plan view showing the energy irradiation state in the single crystallization method of the present invention. , FIG. 4 is a plan view showing an example of the base substrate according to the present invention, FIG. 5 is a partial plan view showing another example of the base substrate according to the present invention, and FIGS. It is a process cross-sectional view of a specific example of the single crystallization method used. 1... Semiconductor substrate, 2... Opening, 3...
...Insulating film, 7... Polycrystalline part, 8, 32...
... Single crystal part, 9 ... Implanted ions, 30.
...Amorphous part. Name of agent: Patent attorney Toshio Nakao and one other person F+
Q
taste ward ward size 0 taste taste

Claims (4)

【特許請求の範囲】[Claims] （１）半導体基板上の絶縁膜に連続した開口部を設ける
工程と、エピタキシャル成長によシ少なくとう虱 も開口部に単結晶部を成長させ前記絶縁膜上に非単結晶
部を形成する工程と、イオン注入によシ、少なくとも前
記開口部以外の絶縁膜上の多結晶部を非晶質化する工程
と、エネルギー照射を一端から移動せしめて、非晶質層
を熔融せず単結晶化する工程とを含むことを特徴とした
半導体装置用基板の製造方法。(1) A step of providing a continuous opening in an insulating film on a semiconductor substrate, and a step of growing at least a single crystal part in the opening by epitaxial growth to form a non-single crystal part on the insulating film. , a process of amorphizing at least the polycrystalline part on the insulating film other than the opening by ion implantation, and moving the energy irradiation from one end to make the amorphous layer into a single crystal without melting it. A method of manufacturing a substrate for a semiconductor device, the method comprising: （２）　　エピタキシャル成長を、加速した荷電粒子を
蒸着することによって行うことを特徴とする特許請求の
範囲第１項に記載の半導体装置用基板の製造方法。(2) The method for manufacturing a substrate for a semiconductor device according to claim 1, wherein the epitaxial growth is performed by depositing accelerated charged particles. （３）線状のエネルギー照射を行う時、その移動方向に
沿って開口部が連続していることを特徴とする特許請求
の範ｊ」第１項に記載の半導体装置用基板の製造方法。(3) The method for manufacturing a substrate for a semiconductor device according to claim 1, wherein the opening is continuous along the moving direction when linear energy irradiation is performed. （４）連続した開口部が格子状になっていることを特徴
とする特許請求の範囲第１項に記載の半導体装置用基板
の製造方法。(4) The method for manufacturing a substrate for a semiconductor device according to claim 1, wherein the continuous openings are arranged in a lattice shape.
JP57212219A 1982-12-02 1982-12-02 Manufacture of substrate for semiconductor device Pending JPS59101822A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57212219A JPS59101822A (en) 1982-12-02 1982-12-02 Manufacture of substrate for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57212219A JPS59101822A (en) 1982-12-02 1982-12-02 Manufacture of substrate for semiconductor device

Publications (1)

Publication Number Publication Date
JPS59101822A true JPS59101822A (en) 1984-06-12

Family

ID=16618909

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57212219A Pending JPS59101822A (en) 1982-12-02 1982-12-02 Manufacture of substrate for semiconductor device

Country Status (1)

Country Link
JP (1) JPS59101822A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61245517A (en) * 1985-04-23 1986-10-31 Agency Of Ind Science & Technol Formation of soi crystal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61245517A (en) * 1985-04-23 1986-10-31 Agency Of Ind Science & Technol Formation of soi crystal

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