JPS61201414A - Manufacture of semiconductor single crystal layer - Google Patents

Manufacture of semiconductor single crystal layer

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Publication number
JPS61201414A
JPS61201414A JP60040323A JP4032385A JPS61201414A JP S61201414 A JPS61201414 A JP S61201414A JP 60040323 A JP60040323 A JP 60040323A JP 4032385 A JP4032385 A JP 4032385A JP S61201414 A JPS61201414 A JP S61201414A
Authority
JP
Japan
Prior art keywords
film
silicon
single crystal
semiconductor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60040323A
Other languages
Japanese (ja)
Other versions
JPH0334847B2 (en
Inventor
Tomoyasu Inoue
井上　知泰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP60040323A priority Critical patent/JPS61201414A/en
Publication of JPS61201414A publication Critical patent/JPS61201414A/en
Publication of JPH0334847B2 publication Critical patent/JPH0334847B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
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    • H01L21/02502—Layer structure consisting of two layers
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02494—Structure
    • H01L21/02513—Microstructure
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To melt a semiconductor film on a seed part and on an insulation film properly even if there is a temperature difference between the seed parts and the insulation film by lowering the melting point of the part of the semiconductor film on the seed part. CONSTITUTION:An SiO2 film 12 is formed on a single crystal silicon substrate 11 of surface orientation (100). A part of the SiO2 film 12, which is to be a seed part, is removed to form an aperture 13. In order to remove a natural oxide film and contaminants on the exposed surface of the silicon substrate 11, the silicon substrate 11 is cleansed in HF solution and dried. Immediately after that, a polycrystalline silicon film 14 is formed on the whole surface by heat decomposition of SiH4. Then a germanium layer (material layer) 15 is formed. Leaving the germanium layer 15 on the aperture 13, other part of the germanium layer is removed. Then an SiO2 film 16 is formed as a surface protection film. With this constitution, the melting point of the silicon on the aperture is lowered compared to that of the silicon on the SiO2 film 12 so that it is facilitated to meld the silicon on the aperture 13 and the silicon on the SiO2 film 12 at proper temperature.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体単結晶層の製造方法に係わり、特に絶
縁膜上にシリコンの単結晶層を形成する半導体単結晶層
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor single crystal layer, and particularly to a method for manufacturing a semiconductor single crystal layer in which a silicon single crystal layer is formed on an insulating film.

（発明の技術的背景とその問題点） 近年、半導体工業の分野では、電子ビームやレーザビー
ムによるアニールで絶縁膜上にシリコン単結晶層を形成
する、所謂Ｓ　ＯＩ　（Ｓ　１ｌｉｃｏｎ　ｏｎｌ　ｎ
５ｕｌａｔｏｒ）技術の研究開発が盛んに行われている
。また、Ｓｏｌ技術を利用して素子を３次元的に形成す
る、所！ｉ！１３次元ＩＣの開発も進められている。(Technical background of the invention and its problems) In recent years, in the field of semiconductor industry, so-called SOI (S OI), which forms a silicon single crystal layer on an insulating film by annealing with electron beams or laser beams, has been developed.
5ulator) technology is actively being researched and developed. In addition, we are using Sol technology to form elements three-dimensionally! i! Development of 13-dimensional IC is also progressing.

絶縁股上にシリコン単結晶層を形成する技術の一つとし
て従来、第４図に示すような方法が提案されている。こ
の方法では、シリコン基板４１上に開孔部４３を持つ絶
縁膜４２を形成し、続いて多結晶若しくは非晶質のシリ
コンＩｔ！４４を全面に形成する。次いで、これを電子
ビーム或いはレーザビームで順次溶融・固化していくこ
とによって、ビーム照射された部分を単結晶化する。こ
の場合、開孔部４３ではシリコン膜４４がシリコン基板
４１と直接接触しているので、基板４１から縦方向及び
それに続いて横方向にエピタキシャル成長が進行し、接
触部分の方位情報が絶縁ｌｌ１４２上に成長する単結晶
層に与えられる。As one of the techniques for forming a silicon single crystal layer on an insulating layer, a method as shown in FIG. 4 has been proposed. In this method, an insulating film 42 having an opening 43 is formed on a silicon substrate 41, and then polycrystalline or amorphous silicon It! 44 is formed on the entire surface. Next, by successively melting and solidifying this with an electron beam or a laser beam, the beam irradiated portion is turned into a single crystal. In this case, since the silicon film 44 is in direct contact with the silicon substrate 41 in the opening 43, epitaxial growth progresses from the substrate 41 in the vertical direction and subsequently in the lateral direction, and the orientation information of the contact portion is transferred onto the insulator 142. given to the growing single crystal layer.

しかしながら、この種の方法にあっては次のような問題
があった。即ち、シリコンと絶縁膜例えばシリコン酸化
層との熱伝導度を比較すると、シリコンの熱伝導性の方
が遥かに良好である。この熱伝導度の違いにより、開孔
部４３上と絶縁１１４２上とで熱抵抗が異なり、シード
部（開孔部）の熱抵抗の方が小さくなる。これは、前記
第４図にも示す如く、シード部における熱拡散が絶縁膜
４２上のそれより大きくなるからである。このため、絶
縁膜４２上のシリコンを溶融するのに適切なエネルギー
では、シード部のシリコンが溶融しない場合がある。ま
た、シード部を適切に溶融させるエネルギーでは、絶縁
膜４２上のシリコンが過度に加熱され蒸発してしまう虞
れがある。このように、シード部と絶縁膜上の半導体部
分を共に適切に溶融させることは困難であった。However, this type of method has the following problems. That is, when comparing the thermal conductivity of silicon and an insulating film such as a silicon oxide layer, silicon has a much better thermal conductivity. Due to this difference in thermal conductivity, the thermal resistance differs between the openings 43 and the insulation 1142, and the seed section (openings) has a smaller thermal resistance. This is because, as shown in FIG. 4, the thermal diffusion in the seed portion is greater than that on the insulating film 42. Therefore, even with energy suitable for melting the silicon on the insulating film 42, the silicon in the seed portion may not be melted. Furthermore, with the energy required to properly melt the seed portion, there is a risk that the silicon on the insulating film 42 will be excessively heated and evaporated. As described above, it has been difficult to appropriately melt both the seed portion and the semiconductor portion on the insulating film.

一方、上記の問題を解決する手法として最近、半導体膜
の上部に高融点金属層を配置させて２次元面内の熱拡散
を促進させる方法、或いは半導体膜の上部にＳｉＯ２，
８ｉ３Ｎ＋等の保護絶縁膜を被着させて絶縁膜上の半導
体膜が過度に加熱された時の蒸発を抑制する方法等が試
みられている。On the other hand, recently, as a method to solve the above problem, a method has been proposed in which a high melting point metal layer is placed on top of the semiconductor film to promote thermal diffusion in a two-dimensional plane, or a method in which SiO2,
Attempts have been made to deposit a protective insulating film such as 8i3N+ to suppress evaporation when the semiconductor film on the insulating film is excessively heated.

しかしながら、上記の方法にあっても半導体膜を一様に
溶融・再凝固させ、清らかな表面形状を得ると共に、大
面積の単結晶層を得ることは困難であった。However, even with the above method, it is difficult to uniformly melt and resolidify a semiconductor film, obtain a clean surface shape, and obtain a large-area single crystal layer.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、絶縁膜上とシード部上との熱抵抗の違
いに起因する問題を解決し、横方向シーディングエピタ
キシャル成長を容易に行うことができ、絶縁膜上に大面
積の単結晶層を形成し得る半導体単結晶層の製造方法を
提供することにある。An object of the present invention is to solve the problem caused by the difference in thermal resistance between the insulating film and the seed part, to easily perform lateral seeding epitaxial growth, and to provide a large-area single crystal layer on the insulating film. An object of the present invention is to provide a method for manufacturing a semiconductor single crystal layer that can form a semiconductor single crystal layer.

〔発明の概要〕[Summary of the invention]

本発明の骨子は、シード部の半導体膜の融点を下げるこ
とにより、シード部と絶縁膜上とで温度差が生じても両
者の半導体膜の溶融を適切に行うことにある。The gist of the present invention is to lower the melting point of the semiconductor film in the seed part so that even if there is a temperature difference between the seed part and the insulating film, both semiconductor films can be appropriately melted.

即ち本発明は、絶縁膜上に半導体単結晶層を形成する半
導体単結晶の製造方法において、半導体基板上に一部開
孔部を有する絶縁膜を形成したのち、上記開孔部及び絶
縁膜上に半導体膜を堆積し、さらに前記開孔部の半導体
膜の上及び下の少なくとも一方に該半導体膜より融点の
低い物質層を形成し、しかるのち前記半導体膜を帯溶融
して単結晶化するようにした方法である。That is, the present invention provides a method for manufacturing a semiconductor single crystal in which a semiconductor single crystal layer is formed on an insulating film. A semiconductor film is deposited on the semiconductor film, and a layer of material having a melting point lower than that of the semiconductor film is formed on at least one of the upper and lower sides of the semiconductor film in the opening, and then the semiconductor film is melted into a single crystal. This is how I did it.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、シード部に半導体膜より融点の低い°
物質層を設けることにより、シード部の半導体膜の融点
を低下させることができるので、シード部が絶縁膜上よ
りも低い温度であっても、この部分の半導体膜を絶縁膜
上のそれと同様に溶融させることができる。即ち、シー
ド部及び絶縁膜上の半導体膜を共に適切に溶融させるこ
とができる。このため、シード部及び絶縁膜上の半導体
膜を連続的に清らかに溶融・再凝固させることができる
。特に、シード部の溶融を容易に行うことができ、そこ
から絶縁膜上の半導体膜への横方向エピタキシャル成長
が円滑に行えるようになる。この効果は、絶縁膜の厚み
が大きい場合（例えば１μｍ以上）で特に顕著であり、
従来技術の限界（約１．３μｍ程度）以上の絶縁膜の厚
みにおいても単結晶化が容易となる。また、この効果に
より、結晶粒界の発生を抑制することができ、単結晶層
の大面積形成とその結晶品質の向上が実現できる。According to the present invention, the seed portion has a film having a melting point lower than that of the semiconductor film.
By providing a material layer, the melting point of the semiconductor film in the seed part can be lowered, so even if the temperature of the seed part is lower than that on the insulating film, the semiconductor film in this part can be made to be similar to that on the insulating film. Can be melted. That is, both the seed portion and the semiconductor film on the insulating film can be appropriately melted. Therefore, the semiconductor film on the seed portion and the insulating film can be continuously and clearly melted and resolidified. In particular, the seed portion can be easily melted, and lateral epitaxial growth onto the semiconductor film on the insulating film can be smoothly performed from there. This effect is particularly noticeable when the thickness of the insulating film is large (for example, 1 μm or more),
Even when the thickness of the insulating film exceeds the limit of the conventional technology (approximately 1.3 μm), single crystallization becomes easy. Moreover, this effect makes it possible to suppress the occurrence of grain boundaries, thereby realizing formation of a large area single crystal layer and improvement of its crystal quality.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の詳細を図示の実施例によって説明する。 Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

第１図（ａ）〜（ｄ）は本発明の一実施例方法に係わる
シリコン単結晶層製造工程を示す断面口である。まず、
第１図（ａ）に示す如く面方位（１００）の単結晶シリ
コン基板（半導体基板）１１上にＣＶＤ法により厚さ１
．５　［μｍｌの５ｉ０２）！１２を堆積し、通常のフ
ォトエツチング法により幅２［μｍ］のシード部とすべ
き部分を除去して開孔部１３を形成した。FIGS. 1(a) to 1(d) are cross-sectional views showing a silicon single crystal layer manufacturing process according to an embodiment of the present invention. first,
As shown in FIG. 1(a), a film with a thickness of 1 cm is deposited on a single crystal silicon substrate (semiconductor substrate) 11 with a plane orientation (100) by CVD.
．． 5 [μml of 5i02)! 12 was deposited, and a portion having a width of 2 [μm] that was to be a seed portion was removed by a normal photoetching method to form an opening portion 13.

次いで、シリコン基板１１の露出部表面の自然酸化膜を
及び汚染物質を除去するために、Ｈ２ＳＯ４＋Ｈ２Ｏ２
混合液及び純水で希釈したＨＦ溶液中で該基板１１を洗
浄し、乾燥させた。Next, in order to remove the native oxide film and contaminants on the exposed surface of the silicon substrate 11, H2SO4 + H2O2
The substrate 11 was washed in an HF solution diluted with the mixed solution and pure water, and dried.

その後、直ちにＳ　ｉ　Ｈ４の熱分解を用いたＣＶＤ法
により、第１図（ｂ）に示す如く全面に厚さ■ ０．６Ｃμｍ〕の多結晶シリコン膜（半導体層）１４を
堆積した。Immediately thereafter, a polycrystalline silicon film (semiconductor layer) 14 with a thickness of 0.6 C .mu.m was deposited on the entire surface as shown in FIG. 1(b) by a CVD method using thermal decomposition of SiH4.

次いで、真空蒸着法により、第１図（Ｃ）に示す如くゲ
ルマニウムＭ（物質層）１５を厚さ０．４［μ７ＦＬ］
堆積し、フォトエツチング法により、開孔部１３上のゲ
ルマニウム層１５を残し、他の部分のゲルマニウム層を
除去した。続いて、第１図１）に示す如く、表面保ＩＩ
膜として厚さ０．２　［μｍ］のＳｉＯ２膜１６をＣＶ
Ｄ法により堆積した。Next, germanium M (material layer) 15 is deposited to a thickness of 0.4 [μ7FL] as shown in FIG. 1(C) by vacuum evaporation.
The germanium layer 15 was deposited on the opening 13, and the other portions of the germanium layer were removed by photoetching. Next, as shown in Figure 1 1), surface preservation II was applied.
A SiO2 film 16 with a thickness of 0.2 [μm] is used as a film by CV
Deposited by method D.

以上の手順で製作した試料を走査型電子ビームアニール
により、表面半導体層を順次溶融・再凝固させて、横方
向エピタキシャル成長させた。電子ビームは３６［ＭＨ
ｚｌの正弦波により半値幅的１５０［μ７７Ｌ］のスポ
ットビームを一方向に高速偏向することにより長さ〜１
［μｍ］に疑似的に線状化したものを用いた。この線状
化ビームを線状方向と直角な方向に走査した。走査速度
は１００　［ｍ／ｓｅａ　］　、ビーム加速電圧ハ１０
［ＫｅＶ］　、ビーム電流は３．２　［ｍＡ］とした。The sample fabricated using the above procedure was subjected to scanning electron beam annealing to sequentially melt and resolidify the surface semiconductor layer, resulting in lateral epitaxial growth. The electron beam is 36 [MH
By rapidly deflecting a spot beam with a half-width of 150 [μ77L] in one direction using a sine wave of zl, the length ~1
A pseudo-linear one was used in [μm]. This linear beam was scanned in a direction perpendicular to the linear direction. The scanning speed was 100 [m/sea], the beam acceleration voltage was 10
[KeV], and the beam current was 3.2 [mA].

この結果、５００　［μｍ］角の８０１層（シリコン１
１１１４）全域が基板１１と同一方位の単結晶層となり
、亜結晶粒界は全く存在しないことが、選択エツチング
後の表面形状の観察により明らかになった。また、シー
ド部から５ｏｔｓへの遷移領域の表面形状はなだらかに
なっており、８０１層での表面平坦度も良好で、表面凹
凸は±１００ｒ人ｊであった。As a result, 801 layers (silicon 1
1114) Observation of the surface shape after selective etching revealed that the entire area was a single crystal layer with the same orientation as the substrate 11, and there were no subgrain boundaries at all. Further, the surface shape of the transition region from the seed part to 5 ots was smooth, and the surface flatness of the 801 layer was also good, and the surface unevenness was ±100r.

ここで、前記ゲルマニウム層１５を設けたことによる効
果は、次のようにして説明される。即ち、ゲルマニウム
はシリコンよりも融点の低いものであるから、前記シリ
コン膜１４のアニールの際にシリコン膜１４とゲルマニ
ウム層１５とが反応し、該反応物の融点はシリコンのそ
れよりも低くなる。Here, the effect of providing the germanium layer 15 will be explained as follows. That is, since germanium has a lower melting point than silicon, the silicon film 14 and the germanium layer 15 react when the silicon film 14 is annealed, and the melting point of the reactant becomes lower than that of silicon.

つまり、開孔部１３のシリコン（実際にはシリコンとゲ
ルマニウムとの化合物）の融点が５ｉＱ２）１１２上の
シリコンの融点より低くなる。一方、開孔部１３と５ｔ
Ｏｚｌ！１２上とでは熱抵抗の違いにより、同一アニー
ル条件でも第２図に示す如（表面温度が異なり、開孔部
１３の方が低いものとなる。従って、このときの温度差
を前記融点の差で補償すれば、同一７ニ一ル条件であっ
ても、開孔部１３及び５ｔＯｚｌ！１２上のシリコンを
共に適正温度で溶融させることが可能となる。That is, the melting point of the silicon (actually a compound of silicon and germanium) in the opening 13 is lower than the melting point of the silicon on the 5iQ2) 112. On the other hand, the opening part 13 and 5t
Ozl! Due to the difference in thermal resistance between 12 and above, even under the same annealing conditions, the surface temperature will be different (the surface temperature will be lower at the opening 13) as shown in FIG. By compensating for this, it is possible to melt the silicon on both the opening 13 and the 5tOzl!12 at an appropriate temperature even under the same 7N1 condition.

また、開孔部１３上のゲルマニウム層１５の厚みにより
、シード部の融点は変化する。第３図はシリコン１１１
４の厚みを０．６［μｍ］としたときのゲルマニウム層
１５の厚みによる融点の変化を示したものである。この
データを利用して、Ｓｏ１層下部の表面温度差に見合っ
た融点低下量゛となるようにゲルマニウム層１５の厚さ
を制御することにより本発明の効果を最適に導くことが
できる。これを利用して２［μｍ１以上の厚みの絶縁層
に対しても、良好な単結晶膜を形成することができた。Further, the melting point of the seed portion changes depending on the thickness of the germanium layer 15 on the opening portion 13. Figure 3 shows silicon 111
4 shows the change in melting point depending on the thickness of the germanium layer 15 when the thickness of the germanium layer 15 is 0.6 [μm]. Using this data, the effects of the present invention can be optimally brought out by controlling the thickness of the germanium layer 15 so that the melting point decrease is commensurate with the surface temperature difference under the So1 layer. Utilizing this, it was possible to form a good single crystal film even for an insulating layer with a thickness of 2 μm or more.

かくして本実施例方法によれば、開孔部１３と５ｉＯｚ
膜１２上の熱抵抗の差に起因する問題を解決することが
でき、両者のシリコンを共に最適条件で溶融することが
できる。このため、ＳｉＯ２膜１２上に大面積で良質の
シリコン単結晶を作成することができる。Thus, according to the method of this embodiment, the opening 13 and the 5 iOz
The problem caused by the difference in thermal resistance on the film 12 can be solved, and both types of silicon can be melted together under optimal conditions. Therefore, a silicon single crystal of good quality can be formed on the SiO2 film 12 over a large area.

なお、本発明は上述した実施例方法に限定されるもので
はない。例えば、前記シリコンの融点降下剤としてのゲ
ルマニウム層は必ずしもシリコン膜の上部に形成する必
要はなく、ゲルマニウム層を下層とし、バターニングし
た後にシリコン膜を形成するようにしてもよい。また、
ゲルマニウムの代りには、シリコンと固溶した場合に融
点の下がる物質であればよい。例えば、Ｓｎ、Ａｇ。Note that the present invention is not limited to the method of the embodiment described above. For example, the germanium layer as a melting point depressant for silicon does not necessarily need to be formed on top of the silicon film, but the germanium layer may be used as a lower layer and the silicon film may be formed after buttering. Also,
Instead of germanium, any substance that lowers its melting point when dissolved in solid solution with silicon may be used. For example, Sn, Ag.

Ａｕ、Ｐｂ、Ｎ　ｉ、Ｃｕ、Ｆｅ、Ａｇ、Ｐｄ。Au, Pb, Ni, Cu, Fe, Ag, Pd.

ｉｎ、３ｂ等や、これらの合金を用いることも可能であ
る。さらに、物質層の寸法は開孔部の寸法と同一である
必要はなく、開孔部の寸法より多少大きくても小さくて
もよい。また、電子ビームの代りに、レーザビームを用
いることもでき、さらにカーボンストリップヒータやラ
ンプ加熱等を利用したゾーンメルティング法に適用する
ことも可能である。また、絶縁膜上に形成する半導体膜
は多結晶シリコンに限るものではなく、非晶質シリコン
でもよく、さらに他の半導体膜の単結晶化に適用するこ
とも可能である。その他、本発明の要旨を逸脱しない範
囲で、種々変形して実施することができる。It is also possible to use in, 3b, etc., and alloys thereof. Furthermore, the dimensions of the material layer need not be the same as the dimensions of the apertures, but may be somewhat larger or smaller than the dimensions of the apertures. Further, a laser beam can be used instead of an electron beam, and it is also possible to apply a zone melting method using a carbon strip heater, lamp heating, or the like. Further, the semiconductor film formed on the insulating film is not limited to polycrystalline silicon, but may be amorphous silicon, and the present invention can also be applied to single crystallization of other semiconductor films. In addition, various modifications can be made without departing from the gist of the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）〜ｌ）は本発明の一実施例方法に係わるシ
リコン単結晶層製造工程を示す断面図、第２図は開孔部
と絶縁膜上との表面温度差を示す模式図、第３図はゲル
マニウム層の膜厚に対する融点変化を示す特性図、第４
図は従来方法を説明するための断面図である。 １１・・・単結晶シリコン基板（半導体基板）、１２・
・・ＳｉＯ２膜（絶縁膜）、１３・・・開孔部、１４・
・・多結晶シリコン膜（半導体膜）、１５・・・ゲルマ
ニウム！！（物質！り、１６・・・ＳｉＯ２膜（保護絶
縁膜）。 出願人　工業技術院長　等々力　達 第２図 Ｓｏｌ肝　　植局晶テ　　　Ｓｏｌう 第３図 第４図FIGS. 1(a) to 1) are cross-sectional views showing the silicon single crystal layer manufacturing process according to an embodiment of the present invention, and FIG. 2 is a schematic diagram showing the surface temperature difference between the opening and the insulating film. , Figure 3 is a characteristic diagram showing the change in melting point with respect to the film thickness of the germanium layer, Figure 4
The figure is a sectional view for explaining a conventional method. 11... Single crystal silicon substrate (semiconductor substrate), 12.
...SiO2 film (insulating film), 13...opening part, 14.
...Polycrystalline silicon film (semiconductor film), 15...Germanium! ! (Substance! Ri, 16...SiO2 film (protective insulating film). Applicant Todoroki Director General of the Agency of Industrial Science and Technology

Claims (3)

【特許請求の範囲】[Claims] （１）半導体基板上に一部開孔部を有する絶縁膜を形成
する工程と、次いで上記開孔部及び絶縁膜上に半導体膜
を堆積する工程と、前記開孔部の半導体膜の上及び下の
少なくとも一方に該半導体膜より融点の低い物質層を形
成する工程と、次いで前記半導体膜を帯溶融して単結晶
化する工程とを含むことを特徴とする半導体単結晶層の
製造方法。(1) A step of forming an insulating film having a partial opening on a semiconductor substrate, a step of depositing a semiconductor film on the opening and the insulating film, and a step of depositing a semiconductor film on the opening and the insulating film. A method for manufacturing a semiconductor single crystal layer, comprising the steps of: forming a layer of a substance having a lower melting point than the semiconductor film on at least one of the lower sides; and then band-melting the semiconductor film to form a single crystal. （２）前記半導体基板として単結晶シリコン、前記半導
体膜として多結晶若しくは非晶質のシリコンを用いたこ
とを特徴とする特許請求の範囲第１項記載の半導体単結
晶層の製造方法。(2) The method for manufacturing a semiconductor single crystal layer according to claim 1, wherein single crystal silicon is used as the semiconductor substrate, and polycrystalline or amorphous silicon is used as the semiconductor film. （３）前記物質層として、ゲルマニウムを用いたことを
特徴とする特許請求の範囲第２項記載の半導体単結晶層
の製造方法。(3) The method for manufacturing a semiconductor single crystal layer according to claim 2, characterized in that germanium is used as the material layer.
JP60040323A 1985-03-02 1985-03-02 Manufacture of semiconductor single crystal layer Granted JPS61201414A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60040323A JPS61201414A (en) 1985-03-02 1985-03-02 Manufacture of semiconductor single crystal layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60040323A JPS61201414A (en) 1985-03-02 1985-03-02 Manufacture of semiconductor single crystal layer

Publications (2)

Publication Number Publication Date
JPS61201414A true JPS61201414A (en) 1986-09-06
JPH0334847B2 JPH0334847B2 (en) 1991-05-24

Family

ID=12577396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60040323A Granted JPS61201414A (en) 1985-03-02 1985-03-02 Manufacture of semiconductor single crystal layer

Country Status (1)

Country Link
JP (1) JPS61201414A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6336514A (en) * 1986-07-30 1988-02-17 Sony Corp Manufacture of thin single-crystal semiconductor film
JP2009231712A (en) * 2008-03-25 2009-10-08 Sumitomo Heavy Ind Ltd Laser beam machining method and semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5893222A (en) * 1981-11-30 1983-06-02 Toshiba Corp Preparation of semiconductor single crystal film
JPS58212123A (en) * 1982-06-02 1983-12-09 Hitachi Ltd Manufacture of single crystal thin film

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5893222A (en) * 1981-11-30 1983-06-02 Toshiba Corp Preparation of semiconductor single crystal film
JPS58212123A (en) * 1982-06-02 1983-12-09 Hitachi Ltd Manufacture of single crystal thin film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6336514A (en) * 1986-07-30 1988-02-17 Sony Corp Manufacture of thin single-crystal semiconductor film
JP2009231712A (en) * 2008-03-25 2009-10-08 Sumitomo Heavy Ind Ltd Laser beam machining method and semiconductor device

Also Published As

Publication number Publication date
JPH0334847B2 (en) 1991-05-24

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