JPS5961117A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS5961117A
JPS5961117A JP57171219A JP17121982A JPS5961117A JP S5961117 A JPS5961117 A JP S5961117A JP 57171219 A JP57171219 A JP 57171219A JP 17121982 A JP17121982 A JP 17121982A JP S5961117 A JPS5961117 A JP S5961117A
Authority
JP
Japan
Prior art keywords
insulating film
layer
substrate
polycrystalline
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57171219A
Other languages
Japanese (ja)
Inventor
Seiichiro Kawamura
河村　誠一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57171219A priority Critical patent/JPS5961117A/en
Publication of JPS5961117A publication Critical patent/JPS5961117A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To perform a uniform heating as well as to prevent the exfoliation of a single crystal silicon layer and also to prevent the generation of cracks and the like by a method wherein the first insulating film and a polycrystalline silicon layer are selectively formed on a single crystal silicon substrate, the second insulating film is formed on the upper surface of the region where said two layers come in contact with each other, and a laser beam is scanned on them. CONSTITUTION:The first silicon dioxide insulating film 3 isolated in island form is formed on an Si substrate 1 using a selective oxidization method, and then a non-doped polycrystalline Si layer 4 is formed on the substrate using a chemical vapor-phase growing method. Then, the first silicon nitride film 6, which covers the upper part of an element formation region 2, is provided on the polycrystalline Si layer 4, and a selective thermal oxidization is performed. A second SiO2 insulating film 7 is formed in the thickness almost equal to that of the first SiO2 insulating film 3, with which the element formation region 2 is laid out, and a continuous laser beam of carbonic acid having an absorption wavelength band of the SiO2 insulating films 3 and 7 is made to scan on the substrate.

Description

【発明の詳細な説明】 （ａｌ　　発明の技術分野 不発明け５Ｎｉｃｏｎ　Ｏｎ　Ｉｎ５ｕｌａｔｏｒ　（
ＳＯＩ　）構造の半導体装置の製造方法に係り、特に絶
縁膜上への単結晶゛シリ３フ層の成長方法に関する。[Detailed description of the invention] (al Technical field of the invention
The present invention relates to a method of manufacturing a semiconductor device having an SOI structure, and particularly to a method of growing a single crystal silicon 3 layer on an insulating film.

（ｂｌ　　技術の背景 半導体集積回路（ＩＣ）に於て、８０　Ｓ　（８１１１
ｃｏｎＯｎ’８ａｐｐｈｉｒｅ　）構造に代わるものと
して、絶縁膜上に単結晶シリコン層？形成するＳ　ＯＩ
　（Ｓｉｌ　１ｃｏｎＯｎ　Ｉｎ５ｕｌａｔｏｒ　）ｍ
ａカ提供すｔｚＴイル。(bl Technology Background In semiconductor integrated circuits (IC), 80S (8111
As an alternative to the conOn'8apphire) structure, is there a single crystal silicon layer on the insulating film? S OI to form
(Sil 1conOn In5ulator)m
I'll provide you with a copy.

この構造は、シリコン基板？使用するのでＳＯ８構造に
比べて極めて廉価で８０８構造の具備する高分離耐圧、
低寄生容量等の％’Ｊｔ’を備えたＩＣが形成できると
いう利点？持っている。Is this structure a silicon substrate? Because it is used, it is extremely inexpensive compared to the SO8 structure, and the high separation voltage that the 808 structure has,
The advantage of being able to form an IC with %'Jt' such as low parasitic capacitance? have.

そしてこの構造の更に大きな利点は、絶縁膜？介して半
導体ＩＣｉ何層も積層する三次元ＩＣの形成？可能なら
しめたことである。And the even bigger advantage of this structure is the insulating film? Formation of a three-dimensional IC by stacking multiple layers of semiconductor ICi through it? This made it possible.

（ｃｌ　　従来技術と問題点 上記ＳＯＩ構造に於ける絶縁膜上の単結晶シリコノ（Ｓ
ｉ）層は、連続波レーザ・ビーム走査によるアニール手
段音用いたラテラル・エピタキシャル−ｇ長（Ｌａｔｅ
ｒａｌ　Ｅｐｉｔａｘｉ；ＩＩ　Ｇｒｏｗｔｈ　）技術
によって形成式れる。(cl) Conventional technology and problems Single crystal silicon (S) on the insulating film in the above SOI structure
i) The layer is annealed by continuous wave laser beam scanning using lateral epitaxial-g length (Late
ral Epitaxy; II Growth) technology.

そして該技術に於て従来性われた方法では、第１図（イ
）に示すよろに単結晶Ｓｉ基板１面の素子形成が予定さ
れる領域２に島状に二酸化ン１１コン（ＳＩ０２）絶縁
膜３７形成し、該基板上に多結晶８１層４孕化学気相成
長ぜしめた後、第１図ｔ”］に示すように該基板面を連
続波（ＣＷ）アルゴン（Ａｒ　）レーザ・ビームＬ＋ａ
ｒで走青しく矢印ｍは走査方向）、多結晶Ｓｉ層４？単
結晶ＳＬ基板１面上から５ｈｏ２絶縁膜３上に向って順
次溶融することにより単結晶化し基板１間尺Ｕ：　Ｓ　
ｉ　０２絶縁膜３上に単結晶８１層５金形成していた。In the conventional method of this technology, as shown in FIG. After forming a film 37 and chemical vapor deposition of a polycrystalline 81 layer 4 on the substrate, the substrate surface is exposed to a continuous wave (CW) argon (Ar) laser beam as shown in FIG. L+a
r indicates the scanning direction; the arrow m indicates the scanning direction), and the polycrystalline Si layer 4? By sequentially melting from the top of the single crystal SL substrate 1 toward the top of the 5ho2 insulating film 3, the substrate is made into a single crystal, and the size of the substrate 1 is U: S.
A single crystal 81 layer 5 gold layer was formed on the i02 insulating film 3.

（図中４′はＳＬ溶融領域プし力）し該従来方法に於て
１ｊｓｉｏｔ絶縁膜上の単結晶８１層が剥離しやすく、
単結晶８１基板１面に分散配設ぢれているＳ　ｉ０２絶
縁膜の」二面全域にわたって欠落部、クラック等の欠陥
のない単結晶８＋ｆ＠２形成させることが非常に困難で
あるという問題があった。(4' in the figure is the SL melting region pushing force) In this conventional method, the single crystal 81 layer on the 1jsiot insulating film is likely to peel off.
The problem is that it is extremely difficult to form a single crystal 8+f@2 without any defects such as missing parts or cracks over the entire two sides of the Si02 insulating film which is dispersed and disposed on one surface of the single crystal 81 substrate. there were.

こればＡ、ｒレーザの波長が０．５［ｌ１ｍ、］程度の
短波長４有するため、Ｓ１層はこれケ良く吸収するが、
ＳｉＯ□絶縁膜が該レーザに対しで殆んど透明であるこ
とに起因する。即ち上記従来方法に於ては多結晶Ｓ１層
はそれ自体に吸収されるレーザ・工オルキにより加熱逼
れるため、熱抵抗の高いＳｉｎ！絶縁膜の上部と熱抵抗
の低い単結晶Ｓｌ基板上部との間に大きな温度差を生す
ることによる。In this case, since the wavelength of the A and r lasers has a short wavelength of about 0.5 [l1m,], the S1 layer absorbs this well, but
This is due to the fact that the SiO□ insulating film is almost transparent to the laser. That is, in the conventional method described above, the polycrystalline S1 layer is heated by the laser/orc oil absorbed by itself, so the Sin! layer has a high thermal resistance. This is because a large temperature difference is generated between the upper part of the insulating film and the upper part of the single-crystal Sl substrate having low thermal resistance.

Ｆｄｌ　　発明の目的 不発明は絶縁膜か選択的に配設された単結晶シリコン基
板上に形成した多結晶ン【３コンｆｆｌ’に、　　レー
ザ・ビーム走査により均一な温度に力口熱し単結晶化す
る方法ｉ提供するものであり、その目的とするとＣろは
上記問題点全除去し、　ＳＯＩ構造？有する半導体装置
の製造歩留まり紫向上せしめるＶＣある。Fdl Purpose of the Invention The invention is based on polycrystalline silicon formed on a monocrystalline silicon substrate on which an insulating film is selectively disposed, and heated to a uniform temperature by laser beam scanning to form a monocrystal. Is there a way to do this, and its purpose is to eliminate all of the above problems and create an SOI structure? There is a VC that can improve the manufacturing yield of semiconductor devices.

ｔｅｌ　　発明の構成 即ち不発明は半導体装置の製造方法に於て、単結晶シリ
コン基体上に選択的に第１の絶愚膜？形成し、該単結晶
ンリコン基体上に多結晶シリコン層？形成し、該多結晶
シリコン層に於ける少なくとも前記単結晶シリコン基体
に直に接する領域の上面に第２の絶縁膜葡形成し、しか
る後該基体面？連続波炭酸ガス・レーザにょυ走査して
前記多結晶シリコン層重単結晶シリコン基体上刃）ら第
１の絶縁膜上に向って順次溶融単結晶化する工程紮有す
ること全特徴とする。tel The structure of the invention, that is, the non-invention, is that in a method of manufacturing a semiconductor device, a first crystalline film is selectively formed on a single crystal silicon substrate. Form a polycrystalline silicon layer on the monocrystalline silicon substrate? A second insulating film is formed on the upper surface of at least a region of the polycrystalline silicon layer that is in direct contact with the single crystal silicon substrate, and then a second insulating film is formed on the upper surface of the polycrystalline silicon layer, and then a second insulating film is formed on the upper surface of the region of the polycrystalline silicon layer that is in direct contact with the single crystal silicon substrate. The present invention is characterized by the step of scanning the polycrystalline silicon layer with a continuous wave carbon dioxide laser to sequentially melt and single-crystallize the polycrystalline silicon layer (over the single crystal silicon substrate) onto the first insulating film.

（ｆｌ　　発明の実施例 以下本発明オー実施例について、箱２図げ）乃至１、Ｉ
−Ｉ　ＶＣ示す工程断面図ｒ用いて詳細に説明する。(fl Embodiments of the Invention Below, see Box 2 for Embodiments of the Invention) to 1, I
A detailed explanation will be given using the process cross-sectional diagram r shown in -I VC.

不発明の方法を用いて８０１ｖｔ造のＭＯ８ＩＣ２形成
するに際しては、第２図（イ）に示す、Ｊニー″ｌにシ
リコン（ｓ皿）基体例えば８ｉ基板１面に通常の選択酸
化法等・を用い島状に分離ケガた例えば浮名６Ｇ（ト）
〔入〕程度の第１の二酸化シリコン（Ｓ’（Ｊｙ）絶縁
１挨３で形成し、次いで通常の化学気相成＆　（ＣＶＩ
））法ケ用い該基板上に例えばＪ９さ５０００（λ〕径
程度ノン・ドープ多結晶Ｓ１層４全形成する口なお前記
島状Ｓ＋　（Ｊ　２絶縁膜３は素子形成領域２に配設さ
れる。When forming an MO8IC2 made of 801vt using an uninvented method, a conventional selective oxidation method or the like is applied to one side of a silicon (s plate) substrate, for example, an 8i substrate, on a J knee shown in Fig. 2 (a). For example, Ukina 6G (G)
A first silicon dioxide (S' (Jy) insulator of about
)) Using a method, for example, a non-doped polycrystalline S1 layer 4 of about 5000 (λ) diameter is entirely formed on the substrate. Ru.

仄いて紀２図（０１に示ずよろＣＣ１前記多結晶Ｓｉ層
４上に素子形成領域２の上部欠壊う累１の窒化シ１１１
　’／　（Ｓｉ、Ｎ４）膜６を設けて通常の選択熱酸化
全行い、多結晶Ｓ１層４上に素子形成領域２金画定する
７Ｈｕ）８１０．絶縁膜３とほぼ等しい厚さの第２（１
）ＳｉＯ，絶縁膜７全形成する。な２挨ｍ２の８４０．
絶縁膜７の下部には多結晶Ｓ１層４が残っていなければ
ならす、その厚ちは２０００〜３０００〔λ〕径程度望
ましい。従って第２のＳｉｎ、絶縁膜７により素子形成
領域２は画定逼れているのみで、分離されていない。2 (not shown in Fig. 01) CC1 The nitrided silicon 111 of the upper part of the element formation region 2 is broken on the polycrystalline Si layer 4.
'/ (Si, N4) film 6 is provided, normal selective thermal oxidation is carried out, and an element formation region 2 is defined on the polycrystalline S1 layer 4 (7Hu)810. The second (1
) SiO, insulating film 7 is completely formed. 840.
The polycrystalline S1 layer 4 must remain under the insulating film 7, and its thickness is preferably about 2000 to 3000 [λ] diameter. Therefore, the element formation region 2 is only defined by the second Sin insulating film 7 and is not separated.

次いで第２図Ｐｊに示すように、該基板上２ＳｉＯ。Then, as shown in FIG. 2Pj, 2SiO is deposited on the substrate.

絶縁膜３及゛び７の吸収波長帯９１〜９４〔μｍ〕に発
振波長金合わせた炭酸ガス（ＣＯｔ）の連続波レーザ・
ビームＬＣ（＋、によって走査し、該レー＋１ヶ吸収し
て昇温した第ｔ　ｏ）８　ｉ０２絶縁膜３及び第２の３
ｉ０２絶縁膜７孕介して多結晶Ｓｊ１ｍ４ｙ加熱し順次
接融して、単結晶Ｓｔ基板１上７Ｊ１ら第１Ｏ）ＳＩＯ
２絶縁膜３上に向って順次単結晶Ｓｉｔ研５ｋａ長して
行く。（図中ｍは走査方向矢印し、４′は８１溶融領域
う ｉｇこｃで多結晶Ｓ　ｉ　層４下’ｔｆ＆　Ｏｌ　第１
０．）　Ｓ　ｉ　０２絶縁膜３にレーザ・ビームが到達
するの１は、上記波長のレーザに対して８１層が透明で
あることによる。A carbon dioxide gas (COt) continuous wave laser whose oscillation wavelength is matched to the absorption wavelength band 91 to 94 [μm] of the insulating films 3 and 7.
Scanned by the beam LC(+), the ray +1 was absorbed and the temperature was increased.
The polycrystalline Sj1m4y is heated through the i02 insulating film 7 and sequentially welded to form 7J1 and 1st O) SIO on the single crystal St substrate 1.
The length of the single-crystal SIT layer is increased by 5ka toward the top of the second insulating film 3. (In the figure, m indicates an arrow in the scanning direction, and 4' indicates the 81 molten region below the polycrystalline Si layer 4'tf&Ol 1st
0. ) The reason why the laser beam reaches the S i 02 insulating film 3 is that the 81 layer is transparent to the laser of the above wavelength.

又第１のＳｉｎ、絶縁膜３と第２のｓｉｕ、絶縁膜７の
厚さケはぼ等しく形成したのは、全領域の多結晶Ｓｉ層
４ｔはぼ均一な温度に加熱するためである。The reason why the first Si, insulating film 3, second SIU, and insulating film 7 are formed to have approximately the same thickness is to heat the polycrystalline Si layer 4t over the entire region to an almost uniform temperature.

そして父上記レーザービームの強さは、所望のスポット
径の走査スピードに於て多結晶３ｉ層４が充分に溶融さ
れる強さであれば良く、上記５ｉ０２絶縁膜３及び７の
厚さ、多結晶８１層４の厚さに於て、例えばビーム・ス
ポット径約１００［μｍ〕。The intensity of the above-mentioned laser beam may be such that the polycrystalline 3i layer 4 is sufficiently melted at the scanning speed of the desired spot diameter. Regarding the thickness of the crystal 81 layer 4, for example, the beam spot diameter is about 100 [μm].

走査スピード５〜１ＯＣｃＩｒＬ／ＳｅＣ〕の場合３０
〜４０（Ｗ〕程度が適切であった。Scanning speed 5-1OCcIrL/SeC] 30
~40 (W) was appropriate.

更に又図示しないが、琳１のＳｉｎ、絶縁膜３上部の多
結晶８１層上に薄い第３＜７）ＳｉＯ，絶縁膜を形成し
たり、多結晶Ｓｉ層全全形成る際その厚さ孕基板面上と
ｍ　１　ｏ）　Ｓ　ｉ０２絶縁膜上で変えたシするＣと
により、多結晶Ｓｉ層の溶は具合？更に微妙に調節する
ことが可能である。Furthermore, although not shown in the drawings, a thin 3<7) SiO insulating film is formed on the polycrystalline 81 layer on the Sin insulating film 3, and the thickness of the polycrystalline Si layer is changed when the entire polycrystalline Si layer is formed. How is the polycrystalline Si layer melted by changing the C on the substrate surface and on the m1o) Si02 insulating film? Further fine adjustment is possible.

次いで第２図に）に示すように、上記工程により形成嘔
れた単結晶３ｉ層５上に素子形成領域２奮選択的に覆う
第２のＳｔ、Ｎ、膜８？形底し、通常の選択熱酸化？行
い、第２の８ｉ、Ｎ、ｌ＠ｓに覆われでいない領域の単
結晶Ｓｉ層全全底部で完全に酸化し、前記第２の５ｉｎ
２絶縁膜７が拡大して形ｒｌｙ、てれた第２′の５１０
２絶縁膜７１により各第１の３４０、絶縁膜３上の単結
晶ＳＩ層５間才完全に分離する。Next, as shown in FIG. 2), a second St, N, film 8 is formed to selectively cover the element formation region 2 on the single crystal 3i layer 5 that has been formed in the above steps. Shaped bottom and normal selection thermal oxidation? The entire bottom of the single crystal Si layer in the area not covered by the second 8i, N, l@s is completely oxidized, and the second 5in
2 insulating film 7 is enlarged to form rly and protruding 2'th 510
The single crystal SI layers 340 and 5 on each first insulating film 3 are completely separated by the second insulating film 71.

以後第１のＳ　ｉｏ２絶縁絶縁及３肌２′の８１０！絶
縁膜７′によって島状に分離された前記ノン・ドープ単
結晶３ｉ層５にイオン注入等の方法デ用Ｇ）て所望の導
電型？何カした後、通常のＭＯ８ＩＣの製造方法に従っ
て、第２図（ホに示すように該所望の導電型？有する各
単結晶Ｓｉ層５′面に例えば多結晶Ｓ１絶縁ゲート９及
びノース・ドレイン領域１０　ａ、　１０　ｂ　ｋ形成
し、次いで図示しないが絶縁膜の形成、電極コンタクト
窓の形成、配線形成等がな芒れでＳＯＩ構造のＭＯ８Ｉ
Ｃが提供されるＯ 彦２本発明の方法は上記実施例に限らず、基体として８
１層２用いることが可能であり、これによりＩＣが絶縁
膜を介して積層てれてなる三次元Ｉ（Ｉ＝影形成ること
ができる。After that, 1st S io2 insulation insulation and 3 skin 2' 810! G) Using a method such as ion implantation into the non-doped single crystal layer 5 separated into islands by the insulating film 7', the desired conductivity type is obtained. After several steps, a polycrystalline S1 insulated gate 9 and a north drain region are formed on the 5' surface of each single crystal Si layer having the desired conductivity type, as shown in FIG. 10a, 10bk are formed, and then, although not shown, an insulating film is formed, an electrode contact window is formed, wiring is formed, etc., to form an SOI structure MO8I.
The method of the present invention is not limited to the above embodiments, and the method of the present invention is not limited to the above embodiments.
It is possible to use one layer and two layers, thereby making it possible to form a three-dimensional I (I=shadow) in which ICs are laminated with an insulating film interposed therebetween.

ｊｇｌ　　発明の効シー 以上ｄ発明したように本発明によればＳＯＩ構造を形成
する際の多結晶〕１１コンＦ＃（１）単結晶化工程に於
て、レーザ・ビーム走査により単結晶シリコン基板にｉ
［に接する領域の多結晶７１１９７層と絶縁１換上部領
域の多結晶シリコン層とケ殆んど等しい温度にカロ熱づ
−ることかできる。jgl EFFECTS OF THE INVENTION According to the invention, according to the present invention, in the single crystallization process, a single crystal silicon substrate is formed by laser beam scanning. ni i
It is possible to heat the polycrystalline 71197 layer in the region in contact with the polycrystalline silicon layer and the polycrystalline silicon layer in the insulating upper region to almost the same temperature.

そのため上記谷狽域七の年結晶比されたシ１ノコノ層の
界面ＶＣ温度差によって発生する応力が大幅に減少し、
単結晶シリコン）→の剥１ｉｉ１ｃ　、り゛７ツク等の
欠陥が防止される。Therefore, the stress generated by the interfacial VC temperature difference of the Shi1 Nokono layer compared to the above-mentioned Tanigai area 7 is greatly reduced,
Defects such as single-crystal silicon peeling and cracking are prevented.

従って本発明は８０１構造の半導体装１１警の製造歩留
まり向上に有効である。Therefore, the present invention is effective in improving the manufacturing yield of semiconductor devices having an 801 structure.

な８本発明の技術はバイポーラＩＣにも適用できる。又
絶縁膜は二酸化シ１１コン膜に限らなＧ１゜The technology of the present invention can also be applied to bipolar ICs. In addition, the insulating film is limited to G1゜ silicon dioxide film.

【図面の簡単な説明】[Brief explanation of the drawing]

ｍ１図１−を従来ノＳＯＩ　（Ｓ　ｉ　ｌ　１ｃｏｎ　
Ｏｎ　Ｉｎ５ｕｌａｔｏｒ）構造形成方法の工程断面図
で、第２図は本発明Ｑ）方法に於ける一笑施例の工程断
面図である。 図に於て、ｌはシリコン基板、２は累子形収領域、３は
第１の二酸化シリコン絶縁膜、４は多結晶シリコンｒｍ
、ｃはシリコン溶融領域、５は単結晶シリコン層、６に
第１の窒化シリコン膜、７は第２の二酸化シリコン絶縁
膜、Ｉ、Ｃｏ２は遅絖波炭酸ガス・レーザ・ビーム、【
］ｌｊ：走査方向矢印しｔ示す。m1 Figure 1- to conventional SOI (S i l 1con
FIG. 2 is a process cross-sectional view of an example of method Q) of the present invention. In the figure, l is a silicon substrate, 2 is a reticulated storage region, 3 is a first silicon dioxide insulating film, and 4 is a polycrystalline silicon rm.
, c is a silicon melting region, 5 is a single crystal silicon layer, 6 is a first silicon nitride film, 7 is a second silicon dioxide insulating film, I, Co2 are slow wave carbon dioxide laser beams, [
]lj: Scanning direction arrow indicates t.

Claims (1)

【特許請求の範囲】[Claims] 単結晶シリコン基体上に選択的に第１の絶縁膜を形成し
、該単結晶シリコン基板上に多結晶シリコン層金形成し
、該多結晶シリコン層に於ける少なくとも前記単結晶シ
リコン基体に直に接する領域の上面に第２の絶縁膜？形
成し、シｆＪ）る後該基体面葡連続波炭酸ガス・レーザ
により走査して前記多結晶シリコン／Ｆｌ？単結晶シリ
コン基体上の１ら第１の絶、縁膜上に向って順次溶融単
結品化する工程？有することを特徴とする半導体装置の
製造方法。selectively forming a first insulating film on a single-crystal silicon substrate; forming a polycrystalline silicon layer on the single-crystal silicon substrate; A second insulating film on the top surface of the contact area? After forming and scanning the substrate surface with a continuous wave carbon dioxide laser, the polycrystalline silicon/Fl? Is it a process of sequentially melting the first insulation layer on the monocrystalline silicon substrate and turning it into a single product? A method for manufacturing a semiconductor device, comprising:
JP57171219A 1982-09-30 1982-09-30 Manufacture of semiconductor device Pending JPS5961117A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57171219A JPS5961117A (en) 1982-09-30 1982-09-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57171219A JPS5961117A (en) 1982-09-30 1982-09-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5961117A true JPS5961117A (en) 1984-04-07

Family

ID=15919244

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57171219A Pending JPS5961117A (en) 1982-09-30 1982-09-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5961117A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01183145A (en) * 1988-01-18 1989-07-20 Fujitsu Ltd Manufacture of soi semiconductor device
CN112701033A (en) * 2020-12-29 2021-04-23 济南晶正电子科技有限公司 Preparation method of composite substrate, composite substrate and composite film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01183145A (en) * 1988-01-18 1989-07-20 Fujitsu Ltd Manufacture of soi semiconductor device
CN112701033A (en) * 2020-12-29 2021-04-23 济南晶正电子科技有限公司 Preparation method of composite substrate, composite substrate and composite film
CN112701033B (en) * 2020-12-29 2022-03-15 济南晶正电子科技有限公司 Preparation method of composite substrate, composite substrate and composite film

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