JPS58180019A - Semiconductor base body and its manufacture - Google Patents

Semiconductor base body and its manufacture

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Publication number
JPS58180019A
JPS58180019A JP57063757A JP6375782A JPS58180019A JP S58180019 A JPS58180019 A JP S58180019A JP 57063757 A JP57063757 A JP 57063757A JP 6375782 A JP6375782 A JP 6375782A JP S58180019 A JPS58180019 A JP S58180019A
Authority
JP
Japan
Prior art keywords
substrate
insulating
rectangular
opening
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57063757A
Other languages
Japanese (ja)
Other versions
JPH0413848B2 (en
Inventor
Koichi Kugimiya
公一 釘宮
Shigenobu Akiyama
秋山 重信
Haruhide Fuse
玄秀 布施
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
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Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57063757A priority Critical patent/JPS58180019A/en
Publication of JPS58180019A publication Critical patent/JPS58180019A/en
Publication of JPH0413848B2 publication Critical patent/JPH0413848B2/ja
Granted legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02686Pulsed laser beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02488Insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02502Layer structure consisting of two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02598Microstructure monocrystalline
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683Continuous wave laser beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691Scanning of a beam

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To form a semiconductor element such as a high-speed type bipolar element by applying a single crystal change method for a semiconductor polycrystalline film or an amorphous film, at least one part thereof is positioned onto an insulating film and other one part thereof is in contact directly with a semiconductor substrate. CONSTITUTION:Line and space by insulating films 22 and opening sections 28 as seed crystals are formed to the substrate 21 through LOCOS oxidation by a normal method by using a rectangular mask A. The amorphous layer or the polycrystalline layer changed into a single crystal is loaded onto the whole surface on the line and space. Sections corresponding to the opening sections 25 of insulating sections are left while using a mask B through which rectangular windows are left by a # type pattern, and the insulating sections 23, 24 are formed through processes of nitriding, etc. through which the insulating sections are not oxidized into polycrystalline layers. The surface can be flattened approximately by previously etching the sections and reducing thickness to approximately half at that time. Substrate extending sections 27 as amorphous or polycrystals are changed into single crystals through the irradiation of energy beams. Either of a pulse laser, a CW laser, electron beams, infrared rays, ultraviolet rays, etc. may be used as beams irradiated, and they may be used when energy is absorbed and dissolved to the substrate extending sections 27 in a short time.

Description

【発明の詳細な説明】 本発明は一種の絶縁分離領域を搭載した半導体基体およ
びその製造方法を提供するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor body equipped with a type of isolation region and a method of manufacturing the same.

従来より絶縁分離法は半導体装置にとって非常に重要な
技術であり、特にバイポーラ素子などでは、高速化、高
密度化に伴なって、今後も益々重要となる技術と位置づ
けられている。従来は、第1図(a)に示すように半導
体基板11中へ、表面より絶縁分離層12を形成し、そ
の間に残存する領域を活性層13として素子を組み込む
。この時、高密度化のために、分離層12間の距離を縮
めるとその間に大きな応力が働き始め、結晶欠陥が生じ
、素子特性を劣化させるといった欠点や、第1図(2L
)にも示されているようにバーズビーク14が出来、分
離層12間の距離を縮小し得ない等の限界があった。こ
れに対して、第1図(b)に示すように、絶縁分離層1
2を11内部に形成する試みがなされている。例えばイ
オン注入によって酸素を深く注入し、酸化物を形成する
方法で第1図(b)の構造を形成するものであるが、注
入欠陥の残存するという欠点や大量の酸素を注入しなけ
ればならず余り現実的でないといった欠点がある。
The insulation isolation method has traditionally been a very important technology for semiconductor devices, and is positioned as a technology that will become even more important in the future, especially in bipolar devices and the like, as speeds and densities become higher. Conventionally, as shown in FIG. 1(a), an insulating separation layer 12 is formed in a semiconductor substrate 11 from the surface, and the remaining region in between is used as an active layer 13 to incorporate an element. At this time, when the distance between the separation layers 12 is shortened in order to increase the density, large stress begins to act between them, causing crystal defects and deteriorating device characteristics.
), there were limitations such as the formation of bird's beaks 14 and the inability to reduce the distance between the separation layers 12. On the other hand, as shown in FIG. 1(b), the insulating separation layer 1
Attempts have been made to form 2 inside 11. For example, the structure shown in Figure 1(b) is formed by deeply implanting oxygen by ion implantation to form an oxide, but this method has the drawback that implantation defects remain and a large amount of oxygen must be implanted. The drawback is that it is not very realistic.

他にも陽極酸イ1を利用して同様に完全絶縁分離を行う
試みもなされているが種々の問題点があり、未完成の技
術である。
Other attempts have also been made to achieve complete insulation separation using anodic acid I1, but there are various problems and the technology is still incomplete.

本発明は、このような絶縁分離層を形成する新しい方法
、及び、その方法によって高速型のノ;イボーラ素子な
どの実現をはかるものである。
The present invention aims to provide a new method for forming such an insulating separation layer, and to realize a high-speed type IBORA device using the method.

本発明の方法においては、少なくとも一部が絶縁膜上に
あり、他の一部が半導体基板に直接に接している半導体
多結晶膜ないしは非晶質膜の単結晶化法を応用している
In the method of the present invention, a single crystallization method is applied to a semiconductor polycrystalline film or an amorphous film in which at least a part is on an insulating film and the other part is in direct contact with a semiconductor substrate.

この単結晶化法については、ここ数年来、各種の提案が
なされている。以下に提案されている技術について簡単
に説明を行う。
Various proposals have been made regarding this single crystallization method over the past few years. The proposed technology will be briefly explained below.

絶縁基板(例えば5102 や5isNa )上に蝕刻
法などで残した多結晶膜を、CWやpH1seレーザア
ニール、エレクトロンビームアニールなどのいわゆるビ
ームアニール法によって、単結晶化ないしは大結晶粒化
する技術がある。この方法ではかなり良好な単結晶島が
得られるが、結晶方位の制御は不可能であり、又、種結
晶が島周辺から雑多に生ずるために大結晶粒から成る複
結晶島が生じ易いといった大きな欠点が認められている
There is a technology that converts a polycrystalline film left on an insulating substrate (for example, 5102 or 5isNa) by etching into a single crystal or into large crystal grains using a so-called beam annealing method such as CW, pH1se laser annealing, or electron beam annealing. . Although this method yields fairly good single-crystal islands, it is impossible to control the crystal orientation, and since seed crystals are generated miscellaneously from around the islands, large-sized complex islands consisting of large crystal grains are likely to occur. Shortcomings are acknowledged.

まだ、グラフオエピタキシー法は、非晶質絶縁膜上に単
結晶薄膜をビームアニール法で形成しようとする点は、
上述の方法と同じであるが、非晶質基板上に結晶癖に対
応する非常に細かな溝をあらかじめ設けておくことによ
って、上述の方法では不可能であった結晶方位を制御し
ようとするものである。しかしながら、現在の所KGl
の水溶液からの単結晶成長では幾分の成功を得ているよ
うではあるが、Siなどの半導体膜では、満足なものは
得られていない。すなわちこの方法は半導体素子を形成
できる程の大きさく数μm角)になっておらず、素子特
性や結晶欠陥、微小角粒界や双晶などについての解析は
成し得す、現在の所、使用し得る技術ではない。
However, the graph-o-epitaxy method attempts to form a single crystal thin film on an amorphous insulating film using a beam annealing method.
This method is the same as the above method, but attempts to control the crystal orientation, which was not possible with the above methods, by preparing in advance very fine grooves corresponding to the crystal habit on the amorphous substrate. It is. However, currently KGl
Although some success seems to have been achieved in growing single crystals from aqueous solutions, satisfactory results have not been achieved with semiconductor films such as Si. In other words, this method does not have a size large enough to form semiconductor devices (a few μm square), and it is currently not possible to analyze device characteristics, crystal defects, small-angle grain boundaries, twin crystals, etc. This is not a usable technology.

ブリッジングエビタキシーやシープイド・ビームアニー
リングにおいては、種結晶としての基板があるため、結
晶方位はある程度制御されている。
In bridging epitaxy and sheepoid beam annealing, the crystal orientation is controlled to some extent because the substrate is used as a seed crystal.

しかし、よく知られているように、種結晶部から絶縁層
に結晶が成長した点で結晶欠陥などが発生し始め、1〜
3μm成長後には多結晶化してゆくなどの現象が生じて
いる。特にシープイドビームアニーリングにおいては、
開口部から周辺へ単結晶が成長するだめ、基板の結晶方
位を正確に引きつぎ成長する部分は周辺1μmに及ばず
、大粒径(1〜6μm)の多結晶として成長し、そのた
め菊花のように観察される。このような対称形は開口部
をヒートシンクとした同心円状の温度分布に対応してい
ると考えられる。
However, as is well known, crystal defects start to occur at the point where the crystal grows from the seed crystal part to the insulating layer.
After 3 μm growth, phenomena such as polycrystalization occur. Especially in sheepoid beam annealing,
As a single crystal grows from the opening to the periphery, the part where the crystal orientation of the substrate continues accurately and grows does not extend to 1 μm around the periphery, and grows as a polycrystal with a large grain size (1 to 6 μm), so it looks like a chrysanthemum. observed. It is thought that such a symmetrical shape corresponds to a concentric temperature distribution with the opening serving as a heat sink.

一方、ブリッジングエピタキシーでは、両側の種結晶を
橋脚として橋を渡すように単結晶を両側から成長させる
。種結晶部と多結晶体などの載った絶縁部が交互に平行
にラインアンドスペースを画いており、両側から合せて
3μm位がほぼ単結晶化されている。しかし、両側から
ぶつかる中央部には小角粒界のような粒界や大きな欠陥
が残留している。さらにそれよりも巾の広いブ°リッジ
イングは難しいといった欠点がある。ブリッジングエピ
タキシーの方が、幾分大きな単結晶が得られるのは、シ
ープイドビームアニーリングに比べ熱分布の対称がより
一軸性に近づいているためと思われる。このことは、冷
却速度が遅く、熱伝導による温度分布異方性が強くでる
CWレーザアニールなどによる単結晶化の方が、そのよ
うな温度分布異方性の非常に少ないパルスレーザアニー
ルなどによる単結晶化より、良好な結果を得ていること
からも分る。即ち、冷却速度の遅い場合、線状に並んで
いるヒートシンクである種結晶部に熱が流れるため、は
ぼ−軸性の温度分布を実現しゃすいことが分る。しかし
、レーザなどのビーム径は細いため、ビームの周辺部で
は当然このよりな一軸性が崩れ、結晶性を悪くする原因
となっていると考えられる。このことは、良好な結晶性
や方位をもった単結晶の成長部分はほぼレーザビームな
どの中心部分に限定されること、走査するレーザビーム
などの重なりを大きくしても、結晶性の改善が余りなさ
れないことに示されていると考えられる。
On the other hand, in bridging epitaxy, single crystals are grown from both sides using seed crystals on both sides as bridge piers. The seed crystal part and the insulating part on which the polycrystalline material is placed alternately form lines and spaces in parallel, and a total of about 3 μm from both sides is almost monocrystalline. However, grain boundaries such as small-angle grain boundaries and large defects remain in the central portion where both sides collide. Furthermore, it has the disadvantage that bridging wider than that is difficult. The reason why a somewhat larger single crystal can be obtained with bridging epitaxy is probably because the symmetry of the heat distribution is closer to uniaxiality than with sheepied beam annealing. This means that single crystallization by CW laser annealing, which has a slow cooling rate and strong temperature distribution anisotropy due to heat conduction, is better than single crystallization by pulsed laser annealing, which has very little temperature distribution anisotropy. This can be seen from the fact that better results were obtained than in crystallization. That is, it can be seen that when the cooling rate is slow, heat flows to the seed crystal portions that are linearly arranged heat sinks, making it easier to realize a periaxial temperature distribution. However, since the beam diameter of a laser or the like is small, this more uniaxiality naturally breaks down in the peripheral area of the beam, which is thought to be the cause of poor crystallinity. This means that the growth area of a single crystal with good crystallinity and orientation is almost limited to the central part of the laser beam, and even if the overlap of the scanning laser beams is increased, the crystallinity cannot be improved. This is probably due to the fact that it is rarely done.

本発明は、以上の論議のような温度分布の一軸性を改良
し、且つ、結晶成長癖を考慮に入れた単結晶成長に適し
た構造を実現し、従来法で生じていた種々の欠点を改良
した良好な結晶性を有する絶縁分離型単結晶基板を提供
すると同時に、高速のバイポーラ素子などやMO8素子
などの優れた半導体装置を提供する。
The present invention improves the uniaxiality of temperature distribution as discussed above, realizes a structure suitable for single crystal growth that takes into account crystal growth habits, and overcomes various drawbacks of conventional methods. The present invention provides an isolated type single crystal substrate having improved crystallinity, and at the same time provides excellent semiconductor devices such as high-speed bipolar devices and MO8 devices.

本発明は、電気的絶縁と熱的絶縁(低熱伝導性をいう)
を兼ねたいわゆるレリーフと、ヒートシンクでもあり種
結晶でもある開口部の両者の形状と配置により、できる
だけ−軸性に近い一様な熱流と、それと同時に結晶成長
を生じしめる特徴を有しており、且つ、鋭いカドを有す
る開口部のレリーフによる補助的な結晶方位制御作用に
より、従来、欠陥の生じ易い部分の結晶性を向上せしめ
る効果を兼ね備えだ特異な方法であり、絶縁分離熱流制
御、レリーフ補完型エピタキシー法と云えるものである
The present invention provides electrical insulation and thermal insulation (low thermal conductivity).
The shape and arrangement of both the so-called relief, which serves as a heat sink, and the opening, which is both a heat sink and a seed crystal, produces a uniform heat flow that is as close to axial as possible, and at the same time produces crystal growth. In addition, it is a unique method that has the effect of improving the crystallinity of areas where defects are likely to occur due to the auxiliary crystal orientation control effect of the relief of the opening with sharp edges, and it is also effective for insulation separation heat flow control and relief complementation. This can be called a type epitaxy method.

以下に本発明を第2図に示す基本的な一実施例を用いて
説明する。(a)は平面図(b)のI−1′線断面を示
している。第2図(b)のびは積層部分を除いた部分で
ある。基板21上に第1の絶縁膜22が平行な短冊状に
形成されており、その上及び直交するように第2の絶縁
膜23及び24が矩形状の絶縁部より成る窓25を構成
している。この第2の絶縁膜23と第1の絶縁膜22に
よって矩形の開口部26が作られている。通常、いかに
高度な蝕刻法を用いても、又、保護膜を介して窒化や酸
化によって絶縁膜を一度に形成するような場合には、な
おさら、開口部26のカドの部分は丸みを帯びる。第2
図の構造では、−直線上に短冊状に二度刷々に絶縁膜2
2と23.24を形成するため、開口部26のカドの部
分は非常に鋭く形成される。
The present invention will be explained below using a basic embodiment shown in FIG. (a) shows a cross section taken along line I-1' in the plan view (b). The stretch in FIG. 2(b) is the portion excluding the laminated portion. A first insulating film 22 is formed in the shape of parallel strips on a substrate 21, and second insulating films 23 and 24 are formed above and orthogonally to form a window 25 consisting of a rectangular insulating part. There is. A rectangular opening 26 is formed by the second insulating film 23 and the first insulating film 22. Normally, no matter how sophisticated an etching method is used, or when an insulating film is formed at once by nitriding or oxidizing a protective film, the corner portion of the opening 26 will be rounded. Second
In the structure shown in the figure, the insulating film 2 is printed twice in a rectangular shape on a straight line.
2 and 23.24, the corner portion of the opening 26 is formed very sharply.

これは前述したように、種結晶から成長してくる結晶方
位を正確に保持する、いわゆるレリーフとして有用な効
果を示すことになる。
As mentioned above, this exhibits a useful effect as a so-called relief, which accurately maintains the orientation of the crystal grown from the seed crystal.

絶縁膜22.23からなる開口部26の二辺は、本実施
例の場合には、絶縁膜23(矩形絶縁部26の一部)に
平行であるにとどまらず完全に一致している。
In this embodiment, the two sides of the opening 26 made of the insulating films 22 and 23 are not only parallel to the insulating film 23 (part of the rectangular insulating section 26), but also completely coincident with each other.

矩形絶縁部の窓25の内部に、開口部26に接して、単
結晶化された領域すなわち基板伸長部27が第1の絶縁
膜22の上に一部乗り出した状態に形成されている。こ
の基板伸長部27及び基板26の部分を、現在製造され
ている半導体素子を作り込む領域すなわち素子用基板と
する。第2図における開口部26は、種結晶であると同
時に基板26と基板伸長部27を結ぶ導通路をも兼ねて
いる特長も合わせもっている。
Inside the window 25 of the rectangular insulating section, in contact with the opening 26, a single crystallized region, that is, a substrate extension section 27 is formed so as to partially protrude above the first insulating film 22. The substrate extension portion 27 and the substrate 26 are used as a region for fabricating currently manufactured semiconductor devices, that is, a device substrate. The opening 26 in FIG. 2 has the feature of serving not only as a seed crystal but also as a conductive path connecting the substrate 26 and the substrate extension 27.

さらに付は加えると、基板伸長部27を基板21と見做
し、この部分に開口部を形成して、さらに同種の構造を
積層し得ることはいうまでもない。
Furthermore, it goes without saying that the substrate extension portion 27 can be regarded as the substrate 21, an opening can be formed in this portion, and the same type of structure can be further laminated.

第2図に示す例では、開口部2°6.絶縁部の窓25は
いずれも矩形であるが、基板の方位や結晶成長の方位に
合せ後述するような方位に合わせて、菱形に構成しても
同じ効果を得ることができる。
In the example shown in FIG. 2, the opening is 2°6. The windows 25 of the insulating portion are all rectangular, but the same effect can be obtained by configuring them in a rhombus shape in accordance with the orientation of the substrate and the orientation of crystal growth as will be described later.

又、開口部26と絶縁部の窓25の周辺の一部が共通と
なっているが、必らずしも一致せずともよく、少し隙間
があっても互いにほぼ平行になっていればよい。
Further, although a part of the periphery of the opening 26 and the window 25 of the insulating part is common, it does not necessarily have to be the same, and it is sufficient that they are approximately parallel to each other even if there is a slight gap. .

次に第2図の構造をもつ絶縁分離型単結晶基板の製造を
説明する。
Next, the production of an insulated single crystal substrate having the structure shown in FIG. 2 will be explained.

先ず基板21に、短冊状のマスク人を用いて、通常の方
法を用いてLOGO8酸化し、第2図に示すような絶縁
膜22と種結晶となる開口部28とによるラインアンド
スペースを作る。絶縁膜22の厚さは、通常用いられる
0、3〜1.0μmでよい。
First, LOGO 8 is oxidized on the substrate 21 using a rectangular mask using a conventional method to form lines and spaces between the insulating film 22 and the opening 28 which will serve as a seed crystal as shown in FIG. The thickness of the insulating film 22 may be 0.3 to 1.0 μm, which is commonly used.

この上に単結晶に変化せしめる非晶質層ないしは多結晶
質層(厚み0・2〜1.Ollm)を全面に積載する。
On top of this, an amorphous layer or a polycrystalline layer (thickness 0.2 to 1.0 mm) to be converted into a single crystal is stacked on the entire surface.

次に、ナ型のパターンにより矩形の窓を残すマスクBを
用いて、絶縁部の開口部分26に相応する部分を残して
多結晶質層に酸化ないしは窒化などの工程を施して絶縁
部23及び24を形成する。
Next, using a mask B that leaves a rectangular window with a N-shaped pattern, the polycrystalline layer is subjected to a process such as oxidation or nitriding, leaving a portion corresponding to the opening portion 26 of the insulating portion. Form 24.

この時、あらかじめ、この部分をエツチングして厚さを
約捧に減少しておくことによって表面をほぼ平旦化する
ことができる。
At this time, the surface can be made almost flat by etching this portion in advance to reduce the thickness to a certain extent.

又、この工程の前ないしは後で、イオン注入などによっ
て、種結晶となる開口部26と基板伸長部27との界面
状態が改善される。界面が汚れている時には結晶成長が
改善される。
Also, before or after this step, the state of the interface between the opening 26, which will serve as a seed crystal, and the substrate extension 27 is improved by ion implantation or the like. Crystal growth is improved when the interface is dirty.

さらに開1部F6は・以上の工程で明らかなように絶縁
膜22の端面と絶縁部の窓25の端面とで形成されるた
め、例えば開口部26の一辺が0.5μmであっても、
カドが丸くならず、矩形がうまく形成される。現在の通
常のフォトリソグラフィによってはこのような小さな開
口部は作れず、通常は丸い円形になってしまう。このよ
うに正確なカドを持つ矩形開口部はグラフオエピタキシ
ーで認められているように有効なレリーフの効果を示し
、本発明による良好な結晶性に寄与していると考えられ
る。
Furthermore, as is clear from the above steps, the opening F6 is formed by the end face of the insulating film 22 and the end face of the window 25 of the insulating part, so even if one side of the opening 26 is 0.5 μm, for example,
The corners are not rounded and a rectangular shape is formed well. Current standard photolithography does not allow for the creation of such small openings, which are usually rounded. It is believed that the rectangular opening with such precise corners exhibits an effective relief effect as recognized in grapho-epitaxy, and contributes to the good crystallinity according to the present invention.

次にエネルギービームを照射し、非晶質ないしは多結晶
である基板伸長部27を単結晶化する。
Next, an energy beam is irradiated to convert the amorphous or polycrystalline substrate extension 27 into a single crystal.

照射スるビームは、パルスレーザ、CWレーザ。The irradiation beam is a pulse laser or a CW laser.

エレクトロンビーム、赤外線、紫外線などいずれでもよ
く、短時間に基板伸長部27にエネルギーが吸収され、
溶解できればよい。本発明者らの検討によれば、必要な
照射エネルギーは、積層している膜質や種類、さらに上
にかぶせる保護膜などの状態で異なる1基板温度によっ
ても異なる。しかしながら、本発明者らの検討では、C
W−ムrレーザアニール装置の不安定性や微細積層構造
の再現性不良などの問題点はあるものの、基板温度30
0〜600°Cでは基板への大黒エネルギーは3〜11
W、走査速度は30 ”/sec〜3 ”/seaの範
囲にあった。この時、溶融中は、はぼ30μm程度にな
っていた。
Any electron beam, infrared rays, ultraviolet rays, etc. may be used, and the energy is absorbed by the substrate extension part 27 in a short time.
As long as it can be dissolved. According to studies by the present inventors, the required irradiation energy varies depending on the quality and type of laminated films, and the temperature of one substrate, which varies depending on the state of the protective film covered thereon. However, in our study, C
Although there are problems such as instability of the W-MR laser annealing equipment and poor reproducibility of fine laminated structures,
At 0 to 600°C, the Daikoku energy to the substrate is 3 to 11.
W, scanning speeds ranged from 30''/sec to 3''/sea. At this time, during melting, the thickness was approximately 30 μm.

矩形の基板伸長部27にこのビームが照射している時間
は、約0.01〜1 m5eoとなり、この短時間に溶
解、結晶成長が行われていることが分った。パルスレー
ザアニールやエレクトロンビームアニールにおいても、
はぼこの時間に溶解、結晶成長させれば、上述のCW−
ムrレーザによる再結晶化した単結晶と同程度の品質の
ものが得られると推定される。
It was found that the time during which the rectangular substrate extension portion 27 was irradiated with this beam was about 0.01 to 1 m5eo, and that melting and crystal growth took place in this short time. Even in pulsed laser annealing and electron beam annealing,
If melted and crystals are grown during the time, the above-mentioned CW-
It is estimated that a single crystal having the same quality as a single crystal recrystallized by a MU laser can be obtained.

さらに、本発明者らの簡単な実験の結果、結晶欠陥の少
ない良好な結晶を得るには、照射するビーム半径は、は
ぼ第1の絶縁膜22の上に伸びた基板伸長部27の積載
部29の長さよりも大きいことが必要であった。このこ
とは周辺を絶縁部23.24に囲まれた基板伸長部27
の熱分布を考えれば理解できる。即ち、種結晶28と絶
縁層22との境界部分にビームの中心があり、ヒートシ
ンクであっても十分なエネルギーが照射されて、種結晶
の境界表面の一部が溶解して、種結晶の内部から結晶成
長が始まり、ついで、ヒートシンクへ熱が一様に一軸性
に即ち種結晶28の線に直角に熱が流れる。したがって
、結晶成長も一様に熱流と逆方向に進むと考えられる。
Furthermore, as a result of a simple experiment conducted by the present inventors, in order to obtain a good crystal with few crystal defects, the irradiation beam radius should be adjusted to the extent that the substrate extension portion 27 extending above the first insulating film 22 is stacked. It needed to be larger than the length of section 29. This means that the board extension portion 27 surrounded by the insulating portions 23 and 24
This can be understood by considering the heat distribution. That is, the center of the beam is at the boundary between the seed crystal 28 and the insulating layer 22, and even if it is a heat sink, sufficient energy is irradiated to melt a part of the boundary surface of the seed crystal, causing the inside of the seed crystal to melt. Crystal growth begins at , and then heat flows uniformly and uniaxially, ie perpendicular to the lines of the seed crystal 28, to the heat sink. Therefore, it is thought that crystal growth uniformly proceeds in the opposite direction to the heat flow.

もし、ビーム径が、絶縁部の窓25より十分に小さけれ
ば、溶融はスポット状に生じ従って熱流は、スポットの
中心を向くように流れ、−軸性は失なわれる。さらに、
この場合には、同一の窓25内の基板伸長部27を何度
も走査することになり、同一窓内で部分的な溶解や結晶
成長が繰り返され、結晶の微小な方位の差が生じたり、
又、加熱冷却により歪や欠陥の生成が多くなるといった
実験結果は理解される。
If the beam diameter is sufficiently smaller than the window 25 of the insulator, melting occurs in the form of a spot and the heat flow is directed towards the center of the spot and the -axiality is lost. moreover,
In this case, the substrate extension part 27 within the same window 25 is scanned many times, and partial melting and crystal growth are repeated within the same window, resulting in minute differences in crystal orientation. ,
Furthermore, it is understandable that the experimental results show that heating and cooling increase the generation of distortion and defects.

このようにして得られた基板伸長部27の結晶性は良好
であるが、かなり熱応力が残留している。
Although the crystallinity of the substrate extension 27 thus obtained is good, considerable thermal stress remains.

又周囲の絶縁膜との間にも熱応力が残留していると考え
られる。これを残去するために、700〜10oo℃3
0分程度の焼鈍は非常に効果がある。
It is also considered that thermal stress remains between the surrounding insulating film and the surrounding insulating film. To leave this, 700~10oo℃3
Annealing for about 0 minutes is very effective.

なお第2図において開口部26は、絶縁部の窓26のほ
ぼ中心位置においであるが、どちらか一方に片寄っても
差しつかえないことはいうまでもない。又、開口部26
直上の再結晶化部分を、さらに酸化しつくして基板伸長
部27を二つにわけるように完全絶縁分離することも勿
論可能である。
In FIG. 2, the opening 26 is located approximately at the center of the window 26 of the insulating portion, but it goes without saying that it may be located closer to either side. Also, the opening 26
Of course, it is also possible to completely oxidize the recrystallized portion immediately above to completely insulate and separate the substrate extension portion 27 into two.

さらに開口部26の直上の再結晶化部をチャンネルにし
、両側に延びた基板伸長部27をソースとドレインに使
用しても、絶縁分離の大きな効果があることは以上の論
議から明らかである。
Furthermore, it is clear from the above discussion that even if the recrystallized portion directly above the opening 26 is used as a channel and the substrate extensions 27 extending on both sides are used as the source and drain, a great effect of insulation isolation can be obtained.

第3図に別の実施例をあげる。半導体基板31上に第1
の絶縁膜32を例えばLPCVD法で形成する。前述と
同様に短冊状に形成された絶縁膜32上にさらに多結晶
層を全面に載せ、前述の方法と同様にして、絶縁部の開
口部分36を囲むように絶縁部33を形成する。以降の
工程は前述の方法と同じである。この例での特徴として
は、絶縁膜32の下に、あらかじめ素子を形成しておく
ことが比較的に容易にできるために、半導体基板の面積
を有効に利用しえるものである。
Another embodiment is shown in FIG. On the semiconductor substrate 31, the first
The insulating film 32 is formed by, for example, the LPCVD method. A polycrystalline layer is further placed on the entire surface of the insulating film 32 formed in a strip shape in the same manner as described above, and an insulating portion 33 is formed to surround the opening portion 36 of the insulating portion in the same manner as described above. The subsequent steps are the same as the method described above. A feature of this example is that it is relatively easy to form elements in advance under the insulating film 32, so that the area of the semiconductor substrate can be used effectively.

次に開口部、絶縁部の窓の方位について、第4図、第6
図を用いて説明する。
Next, regarding the orientation of the opening and the window of the insulating part, see Figures 4 and 6.
This will be explained using figures.

本発明では、再結晶は種結晶から生ずるので方位は制御
されている。しかし、前述したように、レリーフとして
補助的な効果が大きい。したがって種結晶と類似の対称
を有したものが、結晶性に優れているのは当然といえる
。第4図、第6図では立方晶を有するSS晶を例にとっ
て説明する。
In the present invention, recrystallization occurs from a seed crystal, so orientation is controlled. However, as mentioned above, it has a great auxiliary effect as a relief. Therefore, it is natural that something with a symmetry similar to that of the seed crystal has excellent crystallinity. In FIGS. 4 and 6, an SS crystal having cubic crystals will be explained as an example.

なお簡便のため、例えば(100)面といえば、10o
、010,001の等価な三面のいずれかを指すものと
する。又、図中(110)方向は、以下の説明でいう(
110)面と直角方向である。
For the sake of simplicity, for example, the (100) plane is 10o.
, 010,001. In addition, the (110) direction in the figure is referred to as (110) in the following explanation.
110) is perpendicular to the plane.

本発明者らの検討によれば、第4図(IL)に二つの例
を示すように、はぼ(1oo)面を主平面とした基板を
使用した時は、第2図での矩形開口部26及び絶縁部の
窓25の周辺が(110)方向ないしは〈1oo〉方向
に、即ち(110)面ないしは(10o)面に各々はぼ
直角になっている時に一番よい結晶性のものが得られた
。これは、特にレリーフとなっている矩形開口部26の
対称性と種結晶の結晶方位が一致していることからもう
かかえる。
According to the studies of the present inventors, as shown in two examples in FIG. 4 (IL), when a substrate with a 100 plane as the main plane is used, the rectangular opening in FIG. The best crystallinity is when the periphery of the window 25 of the portion 26 and the insulating portion is in the (110) direction or the <1oo> direction, that is, approximately perpendicular to the (110) plane or the (10o) plane. Obtained. This is particularly possible because the symmetry of the rectangular opening 26 serving as a relief matches the crystal orientation of the seed crystal.

第4図(b)に示すように、はぼ(110)面を主平面
とした基板を使用した時には、第2図の矩形開口部26
及び絶縁部の窓26の周辺が各々(100)面及び(1
1Q)面にほぼ垂直ないしは平行になっている時に、特
によい結晶性のものが得られた。
As shown in FIG. 4(b), when using a substrate with a (110) plane as its main plane, the rectangular opening 26 in FIG.
and the periphery of the window 26 of the insulating part is the (100) plane and (1
Particularly good crystallinity was obtained when the crystallinity was approximately perpendicular or parallel to the 1Q) plane.

第5図に、はぼ(111)面を主平面とした基板を使用
した時に、特に結晶性の優れた方位二側を示しである。
FIG. 5 shows the second side with particularly excellent crystallinity when a substrate with a (111) plane as its main plane is used.

図に示すように、いずれの場合においても、第2図での
開口部26の周辺が(110)ないしは(211)面の
いずれかにほぼ垂直ないしは平行になっている。この内
、特に結晶性の優れた形状は、第5図、pvK示すもの
で、開口部26及び絶縁部の窓27の周辺が各々(11
0)と(211)而に平行になっており、矩形を形成し
ている時であった。
As shown in the figure, in either case, the periphery of the opening 26 in FIG. 2 is approximately perpendicular or parallel to either the (110) or (211) plane. Among these, the shape with particularly excellent crystallinity is shown in FIG.
0) and (211) were parallel to each other, forming a rectangle.

第5図す及びCに示すものは、(110)面ないしは(
211)面の片方のみに平行な周辺より成っており、図
からも分るように菱形をしている。
The objects shown in Figures 5 and 5C are (110) planes or (
211) It consists of a periphery that is parallel to only one side of the plane, and as you can see from the figure, it has a rhombic shape.

第2図での第1の絶縁層22の端部と第2の絶縁層23
の端部が、直角でなく、6o の角度で交わっている。
The end of the first insulating layer 22 and the second insulating layer 23 in FIG.
The ends of the two do not meet at a right angle, but at an angle of 6o.

従って、熱流を考えると少し対称性が崩れており、一様
性が少ないことから、余り結晶性が優れないと思われる
が、レリーフの効果が大きく作用して、結果的には、良
好な結晶性のものになったと考えられる。前述の実施例
に示したように、第1と第2の絶縁層を二度に分けて形
成するため、この60度の角度は鋭く形成されることも
、レリーフの効果が大きい理由になっていると思われる
。この時、第1と第2の絶縁層を一度に形成すると当然
カドの部分に丸みがつき、レリーフの効果がなくなると
思われる。
Therefore, considering the heat flow, the symmetry is slightly broken and there is little uniformity, so it seems that the crystallinity is not very good, but the effect of the relief is large and as a result, the crystallinity is good. It is thought that it became a sexual thing. As shown in the above embodiment, the first and second insulating layers are formed in two parts, so this 60 degree angle is formed sharply, which is also the reason why the relief effect is large. It seems that there are. At this time, if the first and second insulating layers are formed at the same time, the edges will naturally become rounded and the relief effect will be lost.

本発明において従来のブリッジングエビタキシーや、シ
ープイドビームアニーリングと比べ、格段によい結晶が
得られているのは、このようなレリーフの効果と、本発
明により導入された熱流制御による結晶成長の制御によ
ることは明らかであろう。しかも結晶方位が正確に制御
されている優れたものである。
The reason why much better crystals are obtained in the present invention than in the conventional bridging epitaxy and sheepied beam annealing is due to the effect of such relief and the crystal growth by the heat flow control introduced by the present invention. It is clear that this is due to control. Moreover, it is an excellent product in which the crystal orientation is accurately controlled.

以下に本発明の限定的でない実施例をあげる。The following are non-limiting examples of the invention.

〈実施例1〉 はぼ(100)面を主平面とする基板に、マスク人を用
い、LOCO8法で第1の酸化層(第2図22)の巾1
5μm2種結晶の巾(第2図28)1.5μmの交互に
配置されたラインアンドスペースを形成した。この上に
、LPCVD法によって多結晶シリコンを約0.5μm
厚積層上た。この時基板温度を500℃に保った。次に
巾4μm、長さ10μmの窓と、巾4μmと長さ14μ
mの窓と、巾4μm、長さ18μmの窓の三種の異なっ
た窓を有するマスクBを用いて、第2図に示すように基
板伸長部27を囲む多結晶部を酸化し、第4図(+L)
に示すような配置にして完全な酸化層にした。得られた
窓の大きさは、それぞれ、約3×9μm、3×13μm
、3X17μmであった。この時、第1の絶縁膜−ヒの
積載部(第2図29)の長さは、各々約3μm、5μm
、7μmであった。
<Example 1> Using a mask, the width of the first oxide layer (FIG. 2 22) is 1
Two 5 μm seed crystals formed alternately arranged lines and spaces with a width of 1.5 μm (FIG. 2, 28). On top of this, polycrystalline silicon is deposited to a thickness of approximately 0.5 μm using the LPCVD method.
Thick laminate top. At this time, the substrate temperature was maintained at 500°C. Next, a window with a width of 4 μm and a length of 10 μm, and a window with a width of 4 μm and a length of 14 μm.
Using a mask B having three different types of windows: a window with a width of 4 μm and a window with a width of 4 μm and a length of 18 μm, the polycrystalline portion surrounding the substrate extension 27 is oxidized as shown in FIG. (+L)
A completely oxidized layer was obtained by arranging the structure as shown in the figure. The sizes of the obtained windows are approximately 3 x 9 μm and 3 x 13 μm, respectively.
, 3×17 μm. At this time, the lengths of the first insulating film stacking part (FIG. 2 29) are approximately 3 μm and 5 μm, respectively.
, 7 μm.

CW−ムrレーザ照射をつづけて行った。基板温)は約
350 ℃y 走査速度は30 ”/s ec+  レ
ーザエネルギーは約5Wでこの時の溶融する多結晶S1
の巾は約25μm強であった。
CW-mura laser irradiation was continued. The substrate temperature) is approximately 350°C, the scanning speed is 30”/sec+, the laser energy is approximately 5W, and the polycrystalline S1 melted at this time.
The width was a little over 25 μm.

得られた単結晶層を、セコ−エッチ液で軽くエッチした
後、暗視野光学顕微鏡で調べだ。上記の三種の窓での単
結晶化はうまく行われていることが分った。しかし、厚
さ05μmの10倍以上になる積載部をもつ窓、3X1
7μmについては、端部の約2μmの所に小さな他方位
の結晶が生じていることが一部に認められた。この他の
部分については、殆んど結晶欠陥が認められず優れた結
晶であることが分った。
The resulting single-crystal layer was lightly etched with Seco etchant and examined using a dark-field optical microscope. It was found that single crystallization using the above three types of windows was successfully carried out. However, a window with a loading part that is more than 10 times as thick as 05 μm, 3
Regarding 7 μm, it was partially observed that small crystals on the other side were formed at about 2 μm from the edge. In other parts, almost no crystal defects were observed, indicating that the crystal was excellent.

なお、端部に生じた微結晶の部分は、非常にわずかの部
分であるだめ、この部分を例えばソースやドレイン又は
゛コンタクトなどに使用すれば、結晶方位の乱れによる
悪影響を避けることができる。
Note that the microcrystalline portion formed at the end is a very small portion, and if this portion is used, for example, as a source, drain, or contact, it is possible to avoid adverse effects due to disordered crystal orientation.

したがって、このような利用をすれば使用に耐えない品
質不良の結晶でなくなることも判明した。
Therefore, it has been found that if the crystals are used in this way, the crystals will no longer be of poor quality and cannot be used.

〈実施例2〉 実施例1と同様の工程を経て、同様の構造の積層型単結
晶苓板を作成した。但し、この時には、マスクBを実施
例1より15 回転させた結果、矩型ではなく、菱形の
開口部が開いている。得られた基板伸長部の結晶性は、
3X9μmの窓については良好であったが、他の大きな
二種の窓については満足すべきものでなく、種結晶の端
から3〜4μlの位置から欠陥や多結晶化がかなりのも
のに認められた。
<Example 2> Through the same steps as in Example 1, a laminated single crystal laminated plate having a similar structure was created. However, at this time, as a result of rotating the mask B by 15 degrees compared to Example 1, the opening is not rectangular but diamond-shaped. The crystallinity of the obtained substrate extension is
The 3 x 9 μm window was good, but the other two large windows were unsatisfactory, and a considerable number of defects and polycrystals were observed from a position 3 to 4 μl from the edge of the seed crystal. .

〈実施例3〉 実施例1と同様の処理を行った。但し、本実施例では、
CW−ムrレーザ照射を約10W、走査速度3000 
”/secとした。この時の多結晶シリコンの溶融巾は
約30μmであった。得られた単結晶の結晶性は、はぼ
実施例1の結果と同じであった。
<Example 3> The same treatment as in Example 1 was performed. However, in this example,
CW-mura laser irradiation at approximately 10W, scanning speed 3000
''/sec. The melting width of the polycrystalline silicon at this time was about 30 μm. The crystallinity of the obtained single crystal was almost the same as the result of Example 1.

〈実施例4〉 実施例2と同様の処理を行った。但し、CW−ムrレー
サ照射を約4W、走査速度3000 ”Vg 6 Cと
した。この時の多結晶シリコンの溶融巾は約20μmで
あった。得られた単結晶の結晶性はいずれの窓のものに
ついても欠陥が多く、粒界が多く認められた。
<Example 4> The same treatment as in Example 2 was performed. However, the CW-muralaser irradiation was about 4 W and the scanning speed was 3000"Vg 6 C. The melting width of the polycrystalline silicon at this time was about 20 μm. The crystallinity of the obtained single crystal was There were also many defects and many grain boundaries were observed.

〈実施例6〉 はぼ(111)面を主平面とする基板を用い、実施例1
と同様の処理をした。窓の配置は、第5図aに示す方位
である。得られた単結晶の結晶性はいずれも、実施例1
と同様に優れたものであった。
<Example 6> Using a substrate having a (111) plane as its main plane, Example 1
I did the same process. The arrangement of the windows is in the orientation shown in Figure 5a. The crystallinity of the obtained single crystals was that of Example 1.
It was equally excellent.

〈実施例6〉 実施例6と同様の検討を行った。但し、この実施例にお
いては、窓の配置を第6図すおよびCに示す方位にした
。得られた単結晶の結晶性はいずれもかなり良好であっ
たが実施例6のものより幾分劣っていた。しかし、実施
例2のものよりは優れていた。
<Example 6> The same study as in Example 6 was conducted. However, in this embodiment, the windows were arranged in the directions shown in FIGS. 6 and 6C. The crystallinity of the obtained single crystals was all quite good, but was somewhat inferior to that of Example 6. However, it was better than that of Example 2.

〈実施例7〉 実施例1と同様の実験を行った。但し、本検討では、多
結晶シリコンを約03μmプラズマCVDエレクトロン
ビームアニーリングヲ行った。ソリ照射条件は、加速エ
ネルギーts Kev、電流3mム、基基板塵soo℃
、走査速度20oO1nVseCである。
<Example 7> An experiment similar to Example 1 was conducted. However, in this study, polycrystalline silicon was subjected to plasma CVD electron beam annealing at a thickness of approximately 0.3 μm. The warping irradiation conditions are: acceleration energy ts Kev, current 3mm, substrate dust soo℃
, the scanning speed was 20oO1nVseC.

この時のシリコン層の溶融中は約50μmを示した。得
られた単結晶層は、実施例1で得た結晶性とほぼ同じで
あり、レーザビームでも、エレクトロンビームでもほぼ
同じような結果が得られることが分った。
At this time, the thickness of the silicon layer during melting was about 50 μm. The crystallinity of the obtained single crystal layer was almost the same as that obtained in Example 1, and it was found that almost the same results could be obtained with a laser beam or an electron beam.

【図面の簡単な説明】[Brief explanation of the drawing]

3図は本発明にかかる他の半導体基体の断面図、第4図
(lL)、(b)、第6図は開口部及び絶縁部の窓の方
位を簡略に示す図である。 21.31・・・・・・基板、22 y  23 y 
 24 p  33・・・・・・絶縁膜、26・・・・
・・絶縁部の窓、26・・・・・・開口部、27,37
・・・・・・基板伸長部。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名A0 第1図 (α、    (b> 第3図 第5図
FIG. 3 is a cross-sectional view of another semiconductor substrate according to the present invention, and FIGS. 4(IL), (b), and 6 are views schematically showing the orientations of the opening and the window of the insulating portion. 21.31...Substrate, 22 y 23 y
24 p 33... Insulating film, 26...
...Insulating section window, 26...Opening, 27, 37
・・・・・・Extended part of the board. Name of agent Patent attorney Toshio Nakao and 1 other person A0 Figure 1 (α, (b> Figure 3 Figure 5)

Claims (1)

【特許請求の範囲】 (1)基板上の絶縁膜に形成した矩形ないしは菱形開口
部、この開口部を通して前記基板と接触する単結晶化さ
れた基板伸長部、前記基板伸長部を矩形状ないしは菱形
状に周囲から分離す名矩形絶縁部の窓を有し、前記開口
部の周辺と絶縁部窓の周辺のいずれかが互いにほぼ平行
になっていることを特徴とする半導体基体。 G2)  基板伸長部及び前記矩形ないしは菱形絶縁部
の先端の高さがほぼ平旦化されてなることを特徴とする
特許請求の範囲第1項に記載の半導体基体。 (3)基板上に矩形ないしは菱形開口部を有する絶縁膜
を形成する工程と、前記開口部を通して基板と接触する
非晶質ないしは多結晶半導体膜を形成し、前記矩形ない
しは菱形開口部の周辺のいずれかにほぼ平行になってい
る周辺部を有する矩形々いしは菱形の窓を形成するよう
に前記半導体膜を部分的に残すよう周囲の前記半導体膜
を絶縁化する工程と、前記半導体膜にビームアニールを
施す工程とを備えたことを特徴とする半導体基体の製造
方法。 (4)絶縁化する工程より前に、絶縁化される半導体膜
厚を減少せしめることを特徴とする特許請求の範囲第3
項に記載の半導体基体の製造方法。 (6)  ビームアニールを施す工程において、ビーム
の半径が、基板上に形成された絶縁膜の上に突出した基
板伸長部よりも大きいことを特徴とする特許請求の範囲
第3項に記載の半導体基体の製造方法。 (6)  ビームアニールを施す工程において、走査型
ビームアニール法を用い、且つ、その走査方向を肴諮矩
型絶縁部の窓にほぼ平行ないしは直角にすることを特徴
とする特許請求の範囲第3項に記載の半導体基体の製造
方法。 (カ ビームアニールを施す工程において、ビーム滞留
時間を0.01〜1mSθCとすることを特徴とする特
許請求の範囲第3項に記載の半導体基体の製造方法。 (8)基板の主平面が(100)ないしは(110)面
にほぼ一致しており、且つ、矩形ないしは菱形開口部及
び絶縁部周辺が、(100)ないしは(110)面にほ
ぼ平行ないしは直角になっていることを特徴とする特許
請求の範囲第3項に記載の半導体基体の製造方法。 (9)基板の主平面が(111)面にほぼ一致しており
、且つ、矩形ないしは菱形開口部及び絶縁部周辺のいず
れかが(110)ないしは(211)面のいずれかに平
行になっていることを特徴とする特許請求の範囲第3項
に記載の半導体基体の製造方法。
[Scope of Claims] (1) A rectangular or diamond-shaped opening formed in an insulating film on a substrate, a monocrystalline substrate extension that contacts the substrate through the opening, and a rectangular or diamond-shaped opening that contacts the substrate through the opening. 1. A semiconductor substrate having a rectangular insulating window separated from its surroundings in shape, and either the periphery of the opening or the periphery of the insulating window being substantially parallel to each other. G2) The semiconductor substrate according to claim 1, wherein the height of the tip of the substrate extension portion and the rectangular or rhombic insulating portion is approximately equal. (3) forming an insulating film having a rectangular or rhombic opening on the substrate; forming an amorphous or polycrystalline semiconductor film in contact with the substrate through the opening; a step of insulating the surrounding semiconductor film so as to partially leave the semiconductor film so as to form a rectangular or rhombic window having a peripheral portion that is substantially parallel to either side; 1. A method for manufacturing a semiconductor substrate, comprising the step of beam annealing. (4) Claim 3, characterized in that the thickness of the semiconductor film to be insulated is reduced before the insulating step.
A method for manufacturing a semiconductor substrate according to section 1. (6) The semiconductor according to claim 3, wherein in the step of performing beam annealing, the radius of the beam is larger than the extended portion of the substrate that protrudes above the insulating film formed on the substrate. Substrate manufacturing method. (6) In the step of performing beam annealing, a scanning beam annealing method is used, and the scanning direction is made substantially parallel to or perpendicular to the window of the rectangular insulating section. A method for manufacturing a semiconductor substrate according to section 1. (8) The method for manufacturing a semiconductor substrate according to claim 3, characterized in that in the beam annealing step, the beam residence time is 0.01 to 1 mSθC. (8) The main plane of the substrate is ( 100) or (110) plane, and the rectangular or diamond-shaped opening and the periphery of the insulating part are substantially parallel to or perpendicular to the (100) or (110) plane. The method for manufacturing a semiconductor substrate according to claim 3. (9) The main plane of the substrate substantially coincides with the (111) plane, and either the rectangular or rhombic opening or the periphery of the insulating part is ( The method for manufacturing a semiconductor substrate according to claim 3, wherein the semiconductor substrate is parallel to either the (110) or (211) plane.
JP57063757A 1982-04-15 1982-04-15 Semiconductor base body and its manufacture Granted JPS58180019A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57063757A JPS58180019A (en) 1982-04-15 1982-04-15 Semiconductor base body and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57063757A JPS58180019A (en) 1982-04-15 1982-04-15 Semiconductor base body and its manufacture

Publications (2)

Publication Number Publication Date
JPS58180019A true JPS58180019A (en) 1983-10-21
JPH0413848B2 JPH0413848B2 (en) 1992-03-11

Family

ID=13238579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57063757A Granted JPS58180019A (en) 1982-04-15 1982-04-15 Semiconductor base body and its manufacture

Country Status (1)

Country Link
JP (1) JPS58180019A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6163015A (en) * 1984-09-04 1986-04-01 Agency Of Ind Science & Technol Manufacture of seed structure for soi
JPS61234026A (en) * 1985-04-10 1986-10-18 Agency Of Ind Science & Technol Growing method for semiconductor single crystal
US5401683A (en) * 1987-12-04 1995-03-28 Agency Of Industrial Science And Technology Method of manufacturing a multi-layered semiconductor substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56126914A (en) * 1980-03-11 1981-10-05 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56126914A (en) * 1980-03-11 1981-10-05 Fujitsu Ltd Manufacture of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6163015A (en) * 1984-09-04 1986-04-01 Agency Of Ind Science & Technol Manufacture of seed structure for soi
JPS61234026A (en) * 1985-04-10 1986-10-18 Agency Of Ind Science & Technol Growing method for semiconductor single crystal
US5401683A (en) * 1987-12-04 1995-03-28 Agency Of Industrial Science And Technology Method of manufacturing a multi-layered semiconductor substrate

Also Published As

Publication number Publication date
JPH0413848B2 (en) 1992-03-11

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