JPH0413848B2 - - Google Patents

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Publication number
JPH0413848B2
JPH0413848B2 JP57063757A JP6375782A JPH0413848B2 JP H0413848 B2 JPH0413848 B2 JP H0413848B2 JP 57063757 A JP57063757 A JP 57063757A JP 6375782 A JP6375782 A JP 6375782A JP H0413848 B2 JPH0413848 B2 JP H0413848B2
Authority
JP
Japan
Prior art keywords
substrate
insulating film
silicon layer
crystal
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57063757A
Other languages
Japanese (ja)
Other versions
JPS58180019A (en
Inventor
Koichi Kugimya
Shigenobu Akyama
Haruhide Fuse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57063757A priority Critical patent/JPS58180019A/en
Publication of JPS58180019A publication Critical patent/JPS58180019A/en
Publication of JPH0413848B2 publication Critical patent/JPH0413848B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02686Pulsed laser beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02488Insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02502Layer structure consisting of two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02598Microstructure monocrystalline
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683Continuous wave laser beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691Scanning of a beam

Description

【発明の詳細な説明】 本発明は一種の絶縁分離領域を搭載した半導体
基体およびその製造方法を提供するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor body equipped with a type of isolation region and a method of manufacturing the same.

従来より絶縁分離法は半導体装置にとつて非常
に重要な技術であり、特にバイポーラ素子などで
は、高速化、高密度化に伴つて、今後も益々重要
となる技術と位置づけられている。従来は、第1
図aに示すように半導体基板11中へ、表面より
絶縁分離層12を形成し、その間に残存する領域
を活性層13として素子を組み込む。この時、高
密度化のために、分離層12間の距離を縮めると
その間に大きな応力が働き始め、結晶欠陥が生
じ、素子特性を劣化させるといつた欠点や、第1
図aにも示されているようにバーズビーク14が
出来、分離層12間の距離を縮小し得ない等の限
があつた。これに対して、第1図bに示すよう
に、絶縁分離層12を11内部に形成する試みが
なされている。例えばイオン注入によつて酸素を
深く注入し、酸化物を形成する方法で第1図bの
構造を形成するものであるが、注入欠陥の残存す
るという欠点や大量の酸素を注入しなければなら
ず余り現実的で現実的でないといつた欠点があ
る。
The insulation isolation method has traditionally been a very important technology for semiconductor devices, and is positioned as a technology that will become even more important in the future, especially in bipolar devices and the like, as speeds and densities increase. Conventionally, the first
As shown in FIG. 1A, an insulating separation layer 12 is formed in a semiconductor substrate 11 from the surface, and the remaining region between them is used as an active layer 13 to incorporate an element. At this time, when the distance between the separation layers 12 is shortened in order to increase the density, large stress begins to act between them, causing crystal defects and deteriorating device characteristics.
As shown in FIG. 1A, bird's beaks 14 are formed, and the distance between the separation layers 12 cannot be reduced. In response to this, an attempt has been made to form an insulating separation layer 12 inside 11, as shown in FIG. 1b. For example, the structure shown in Figure 1b is formed by deeply implanting oxygen by ion implantation to form an oxide, but this method has the drawback that implantation defects remain and a large amount of oxygen must be implanted. It has the drawback of being too realistic and unrealistic.

他にも陽極酸化を利用して同様に完全絶縁分離
を行う試みもなされているが種々の問題点があ
り、未完成の技術である。
Other attempts have also been made to achieve complete insulation isolation using anodic oxidation, but there are various problems and the technology is still incomplete.

本発明は、このような絶縁分離層を形成する新
しい方法、及び、その方法によつて高速型のバイ
ポーラ素子などの実現をはかるものである。
The present invention aims to provide a new method for forming such an insulating separation layer, and to realize a high-speed bipolar device using the method.

本発明の方法においては、少なくとも一部が絶
縁膜上にあり、他の一部が半導体基板に直接に接
している半導体多結晶膜ないしは非晶質膜の単結
晶化法を応用している。
In the method of the present invention, a single crystallization method is applied to a semiconductor polycrystalline film or an amorphous film in which at least a part is on an insulating film and the other part is in direct contact with a semiconductor substrate.

この単結晶化法については、ここ数年来、各種
の提案がなされている。以下に提案されている技
術について簡単に説明を行う。
Various proposals have been made regarding this single crystallization method over the past few years. The proposed technology will be briefly explained below.

絶縁基板(例えばSiO2やSi3N4)上に蝕刻法な
どで残した多結晶島を、CWやpulseレーザアニ
ール,エレクトロンビームアニールなどのいわゆ
るビームアニール法によつて、単結晶化ないしは
大結晶粒化する技術がある。この方法ではかなり
良好な単結晶島が得られるが、結晶方位の制御は
不可能であり、又、種結晶が島周辺から雑多に生
ずるために大結晶粒から成る複結晶島が生じ易い
といつた大きな欠点が認められている。
Polycrystalline islands left on an insulating substrate (e.g. SiO 2 or Si 3 N 4 ) by etching are made into single crystals or large crystals by so-called beam annealing methods such as CW, pulse laser annealing, and electron beam annealing. There is a technology to granulate it. Although fairly good single-crystal islands can be obtained using this method, it is impossible to control the crystal orientation, and since seed crystals are scattered around the islands, complex islands consisting of large crystal grains are likely to occur. Major shortcomings have been recognized.

また、グラフオエピキタシー法は、非晶質絶縁
膜上に単結晶薄膜をビームアニール法で形成しよ
うとする点は、上述の方法と同じであるが、非晶
質基板上に結晶癖に対応する非常に細かな溝をあ
らかじめ設けておくことによつて、上述の方法で
は不可能であつた結晶方位を制御しようとするも
のである。しかしながら、現在の所KClの水溶液
からの単結晶成長では幾分の成功を得ているよう
ではあるが、Siなどの半導体膜では、満足なもの
は得られていない。すなわちこの方法は半導体素
子を形成できる程の大きさ(数μm角)になつて
おらず、素子特性や結晶欠陥、微小角粒界や双晶
などについての解析は成し得ず、現在の所、使用
し得る技術ではない。
In addition, the grapho-epikitacy method is the same as the above-mentioned method in that it attempts to form a single crystal thin film on an amorphous insulating film by beam annealing. By preparing corresponding very fine grooves in advance, it is possible to control the crystal orientation, which was impossible with the above-mentioned methods. However, although it seems that some success has been achieved in growing single crystals from an aqueous solution of KCl, satisfactory results have not been achieved with semiconductor films such as Si. In other words, this method does not have a size large enough to form semiconductor devices (several μm square), and it is not possible to analyze device characteristics, crystal defects, small-angle grain boundaries, twin crystals, etc. , it is not a usable technique.

ブリツジングエピタキシーやシーデイド・ビー
ムアニーリングにおいては、種結晶としての基板
があるため、結晶方位はある程度制御されてい
る。しかし、よく知られているように、種結晶部
から絶縁層に結晶が成長した点で結晶欠陥などが
発生し始め、1〜3μm成長後には多結晶化してゆ
くなどの現象が生じている。特にシーデイドビー
ムアニーリングにおいては、開口部から周辺へ単
結晶が成長するため、基板の結晶方位を正確に引
きつぎ成長する部分は周辺1μmに及ばず、大粒径
1〜5μmの多結晶として成長し、そのため菊花の
ように観察される。このような対称形は開口部を
ヒートシンクとした同心円状の温度分布に対応し
ていると考えられる。
In bridging epitaxy and seeded beam annealing, the crystal orientation is controlled to some extent because the substrate is used as a seed crystal. However, as is well known, crystal defects begin to occur at the point where crystals grow from the seed crystal portion to the insulating layer, and after 1 to 3 μm growth, phenomena such as polycrystalization occur. In particular, in seeded beam annealing, single crystals grow from the opening to the periphery, so the area where the crystal orientation of the substrate continues accurately and grows does not reach 1 μm around the periphery, and grows as a polycrystal with a large grain size of 1 to 5 μm. Therefore, it is observed like a chrysanthemum. It is thought that such a symmetrical shape corresponds to a concentric temperature distribution with the opening serving as a heat sink.

一方、ブリツジングエピタキシーでは、両側の
種結晶を橋脚として橋を渡すように単結晶を両側
から成長させる。種結晶部と多結晶体などの載つ
た絶縁部が交互に平行にラインアンドスペースを
画いており、両側から合せて3μm位がほぼ単結晶
化されている。しかし、両側からぶつかる中央部
には小角粒界のような粒界や大きな欠陥が残留し
ている。さらにそれよりも巾の広いブリツジイン
グは難しいといつた欠点がある。ブリツジイング
エピタキシーの方が、幾分大きな単結晶が得られ
るのは、シーデイドビームアニーリングに比べ熱
分布の対称がより一軸性に近づいているためと思
われる。このことは、冷却速度が遅く、熱伝導に
よる温度分布異方性が強くでるCWレーザアニー
ルなどによる単結晶化の方が、そのような温度分
布異方性の非常に少ないパルスレーザアニールな
どによる単結晶化より、良好な結果を得ているこ
とからも分る。即ち、冷却速度の遅い場合、線状
に並んでいるヒートシンクである種結晶部に熱が
流れるため、ほぼ一軸性の温度分布を実現しやす
いことが分る。しかし、レーザなどのビーム径は
細いため、ビームの周辺部では当然このような一
軸性が崩れ、結晶性を悪くする原因となつている
と考えられる。このことは、良好な結晶性や方位
をもつた単結晶の成長部分はほぼレーザビームな
どの中心部分に限定されること、走査するレーザ
ビームなどの重なりを大きくしても、結晶性の改
善が余りなされないことに示されていると考えら
れる。
On the other hand, in bridging epitaxy, single crystals are grown from both sides using seed crystals on both sides as bridge piers. The seed crystal part and the insulating part on which polycrystalline material is placed alternately form lines and spaces in parallel, and a total of about 3 μm from both sides is almost single crystallized. However, grain boundaries such as small-angle grain boundaries and large defects remain in the central portion where both sides collide. Furthermore, it has the disadvantage that bridging wider than that is difficult. The reason why a somewhat larger single crystal can be obtained with bridging epitaxy is probably because the symmetry of the heat distribution is closer to uniaxiality than with seeded beam annealing. This means that single crystallization using CW laser annealing, which has a slow cooling rate and strong temperature distribution anisotropy due to heat conduction, is better than single crystallization using pulsed laser annealing, which has very little temperature distribution anisotropy. This can be seen from the fact that better results were obtained than in crystallization. That is, it can be seen that when the cooling rate is slow, heat flows to the seed crystal portions that are linearly arranged heat sinks, so it is easy to realize a substantially uniaxial temperature distribution. However, since the beam diameter of a laser or the like is small, this uniaxiality naturally breaks down in the peripheral area of the beam, which is considered to be the cause of poor crystallinity. This means that the growth area of a single crystal with good crystallinity and orientation is almost limited to the central part of the laser beam, and even if the overlap of the scanning laser beams is increased, the crystallinity cannot be improved. This is probably due to the fact that it is rarely done.

本発明は、以上の論議のような温度分布の一軸
性を改良し、且つ、結晶成長癖を考慮に入れた単
結晶成長に適した構造を実現し、従来法で生じて
いた種々の欠点を改良した良好な結晶性を有する
絶縁分離型単結晶基板を提供すると同時に、高速
のバイポーラ素子などやMOS素子などの優れた
半導体装置を提供する。
The present invention improves the uniaxiality of temperature distribution as discussed above, realizes a structure suitable for single crystal growth that takes into account crystal growth habits, and overcomes various drawbacks of conventional methods. The present invention provides an isolated single-crystal substrate with improved crystallinity, and at the same time provides excellent semiconductor devices such as high-speed bipolar devices and MOS devices.

本発明は、電気的絶縁と熱的絶縁(低熱伝導性
をいう)を兼ねたいわゆるレリーフと、ヒートシ
ンクでもあり種結晶でもある開口部の両者の形状
と配置により、できるだけ一軸性に近い一様な熱
流と、それと同時に結晶成長を生じしめる特徴を
有しており、且つ、鋭いカドを有する開口部のレ
リーフによる補助的な結晶方位制御作用により、
従来、欠陥の生じ易い部分の結晶性を向上せしめ
る効果を兼ね備えた特異な方法であり、絶縁分離
熱流制御、レリーフ補完型エピタキシー法と云え
るものである。
The present invention uses the shape and arrangement of both the so-called relief, which serves as both electrical insulation and thermal insulation (low thermal conductivity), and the opening, which is both a heat sink and a seed crystal, to achieve uniformity as close to uniaxial as possible. It has the characteristics of causing heat flow and crystal growth at the same time, and has an auxiliary crystal orientation control effect by the relief of the opening with sharp corners.
This is a unique method that has the effect of improving the crystallinity of areas where defects are likely to occur, and can be called insulation separation heat flow control and relief complementary epitaxy.

まず、第2図を用いて本発明の前提となる方法
を説明する。aは平面図bの−′線断面を示
している。第2図bのb′は積層部分を除いた部分
である。基板21上に第1の絶縁膜22が平行な
短冊状に形成されており、その上及び直交するよ
うに第2の絶縁膜23及び24が矩形状の絶縁部
より成る窓25を構成している。この第2の絶縁
膜23と第1の絶縁膜22によつて矩形の開口部
26が作られている。通常、いかに高度な蝕刻法
を用いても、又、保護膜を介して窒化や酸化によ
つて絶縁膜を一度に形成するような場合には、な
おさら、開口部26のカドの部分は丸みを帯び
る。第2図の構造では、一直線上に短冊状に二度
別々に絶縁膜22と23,24を形成するため、
開口部26のカドの部分は非常に鋭く形成され
る。これは前述したように、種結晶から成長して
くる結晶方位を正確に保持する、いわゆるレリー
フとして有用な効果を示すことになる。
First, the method on which the present invention is based will be explained using FIG. a shows a cross section taken along the line -' of the plan view b. b' in FIG. 2b is a portion excluding the laminated portion. A first insulating film 22 is formed in the shape of parallel strips on a substrate 21, and second insulating films 23 and 24 are formed above and orthogonally to form a window 25 consisting of a rectangular insulating part. There is. A rectangular opening 26 is formed by the second insulating film 23 and the first insulating film 22. Normally, no matter how advanced the etching method is used, or when an insulating film is formed at once by nitriding or oxidizing through a protective film, the corners of the opening 26 are not rounded. take on In the structure shown in FIG. 2, since the insulating films 22, 23, and 24 are formed twice in a rectangular shape in a straight line,
The corner portion of the opening 26 is formed very sharply. As mentioned above, this exhibits a useful effect as a so-called relief, which accurately maintains the orientation of the crystal grown from the seed crystal.

絶縁膜22,23からなる開口部26の二辺
は、本実施例の場合には、絶縁膜23(矩形絶縁
部25の一部)に平行であるにとどまらず完全に
一致している。
In the case of this embodiment, the two sides of the opening 26 made up of the insulating films 22 and 23 are not only parallel to the insulating film 23 (part of the rectangular insulating section 25) but also completely coincident with each other.

矩形絶縁部の窓25の内部に、開口部26に接
して、単結晶化された領域すなわち基板伸長部2
7が第1の絶縁膜22の上に一部乗り出した状態
に形成されている。この基板伸長部27及び基板
26の部分を、現在使用されている半導体素子を
作り込む領域すなわち素子用基板とする。第2図
における開口部26は、種結晶であると同時に基
板26と基板伸長部27を結ぶ導通路をも兼ねて
いる特長も合わせもつている。
Inside the window 25 of the rectangular insulating part, in contact with the opening 26, there is a single crystallized region, that is, the substrate extension part 2.
7 is formed so as to partially protrude above the first insulating film 22 . The substrate extension portion 27 and the substrate 26 are used as a region for fabricating currently used semiconductor devices, that is, a device substrate. The opening 26 in FIG. 2 has the feature of serving not only as a seed crystal but also as a conductive path connecting the substrate 26 and the substrate extension 27.

さらに付け加えると、基板伸長部27を基板2
1と見倣し、この部分に開口部を形成して、さら
に同種の構造を積層し得ることはいうまでもな
い。
In addition, the board extension part 27 can be
1, an opening can be formed in this portion, and the same type of structure can be further laminated.

第2図に示す例では、開口部26、絶縁部の窓
25はいずれも矩形であるが、基板の方位や結晶
成長の方位に合せ後述するように方位に合わせ
て、菱形に構成しても同じ効果を得ることができ
る。又、開口部26と絶縁部の窓25の周辺の一
部が共通となつているが、必らずしも一致せずと
もよく、少し隙間があつても互いにほぼ平行にな
つていればよい。
In the example shown in FIG. 2, the opening 26 and the window 25 of the insulating part are both rectangular, but they may also be configured in a rhombus shape according to the orientation of the substrate and the orientation of crystal growth, as will be described later. You can get the same effect. Further, although a part of the periphery of the opening 26 and the window 25 of the insulating part is common, it does not necessarily have to be the same, and it is sufficient that they are approximately parallel to each other even if there is a slight gap. .

次に第2図の構造をもつ絶縁分離型単結晶基板
の製造を説明する。
Next, the production of an insulated single crystal substrate having the structure shown in FIG. 2 will be explained.

先ず基板21に、短冊状のマスクAを用いて、
通常の方法を用いてLOCOS酸化し、第2図に示
すような絶縁膜22と種結晶となる開口部28と
によるラインアンドスペースを作る。絶縁膜22
の厚さは、通常用いられる0.3〜1.0μmでよい。こ
の上に単結晶に変化せしめる非晶質層ないしは多
結晶質層(厚み0.2〜1.0μm)を全面に積載する。
First, using a strip-shaped mask A on the substrate 21,
LOCOS oxidation is performed using a conventional method to form lines and spaces between the insulating film 22 and the opening 28 which will serve as a seed crystal, as shown in FIG. Insulating film 22
The thickness may be 0.3 to 1.0 μm, which is commonly used. On top of this, an amorphous layer or a polycrystalline layer (thickness 0.2 to 1.0 μm) to be converted into a single crystal is laminated on the entire surface.

次に、#型のパターンにより矩形の窓を残すマ
スクBを用いて、絶縁部の開口部分25に相応す
る部分を残して多結晶質層に酸化ないしは窒化な
どの工程を施して絶縁部23及び24を形成す
る。この時、あらかじめ、この部分をエツチング
して厚さを約1/2に減少しておくことによつて
表面をほぼ平旦化することができる。
Next, using a mask B that leaves a rectangular window with a #-shaped pattern, the polycrystalline layer is subjected to a process such as oxidation or nitriding, leaving a portion corresponding to the opening portion 25 of the insulating portion. Form 24. At this time, by etching this portion in advance to reduce the thickness to about 1/2, the surface can be made almost flat.

又、この工程の前ないし後で、イオン注入など
によつて、種結晶となる開口部26と基板伸長部
27との界面状態が改善される。界面が汚れてい
る時には結晶成長が改善される。
Also, before or after this step, the state of the interface between the opening 26, which will serve as a seed crystal, and the substrate extension 27 is improved by ion implantation or the like. Crystal growth is improved when the interface is dirty.

さらに開口部26は、以上の工程で明らかなよ
うに絶縁膜22の端面と絶縁部の窓25の端面と
で形成されるため、例えば開口部26の一辺が
0.5μmであつても、カドが丸くならず、矩形がう
まく形成される。現在の通常のフオトリソグラフ
イによつてはこのような小さな開口部は作れず、
通常は丸い円形になつてしまう。このように正確
なカドを持つ矩形開口部はグラフオエピタキシー
で認められているように有効なレリーフの効果を
示し、本発明による良好な結晶性に寄与している
と考えられる。
Further, since the opening 26 is formed by the end face of the insulating film 22 and the end face of the window 25 of the insulating part, for example, one side of the opening 26 is
Even at 0.5 μm, the edges are not round and a rectangular shape is well formed. Such small openings cannot be created using current conventional photolithography;
Usually it becomes a round shape. It is believed that the rectangular opening with such precise corners exhibits an effective relief effect as recognized in grapho-epitaxy, and contributes to the good crystallinity according to the present invention.

次にエネルギービームを照射し、非晶質ないし
は多結晶である基板伸長部27を単結晶化する。
照射するビームは、パルスレーザ、CWレーザ、
エレクトロンビーム、赤外線、紫外線などいずれ
でもよく、短時間に基板伸長部27にエネルギー
が吸収され、溶解できればよい。本発明者らの検
討によれば、必要な照射エネルギーは、積層して
いる膜質や種類、さらに上にかぶせる保護膜など
の状態で異なる、基板温度によつても異なる。し
かしながら、本発明者らの検討では、CW−Arレ
ーザアニール装置の不安定性や微細積層構造の再
現性不良などの問題点はあるものの、基板温度
300〜500℃では基板への入照エネルギーは3〜
11W、走査速度は30mm/sec〜3m/secの範囲に
あつた。この時、溶融巾は、ほぼ30μm程度にな
つていた。
Next, an energy beam is irradiated to convert the amorphous or polycrystalline substrate extension 27 into a single crystal.
The beam to be irradiated can be pulsed laser, CW laser,
Any method such as an electron beam, infrared rays, or ultraviolet rays may be used, as long as the energy can be absorbed by the substrate extension portion 27 and melted in a short time. According to studies by the present inventors, the required irradiation energy varies depending on the quality and type of the laminated films, the state of the overlying protective film, etc., and also varies depending on the substrate temperature. However, according to the inventors' study, although there are problems such as instability of the CW-Ar laser annealing equipment and poor reproducibility of the fine laminated structure,
At 300 to 500℃, the incident energy to the board is 3 to 500℃.
11W, and the scanning speed was in the range of 30 mm/sec to 3 m/sec. At this time, the melt width was approximately 30 μm.

矩形の基板伸長部27にこのビームが照射して
いる時間は、約0.01〜1msecとなり、この短時
間に溶解、結晶成長が行われていることが分つ
た。パルスレーザアニールやエレクトロンビーム
アニールにおいても、ほぼこの時間に溶解、結晶
成長させれば、上述のCW−Arレーザによる再結
晶化した単結晶と同程度の品質のものが得られる
と推定される。
The time during which the rectangular substrate extension portion 27 is irradiated with this beam is about 0.01 to 1 msec, and it was found that melting and crystal growth were performed in this short time. Even in pulsed laser annealing or electron beam annealing, it is estimated that if melting and crystal growth are performed in approximately this time, a single crystal with the same quality as the single crystal recrystallized by the above-mentioned CW-Ar laser can be obtained.

さらに、本発明者らの簡単な実験の結果、結晶
欠陥の少ない良好な結晶を得るには、照射するビ
ーム半径は、ほぼ第1の絶縁膜22の上に伸びた
基板伸長部27の積載部29の長さよりも大きい
ことが必要であつた。このことは周辺を絶縁部2
3,24に囲まれた基板伸長部27の熱分布を考
えれば理解できる。即ち、種結晶28と絶縁層2
2との境界部分にビームの中心があり、ヒートシ
ンクであつても十分なエネルギーが照射されて、
種結晶の境界表面の一部が溶解して、種結晶の内
部から結晶成長が始まり、ついで、ヒートシンク
へ熱が一様に一軸性に即ち種結晶28の線に直角
に熱が流れる。したがつて、結晶成長も一様に熱
流と逆方向に進むと考えられる。もし、ビーム径
が、絶縁部の窓25より十分に小さければ、溶融
はスポツト状に生じ従つて熱流は、スポツトの中
心を向くように流れ、一軸性は失なわれる。さら
に、この場合には、同一の窓25内の基板伸長部
27を何度も走査することになり、同一窓内で部
分的な溶解や結晶成長が繰り返され、結晶の微小
な方位の差が生じたり、又、加熱冷却により歪や
欠陥の生成が多くなるといつた実験結果は理解さ
れる。
Furthermore, as a result of a simple experiment conducted by the present inventors, in order to obtain a good crystal with few crystal defects, the radius of the irradiated beam should be set approximately at the loading area of the substrate extension part 27 extending above the first insulating film 22. It was necessary that the length be greater than 29. This means that the surrounding insulation area 2
This can be understood by considering the heat distribution in the substrate extension portion 27 surrounded by 3 and 24. That is, the seed crystal 28 and the insulating layer 2
The center of the beam is at the boundary between 2 and 2, and even if it is a heat sink, sufficient energy is irradiated.
A portion of the boundary surface of the seed crystal melts and crystal growth begins from within the seed crystal, followed by a uniform uniaxial flow of heat to the heat sink, i.e. perpendicular to the lines of the seed crystal 28. Therefore, it is thought that crystal growth also uniformly proceeds in the opposite direction to the heat flow. If the beam diameter is sufficiently smaller than the window 25 of the insulation, melting will occur in the form of a spot and the heat flow will be directed towards the center of the spot and uniaxiality will be lost. Furthermore, in this case, the substrate extension 27 within the same window 25 is scanned many times, and partial melting and crystal growth are repeated within the same window, resulting in minute differences in crystal orientation. It is understandable that the experimental results show that heating and cooling increase the generation of distortion and defects.

このようにして得られた基板伸長部27の結晶
性は良好であるが、かなり熱応力が残留してい
る。又周囲の絶縁膜との間にも熱応力が残留して
いると考えられる。これを残去するために、700
〜1000℃30分程度の焼鈍は非常に効果がある。
Although the crystallinity of the substrate extension 27 thus obtained is good, considerable thermal stress remains. It is also considered that thermal stress remains between the surrounding insulating film and the surrounding insulating film. To leave this, 700
Annealing at ~1000℃ for about 30 minutes is very effective.

なお第2図において開口部26は、絶縁部の窓
25のほぼ中心位置においてあるが、どちらか一
方に片寄つても差しつかえないことはいうまでも
ない。又、開口部26直上の再結晶化部分を、さ
らに酸化しつくして基板伸長部27を二つにわけ
るように完全絶縁分離することも勿論可能であ
る。さらに開口部26の直上の再結晶化部をチヤ
ンネルにし、両側に延びた基板伸長部27をソー
スとドレインに使用しても、絶縁分離の大きな効
果があることは以上の論議から明らかである。
In FIG. 2, the opening 26 is located approximately at the center of the window 25 of the insulating portion, but it goes without saying that it may be located closer to either side. It is also possible, of course, to completely oxidize the recrystallized portion directly above the opening 26 to completely insulate and separate the substrate extension 27 into two. Furthermore, it is clear from the above discussion that even if the recrystallized portion directly above the opening 26 is used as a channel and the substrate extensions 27 extending on both sides are used for the source and drain, a great effect of insulation isolation can be obtained.

本発明は、以上の方法をもとに次の工程を実施
するものである。すなわち、(100)ないし(110)
主面を有する単結晶半導体基板上に、前記基板の
一部を残し短冊状の第1の絶縁膜を選択的に形成
し、前記基板および第1の絶縁膜上に非単結晶シ
リコン層を形成し、前記シリコン層の一部を選択
的に絶縁化して第2の絶縁膜とすることにより前
記基板の一部及びその両端の前記第1の絶縁膜上
にわたつて周辺が直線状の島状のシリコン層を形
成するとともに、前記島状のシリコン層の周辺面
が前記基板の(100)ないし(110)面に対してほ
ぼ平行又は直角になるように形成し、前記シリコ
ン層にエネルギービームを照射して結晶化する。
The present invention implements the following steps based on the above method. i.e. (100) to (110)
A first insulating film in a strip shape is selectively formed on a single crystal semiconductor substrate having a main surface, leaving a part of the substrate, and a non-single crystal silicon layer is formed on the substrate and the first insulating film. By selectively insulating a part of the silicon layer to form a second insulating film, an island shape with a straight periphery is formed over a part of the substrate and the first insulating film at both ends thereof. A silicon layer is formed, and the peripheral surface of the island-shaped silicon layer is formed to be approximately parallel or perpendicular to the (100) to (110) plane of the substrate, and an energy beam is applied to the silicon layer. Irradiate to crystallize.

また、基板主面を(111)面とし、シリコン層
の周辺面が(100)ないし(211)面に対してほぼ
平行又は直角であつてもよい。
Alternatively, the main surface of the substrate may be the (111) plane, and the peripheral surface of the silicon layer may be approximately parallel or perpendicular to the (100) to (211) planes.

第3図に別の例をあげる。半導体基板31上に
第1の絶縁膜32を例えばLPCVD法で形成す
る。前述と同様に短冊状に形成された絶縁膜32
上にさらに多結晶層を全面に載せ、前述の方法と
同様にして、絶縁部の開口部分35を囲むように
絶縁部33を形成する。以降の工程は前述の方法
と同じである。この例での特徴としては、絶縁膜
32の下に、あらかじめ素子を形成しておくこと
が比較的に容易にできるために、半導体基板の面
積を有効に利用しえるものである。
Figure 3 shows another example. A first insulating film 32 is formed on a semiconductor substrate 31 by, for example, the LPCVD method. The insulating film 32 is formed into a strip shape as described above.
A polycrystalline layer is further placed on the entire surface, and an insulating section 33 is formed to surround the opening 35 of the insulating section in the same manner as described above. The subsequent steps are the same as the method described above. A feature of this example is that it is relatively easy to form elements in advance under the insulating film 32, so that the area of the semiconductor substrate can be used effectively.

次に本発明の方法における開口部、絶縁部の窓
の方位について、第4図,第5図を用いて説明す
る。
Next, the orientation of the opening and the window of the insulating part in the method of the present invention will be explained using FIGS. 4 and 5.

本発明では、再結晶は種結晶から生ずるので方
位は制御されている。しかし、前述したように、
レリーフとして補助的な効果が大きい。したがつ
て種結晶と類似の対称を有したものが、結晶性に
優れているのは当然といえる。第4図,第5図で
は立方晶を有するSi結晶を例にとつて説明する。
なお簡便のため、例えば(100)面といえば、
100,010,001の等価を三面のいずれかを指すも
のとする。又、図中〈110〉方向は、以下の説明
でいう(110)面と直角方向である。
In the present invention, recrystallization occurs from a seed crystal, so orientation is controlled. However, as mentioned above,
It has a great auxiliary effect as a relief. Therefore, it is natural that a material having a symmetry similar to that of the seed crystal has excellent crystallinity. In FIGS. 4 and 5, an Si crystal having a cubic crystal structure will be explained as an example.
For the sake of simplicity, for example, speaking of (100) plane,
Let the equivalence of 100, 010, 001 refer to any of the three sides. Furthermore, the <110> direction in the figure is a direction perpendicular to the (110) plane in the following explanation.

本発明者らの検討によれば、第4図aに二つの
例を示すように、ほぼ(100)面を主平面とした
基板を使用した時は、第2図での矩形開口部26
及び絶縁部の窓25の周辺が〈110〉方向ないし
は〈100〉方向に、即ち(110)面ないしは(100)
面に各々ほぼ直角になつている時に一番よい結晶
性のものが得られた。これは、特にレリーフとな
つている矩形開口部26の対称性と種結晶の結晶
方位が一致していることからもうかがえる。
According to the studies of the present inventors, as shown in two examples in FIG. 4a, when using a substrate whose principal plane is approximately the (100) plane, the rectangular opening 26 in FIG.
And the periphery of the window 25 of the insulation part is in the <110> direction or in the <100> direction, that is, in the (110) plane or in the (100) direction.
The best crystallinity was obtained when each plane was approximately perpendicular to the other. This can be seen especially from the fact that the symmetry of the rectangular opening 26 serving as a relief matches the crystal orientation of the seed crystal.

第4図bに示すように、ほぼ(110)面を主平
面とした基板を使用した時には、第2図の矩形開
口部26及び絶縁部の窓25の周辺が各々(100)
面及び(110)面にほぼ垂直ないし平行になつて
いる時に、特によい結晶性のものが得られた。
As shown in FIG. 4b, when using a substrate whose main plane is approximately the (110) plane, the peripheries of the rectangular opening 26 and the window 25 of the insulating part in FIG. 2 are each (100).
Particularly good crystallinity was obtained when the crystallinity was approximately perpendicular or parallel to the (110) plane.

第5図に、ほぼ(111)面を主平面とした基板
を使用した時に、特に結晶性の優れた方位三例を
示してある。図に示すように、いずれの場合にお
いても、第2図での開口部26の周辺が(110)
ないしは(211)面のいずれかにほぼ垂直ないし
平行になつている。この内、特に結晶性の優れた
形状は、第5図aに示すもので、開口部26及び
絶縁部の窓27の周辺が各々(110)と(211)面
に平行になつており、矩形を形成している時であ
つた。
FIG. 5 shows three examples of orientations that have particularly excellent crystallinity when using a substrate whose main plane is approximately the (111) plane. As shown in the figure, in either case, the periphery of the opening 26 in Figure 2 is (110).
It is almost perpendicular or parallel to either the (211) plane or the (211) plane. Among these, the shape with particularly excellent crystallinity is shown in FIG. It was at the time when the

第5図b及びcに示すものは、(110)面ないし
は(211)面の片方のみに平行な周辺より成つて
おり、図からも分るように菱形をしている。第2
図での第1の絶縁層22の端部と第2の絶縁層2
3の端部が、直角でなく、60゜の角度で交わつて
いる。従つて、熱流を考えると少し対称性が崩れ
ており、一様性が少ないことから、余り結晶性が
優れないと思われるが、レリーフの効果が大きく
作用して、結果的には、良好な結晶性のものにな
つたと考えられる。前述の実施例に示したよう
に、第1と第2の絶縁層を二度に分けて形成する
ため、この60度の角度は鋭く形成されることも、
レリーフの効果が大きい理由になつていると思わ
れる。この時、第1と第2の絶縁層を一度に形成
すると当然カドの部分に丸みがつき、レリーフの
効果がなくなると思われる。
The one shown in FIGS. 5b and 5c consists of a periphery parallel to only one of the (110) and (211) planes, and as can be seen from the figures, it is rhombic. Second
The end of the first insulating layer 22 and the second insulating layer 2 in the figure
The ends of 3 intersect at a 60° angle instead of at a right angle. Therefore, considering the heat flow, the symmetry is slightly broken and there is little uniformity, so it seems that the crystallinity is not very good, but the effect of the relief is large and as a result, it is good. It is thought that it became crystalline. As shown in the above embodiment, since the first and second insulating layers are formed in two parts, this 60 degree angle may be formed sharply.
This seems to be the reason why the relief is so effective. At this time, if the first and second insulating layers are formed at the same time, the edges will naturally become rounded and the relief effect will be lost.

本発明において従来のブリツジングエピタキシ
ーや、シーデイドビームアニーリングと比べ、格
段によい結晶が得られているのは、このようなレ
リーフの効果と、本発明により導入された熱流制
御による結晶成長の制御によることは明らかであ
ろう。しかも結晶方位が正確に制御されている優
れたものである。
The reason why much better crystals are obtained in the present invention than in conventional bridging epitaxy or seeded beam annealing is due to the relief effect and the crystal growth by the heat flow control introduced by the present invention. It is clear that this is due to control. Moreover, it is an excellent product in which the crystal orientation is accurately controlled.

以下に本発明の限定的でない実施例をあげる。 The following are non-limiting examples of the invention.

実施例 1 ほぼ(100)面を主平面とする基板に、マスク
Aを用い、LOCOS法で第1の酸化層(第2図2
2)の巾15μm、種結晶の巾(第2図28)
1.5μmの交互に配置されたラインアンドスペース
を形成した。この上に、LPCVD法によつて多結
晶シリコンを約0.5μm厚積層した。この時基板温
度を500℃に保つた。次に巾4μm、長さ10μmの窓
と、巾4μmと長さ14μmの窓と、巾4μm、長さ
18μmの窓の三種の異なつた窓を有するマスクB
を用いて、第2図に示すように基板伸長部27を
囲む多結晶部を酸化し、第4図aに示すような配
置にして完全な酸化層にした。得られた窓の大き
さは、それぞれ、約3×9μm、3×13μm、3×
17μmであつた。この時、第1の絶縁膜上の積載
部(第2図29)の長さは、各々約3μm、5μm、
7μmであつた。
Example 1 Using mask A, the first oxide layer (see Fig. 2
2) Width 15 μm, width of seed crystal (Fig. 2 28)
Alternating lines and spaces of 1.5 μm were formed. On top of this, polycrystalline silicon was laminated to a thickness of about 0.5 μm using the LPCVD method. At this time, the substrate temperature was maintained at 500°C. Next, a window with a width of 4 μm and a length of 10 μm, a window with a width of 4 μm and a length of 14 μm, and a window with a width of 4 μm and a length of 10 μm.
Mask B with three different types of 18μm windows
2 to oxidize the polycrystalline portion surrounding the substrate extension 27 as shown in FIG. 2, forming a completely oxidized layer in the arrangement shown in FIG. 4a. The sizes of the obtained windows are approximately 3 × 9 μm, 3 × 13 μm, and 3 ×
It was 17μm. At this time, the lengths of the loading portion (FIG. 2 29) on the first insulating film are approximately 3 μm, 5 μm, and 5 μm, respectively.
It was 7μm.

CW−Arレーザ照射をつづけて行つた。基板温
度は約350℃、走査速度は30mm/sec、レーザエネ
ルギーは約5Wでこの時の溶融する多結晶Siの巾
は約25μmであつた。
CW-Ar laser irradiation was continued. The substrate temperature was approximately 350°C, the scanning speed was 30 mm/sec, the laser energy was approximately 5 W, and the width of the melted polycrystalline Si was approximately 25 μm.

得られた単結晶層を、セコーエツチ液で軽くエ
ツチした後、暗視野光学顕微鏡で調べた。上記の
三種の窓での単結晶化はうまく行われていること
が分つた。しかし、厚さ0.5μmの10倍以上になる
積載部をもつ窓、3×17μmについては、端部の
約2μmの所に小さな他方位の結晶が生じているこ
とが一部に認められた。この他の部分について
は、殆んど結晶欠陥が認められず優れた結晶であ
ることが分つた。
The obtained single crystal layer was lightly etched with Seco etchant and then examined with a dark field optical microscope. It was found that single crystallization using the above three types of windows was successfully carried out. However, for the 3 x 17 μm window, which has a loading area that is more than 10 times as thick as 0.5 μm, small crystals on the other side were partially observed at about 2 μm at the edge. In other parts, almost no crystal defects were observed, indicating that the crystal was excellent.

なお、端部に生じた微結晶の部分は、非常にわ
ずかの部分であるため、この部分を例えばソース
やドレイン又はコンタクトなどに使用すれば、結
晶方位の乱れによる悪影響を避けることができ
る。したがつて、このような利用をすれば使用に
耐えない品質不良の結晶でなくなることも判明し
た。
Note that the microcrystalline portion formed at the end is a very small portion, so if this portion is used, for example, as a source, drain, or contact, it is possible to avoid adverse effects due to disordered crystal orientation. Therefore, it has been found that if the crystals are used in this way, the crystals will no longer be of poor quality and cannot be used.

実施例 2 実施例1と同様の工程を経て、同様の構造の積
層型単結晶基板を作成した。但し、この時には、
マスクBを実施例1より15゜回転させた結果、矩
型ではなく、菱形の開口部が開いている。得られ
た基板伸長部の結晶性は、3×9μmの窓について
は良好であつたが、他の大きな二種の窓について
は満足すべきものでなく、種結晶の端から3〜
4μmの位置から欠陥や多結晶化がかなりのものに
認められた。
Example 2 A laminated single crystal substrate having a similar structure was created through the same steps as in Example 1. However, at this time,
As a result of rotating mask B by 15 degrees from Example 1, the opening is not rectangular but diamond-shaped. The crystallinity of the obtained substrate extension was good for the 3 x 9 μm window, but was not satisfactory for the other two large windows, and the
Considerable defects and polycrystalline formation were observed from the 4 μm position.

実施例 3 実施例1と同様の処理を行つた。但し、本実施
例では、CW−Arレーザ照射を約10W、走査速度
3000mm/secとした。この時の多結晶シリコンの
溶融巾は約30μmであつた。得られた単結晶の結
晶性は、ほぼ実施例1の結果と同じであつた。
Example 3 The same treatment as in Example 1 was carried out. However, in this example, CW-Ar laser irradiation was performed at approximately 10W and scanning speed.
It was set to 3000mm/sec. The melting width of the polycrystalline silicon at this time was about 30 μm. The crystallinity of the obtained single crystal was almost the same as that of Example 1.

実施例 4 実施例2と同様の処理を行つた。但し、CW−
Arレーザ照射を約4W、走査速度3000mm/secと
した。この時の多結晶シリコンの溶融巾は約
20μmであつた。得られた単結晶の結晶性はいず
れの窓のものについても欠陥が多く、粒界が多く
認められた。
Example 4 The same treatment as in Example 2 was carried out. However, CW-
The Ar laser irradiation was approximately 4 W and the scanning speed was 3000 mm/sec. The melting width of polycrystalline silicon at this time is approximately
It was 20μm. The crystallinity of the obtained single crystal had many defects and many grain boundaries were observed for all windows.

実施例 5 ほぼ(111)面を主平面とする基板を用い、実
施例1と同様の処理をした。窓の配置は、第5図
aに示す方位である。得られた単結晶の結晶性は
いずれも、実施例1と同様に優れたものであつ
た。
Example 5 The same process as in Example 1 was carried out using a substrate whose main plane was approximately the (111) plane. The arrangement of the windows is in the orientation shown in Figure 5a. The crystallinity of the obtained single crystals was as excellent as in Example 1.

実施例 6 実施例5と同様の検討を行つた。但し、この実
施例においては、窓の配置を第5図bおよびcに
示す方位にした。得られた単結晶の結晶性はいず
れもかなり良好であつたが実施例5のものより幾
分劣つていた。しかし、実施例2のものよりは優
れていた。
Example 6 The same study as in Example 5 was conducted. However, in this embodiment, the windows were arranged in the orientations shown in FIGS. 5b and 5c. The crystallinity of the obtained single crystals was all quite good, but was somewhat inferior to that of Example 5. However, it was better than that of Example 2.

実施例 7 実施例1と同様の実験を行つた。但し、本検討
では、多結晶シリコンを約0.3μmプラズマCVDで
形成した。この時の基板温度は約320℃であつた。
さらに酸化層の窓を形成した後、Si+を加速エネ
ルギー150Kevで5×1015/cm2注入し、エレクト
ロンビームアニーリングを行つた。その照射条件
は、加速エネルギー5Kev、電流3mA、基板温度
500℃、走査速度2000mm/secである。この時のシ
リコン層の溶融巾は約50μmを示した。得られた
単結晶層は、実施例1で得た結晶性とほぼ同じで
あり、レーザビームでも、エレクトロンビームで
もほぼ同じような結果が得られることが分つた。
Example 7 An experiment similar to Example 1 was conducted. However, in this study, polycrystalline silicon was formed using plasma CVD to a thickness of approximately 0.3 μm. The substrate temperature at this time was approximately 320°C.
After further forming an oxide layer window, Si + was implanted at 5×10 15 /cm 2 at an acceleration energy of 150 Kev, and electron beam annealing was performed. The irradiation conditions are acceleration energy 5Kev, current 3mA, and substrate temperature.
The temperature was 500°C and the scanning speed was 2000mm/sec. The melting width of the silicon layer at this time was approximately 50 μm. The obtained single crystal layer had almost the same crystallinity as that obtained in Example 1, and it was found that almost the same results could be obtained with a laser beam or an electron beam.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,bは従来より製造ないしは提案され
ている絶縁分離構造を示す断面図、第2図a,b
は本発明のにかかる絶縁分離搭載半導体基体の要
部断面図及び平面図、第3図は本発明にかかる他
の半導体基体の断面図、第4図a,b、第5図は
本発明の一実施例の方法における開口部及び絶縁
部の窓の方位を簡略に示す図である。 21,31……基板、22,23,24,33
……絶縁膜、25……絶縁部の窓、26……開口
部、27,37……基板伸長部。
Figures 1a and b are cross-sectional views showing conventionally manufactured or proposed insulation isolation structures, Figures 2a and b
3 is a cross-sectional view of another semiconductor substrate according to the present invention, and FIGS. 4a and 5 are cross-sectional views of another semiconductor substrate according to the present invention. FIG. 3 is a diagram schematically showing the orientation of an opening and a window of an insulating part in a method of one embodiment. 21, 31...Substrate, 22, 23, 24, 33
... Insulating film, 25 ... Window of insulating section, 26 ... Opening, 27, 37 ... Substrate extension part.

Claims (1)

【特許請求の範囲】 1 (100)ないし(110)主面を有する単結晶半
導体基板上に、前記基板の一部を残し短冊状の第
1の絶縁膜を選択的に形成し、前記基板および第
1の絶縁膜上に非単結晶シリコン層を形成し、前
記シリコン層の一部を選択的に絶縁化して第2の
絶縁膜とすることにより前記基板の一部及びその
両端の前記第1の絶縁膜上にわたつて周辺が直線
状の島状のシリコン層を形成するとともに、前記
島状のシリコン層の周辺面が前記基板の(100)
ないし(110)面に対してほぼ平行又は直角にな
るように形成し、前記シリコン層にエネルギービ
ームを照射して結晶化することを特徴とする半導
体基体の製造方法。 2 (111)主面を有する単結晶半導体基板上に、
前記基板の一部を残し短冊状の第1の絶縁膜を選
択的に形成し、前記基板および第1の絶縁膜上に
非単結晶シリコン層を形成し、前記シリコン層の
一部を選択的に絶縁化して第2の絶縁膜とするこ
とにより前記基板の一部及びその両端の前記第1
の絶縁膜上にわたつて周辺が直線状の島状のシリ
コン層を形成するとともに、前記島状のシリコン
層の周辺面が前記基板の(110)ないし(211)面
に対してほぼ平行又は直角になるように形成し、
前記シリコン層にエネルギービームを照射して結
晶化することを特徴とする半導体基体の製造方
法。
[Claims] 1. A first insulating film in the form of a strip is selectively formed on a single crystal semiconductor substrate having a (100) to (110) principal surface, leaving a part of the substrate, and A non-single crystal silicon layer is formed on the first insulating film, and a part of the silicon layer is selectively insulated to form a second insulating film, so that a part of the substrate and both ends of the first insulating film are formed. An island-shaped silicon layer with a straight periphery is formed over the insulating film of the substrate, and the peripheral surface of the island-shaped silicon layer is (100) of the substrate.
A method of manufacturing a semiconductor substrate, characterized in that the silicon layer is formed substantially parallel or perpendicular to the (110) plane, and crystallized by irradiating the silicon layer with an energy beam. 2. On a single crystal semiconductor substrate having a (111) main surface,
A strip-shaped first insulating film is selectively formed leaving a part of the substrate, a non-single crystal silicon layer is formed on the substrate and the first insulating film, and a part of the silicon layer is selectively formed. A part of the substrate and both ends of the first insulating film are insulated to form a second insulating film.
An island-shaped silicon layer with a straight periphery is formed over the insulating film, and the peripheral surface of the island-shaped silicon layer is substantially parallel or perpendicular to the (110) or (211) plane of the substrate. Form it so that it becomes
A method for manufacturing a semiconductor substrate, characterized in that the silicon layer is crystallized by irradiating the silicon layer with an energy beam.
JP57063757A 1982-04-15 1982-04-15 Semiconductor base body and its manufacture Granted JPS58180019A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57063757A JPS58180019A (en) 1982-04-15 1982-04-15 Semiconductor base body and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57063757A JPS58180019A (en) 1982-04-15 1982-04-15 Semiconductor base body and its manufacture

Publications (2)

Publication Number Publication Date
JPS58180019A JPS58180019A (en) 1983-10-21
JPH0413848B2 true JPH0413848B2 (en) 1992-03-11

Family

ID=13238579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57063757A Granted JPS58180019A (en) 1982-04-15 1982-04-15 Semiconductor base body and its manufacture

Country Status (1)

Country Link
JP (1) JPS58180019A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0612757B2 (en) * 1984-09-04 1994-02-16 工業技術院長 Method for manufacturing SOI film
JPH084066B2 (en) * 1985-04-10 1996-01-17 工業技術院長 Semiconductor single crystal growth method
JPH0693428B2 (en) * 1987-12-04 1994-11-16 工業技術院長 Method for manufacturing multilayer semiconductor substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56126914A (en) * 1980-03-11 1981-10-05 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56126914A (en) * 1980-03-11 1981-10-05 Fujitsu Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS58180019A (en) 1983-10-21

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