JPH0612757B2 - Method for manufacturing SOI film - Google Patents

Method for manufacturing SOI film

Info

Publication number
JPH0612757B2
JPH0612757B2 JP59183726A JP18372684A JPH0612757B2 JP H0612757 B2 JPH0612757 B2 JP H0612757B2 JP 59183726 A JP59183726 A JP 59183726A JP 18372684 A JP18372684 A JP 18372684A JP H0612757 B2 JPH0612757 B2 JP H0612757B2
Authority
JP
Japan
Prior art keywords
film
insulating film
substrate
single crystal
amorphous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59183726A
Other languages
Japanese (ja)
Other versions
JPS6163015A (en
Inventor
武光 國尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
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Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP59183726A priority Critical patent/JPH0612757B2/en
Publication of JPS6163015A publication Critical patent/JPS6163015A/en
Publication of JPH0612757B2 publication Critical patent/JPH0612757B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H01L21/02645—Seed materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は単結晶Ｓｉ基板上に形成されるＳＯＩ膜の製造
方法に関するものである。The present invention relates to a method for manufacturing an SOI film formed on a single crystal Si substrate.

（従来技術とその問題点） 従来ＳＯＩを形成するためのシードの形成方法として、
特開昭58-6121号公報，特開昭58-53821号公報、特開昭5
8-93220号公報に次のような方法が記載されている。単
結晶Ｓｉ基板上に絶縁パターンを形成し、その後Ｓｉの
選択エピタキシャルを行なって基板が露出している部分
にＳｉ膜をうめこんで平坦にし、この部分をシードとし
てＳＯＩを形成する。(Prior Art and Problems Thereof) As a method of forming a seed for forming a conventional SOI,
JP-A-58-6121, JP-A-58-53821, and JP-A-5
The following method is described in 8-93220. An insulating pattern is formed on a single crystal Si substrate, and then Si is selectively epitaxially grown to fill the exposed portion of the substrate with a Si film to make it flat, and an SOI is formed using this portion as a seed.

Ｓｉ基板は（100）面のものを用いることが多いが、基
板のオリエンテーションフラットは通常〈110〉方向に
設けられている。トランジスタ等のパターンはこれに平
行あるいは直角になるように形成される。つまり絶縁膜
パターンの各辺は〈110〉方向を向くわけである。する
と選択エピタキシャル成長において、絶縁膜と成長させ
るＳｉ膜の界面に、成長速度の遅い傾斜面（ファセット
と呼ばれる）が現われ平坦性が失なわれてしまう。つま
り絶縁膜とシード部の界面という最も平坦性の要求され
る部分に段差が生じてしまうわけであり、ビームアニー
ルには非常に不都合である。前記３つの公報には絶縁膜
パターンの向きは何ら記載されておらず、このような記
載のみでは表面が平坦なシード構造を得ることはできな
い。Although a Si substrate having a (100) plane is often used, the orientation flat of the substrate is usually provided in the <110> direction. The pattern of transistors or the like is formed so as to be parallel or at right angles to it. That is, each side of the insulating film pattern faces the <110> direction. Then, in the selective epitaxial growth, an inclined surface (called a facet) having a slow growth rate appears at the interface between the insulating film and the Si film to be grown, and the flatness is lost. In other words, a step is formed at the interface between the insulating film and the seed portion, which requires the most flatness, which is very inconvenient for beam annealing. The three publications do not describe the orientation of the insulating film pattern, and a seed structure having a flat surface cannot be obtained only by such description.

また特開昭58-93215号公報には次のように記載されてい
る。Ｓｉ基板の一部をエッチングし、その部分を熱酸化
して表面を平坦にする。そのあと多結晶Ｓｉ膜を堆積
し、Ｓｉイオン注入を施してこれを非晶質Ｓｉ膜とす
る。その後６００℃程度で熱処理すると固相エピタキシ
ャルによってSiO2膜上へ単結晶Ｓｉ部分が延びる。この
部分をシードとしてビームアニールする。この公報では
表面が平坦になると記載されているが、実際にこの方法
で表面を平坦化することは困難である。Ｓｉ基板を均一
にエッチングすることは実際には非常に困難である。エ
ッチング量にばらつきが生じるため熱酸化後の表面も必
ずしも全面が平坦にはならず、凹凸が残ってしまう。ビ
ームアニール条件はこのようなばらつきに非常に敏感で
あり、最適条件が非常に狭くなってしまうことになる。Further, JP-A-58-93215 discloses the following. A part of the Si substrate is etched and the part is thermally oxidized to flatten the surface. After that, a polycrystalline Si film is deposited and Si ion implantation is performed to form an amorphous Si film. After that, when heat-treated at about 600 ° C., a single crystal Si portion extends on the SiO 2 film by solid phase epitaxial growth. Beam annealing is performed using this portion as a seed. Although this publication describes that the surface becomes flat, it is difficult to actually flatten the surface by this method. It is actually very difficult to uniformly etch a Si substrate. Since the etching amount varies, the entire surface of the surface after thermal oxidation is not always flat and unevenness remains. The beam annealing condition is very sensitive to such variations, and the optimum condition becomes very narrow.

（発明の目的） 本発明の従来技術の欠点を除去し、絶縁膜上へシードが
延びた構造において、表面を平坦にすることができるＳ
ＯＩ膜の製造方法を提供することを目的とする。(Object of the Invention) It is possible to eliminate the drawbacks of the prior art of the present invention and flatten the surface in a structure in which a seed extends over an insulating film.
It is an object to provide a method for manufacturing an OI film.

（発明の構成） 本発明によれば、(100)Ｓｉ単結晶基板上に形成される
ＳＯＩ(Silicon on Insulator)膜の製造方法において、
前記基板上に絶縁膜を形成し、次いでこの絶縁膜に基板
にほぼ垂直でかつ基板面と平行な〈100〉方向を向いた
側壁を有する開口部を形成し、次に露出しているＳｉ基
板上に選択的にＳｉを前記絶縁膜とほぼ同一膜厚だけ気
相エピタキシャル成長させ、次に全面に非晶質Ｓｉ膜を
堆積し、次に熱処理を施して前記エピタキシャルＳｉ上
およびその近傍の絶縁膜上の非晶質Si膜を単結晶化し、
その絶縁膜上の単結晶化Si膜をシードとしてビームアニ
ールを行うことを特徴とするSOI膜の製造方法が得られ
る。(Structure of the Invention) According to the present invention, in a method for manufacturing an SOI (Silicon on Insulator) film formed on a (100) Si single crystal substrate,
An insulating film is formed on the substrate, and then an opening having a side wall facing the <100> direction which is substantially perpendicular to the substrate and parallel to the substrate surface is formed in the insulating film, and then the exposed Si substrate Selectively, Si is vapor-phase epitaxially grown to a film thickness of about the same as the insulating film, an amorphous Si film is then deposited on the entire surface, and then heat treatment is performed to form an insulating film on and near the epitaxial Si. Single crystallize the above amorphous Si film,
A method for manufacturing an SOI film is obtained, which is characterized in that beam annealing is performed using the single-crystallized Si film on the insulating film as a seed.

（実施例） 本発明については、実施例を示す図面を参照して説明す
る。(Example) The present invention will be described with reference to the drawings illustrating an example.

まず第１図(a)に示すように(100)単結晶Ｓｉ基板１に層
間絶縁膜２として厚さ１μｍのSiO2膜を熱酸化法で形成
し、その後ＣＦ４にＨ2を添加したガスを用いた異方性
エッチングでSiO2膜２を一部除去し、垂直な側壁を有す
る開口部５を設けた。開口部５のSiO2膜の各辺は基板と
平行な〈100〉方向と平行になるようにした。エッチン
グの条件としては13.56MHzの平行平板型装置を用い、Ｃ
Ｆ４100sccm,H220sccm，入力パワー２００Ｗである。First, as shown in FIG. 1 (a), a SiO 2 film having a thickness of 1 μm is formed as an interlayer insulating film 2 on a (100) single crystal Si substrate 1 by a thermal oxidation method, and then CF 4 is added with H 2 gas. Part of the SiO 2 film 2 was removed by anisotropic etching using, and an opening 5 having a vertical sidewall was provided. Each side of the SiO 2 film in the opening 5 was made parallel to the <100> direction parallel to the substrate. As the etching conditions, a parallel plate type device of 13.56 MHz was used, and C
F 4 100sccm, H 2 20sccm, input power 200W.

その後、開口部５内のＳｉ基板上のみに、Ｓｉを選択的
に気相エピタキシャル成長させ、第１図(b)に示すよう
に、開口部５を単結晶Si6によりほぼ埋めた。エピタキ
シャルの原料ガスとしては、SiH2Ｃl2/H2，温度950℃，
圧力50Torrである。After that, Si was selectively vapor-phase epitaxially grown only on the Si substrate in the opening 5, and the opening 5 was almost filled with single crystal Si6 as shown in FIG. 1 (b). The epitaxial source gas is SiH 2 Cl 2 / H 2 , temperature 950 ° C.,
The pressure is 50 Torr.

このように絶縁膜パターンを〈100〉方向に平行にする
と、絶縁膜とエピタキシャルＳｉが接する部分は開口部
の四隅を除けば平坦になる。四隅の部分は通常のリソグ
ラフィ技術を用いる限り絶縁膜が丸みをおび、ファセッ
トがわずかに現われる。しかしこれは微小であり実際に
は障害にはならない。When the insulating film pattern is made parallel to the <100> direction in this manner, the contact portion between the insulating film and the epitaxial Si becomes flat except for the four corners of the opening. The insulating film is rounded at the four corners so that facets are slightly visible as long as the ordinary lithography technique is used. However, this is so small that it does not actually become an obstacle.

さらに、第１図(c)に示すように、多結晶Ｓｉ層７をＬ
ＰＣＶＤ法により堆積させた。厚さは0.5μｍである。
この多結晶Ｓｉ層７にＳｉイオン注入(100Ke,V,1×1016
cm-2および180KeV,1×1016cm-2の２重注入）を施すこと
により、多結晶Ｓｉ層７は第１図(d)に示すように非晶
質Si層８に変化する。Further, as shown in FIG. 1 (c), the polycrystalline Si layer 7 is formed into L
It was deposited by the PCVD method. The thickness is 0.5 μm.
Si ion implantation (100 Ke, V, 1 × 10 16
Double implantation of cm −2 and 180 KeV and 1 × 10 16 cm −2 ) changes the polycrystalline Si layer 7 into an amorphous Si layer 8 as shown in FIG. 1 (d).

つぎに電気炉中で６００℃，２時間の熱処理を施すこと
により、単結晶Si6より固相エピタキシャルが生じ、第
１図(e)に示すように、単結晶Si6上および単結晶Si6に
近接した絶縁膜２上の非晶質Ｓｉは単結晶Si9へと結晶
性が向上する。単結晶Ｓｉ部９の中で絶縁膜２上に形成
された単結晶Ｓｉ部分１０は絶縁膜２の端部から横方向
へ５μｍていど伸びる。この部分をシードとして、Ar+
レーザを用いて、パワー3.25〜3.75Ｗ（最適範囲）ビー
ム走査速度100mm/sec，ビーム径10〜20μｍでアニール
することにより、SiO2膜２上の残りの非晶質Ｓｉ層８は
第１図(f)に示すようにすべて単結晶Ｓｉ層９となる。Next, by performing heat treatment at 600 ° C. for 2 hours in an electric furnace, solid phase epitaxial is generated from the single crystal Si6, and as shown in FIG. The crystallinity of the amorphous Si on the insulating film 2 is improved to single crystal Si9. The single crystal Si portion 10 formed on the insulating film 2 in the single crystal Si portion 9 extends laterally from the end portion of the insulating film 2 by 5 μm. Using this part as a seed, Ar +
The remaining amorphous Si layer 8 on the SiO 2 film 2 is formed by annealing with a laser at a power of 3.25 to 3.75 W (optimum range), a beam scanning speed of 100 mm / sec, and a beam diameter of 10 to 20 μm. As shown in (f), all become the single crystal Si layer 9.

（発明の効果） 本発明の方法を用いればシード部分が極めて平坦になる
ので、従来の方法に比べてビームアニールの際の光学系
やビーム出力の変動に対するマージンが広くなりＳＯＩ
形成の再現性が向上する。具体的にArレーザアニールの
場合で前記特開昭58-93215号公報記載の従来方法と比較
すると、他の条件を同じにした場合、Arレーザ出力の最
適範囲はこの従来方法では、3.40〜3.60Wと考えられる
が、前記実施例では3.25〜3.75Wもあり、本発明の方が
マージンが広くなることがわかる。(Advantages of the Invention) Since the seed portion becomes extremely flat by using the method of the present invention, the margin for the fluctuation of the optical system and the beam output at the time of beam annealing becomes wider than that of the conventional method, and the SOI is increased.
The reproducibility of formation is improved. Specifically, in the case of Ar laser annealing, as compared with the conventional method described in JP-A-58-93215, when other conditions are the same, the optimum range of Ar laser output is 3.40 to 3.60 in this conventional method. Although it is considered to be W, there is also 3.25 to 3.75 W in the above embodiment, which shows that the present invention has a wider margin.

【図面の簡単な説明】[Brief description of drawings]

第１図(a)〜(f)は本発明の実施例を説明するための断面
図。 図において、 １……単結晶Ｓｉ基板、２……絶縁膜、７……多結晶Ｓ
ｉ、５……開口部、６，９……単結晶Ｓｉ、８……非晶
質Ｓｉ、10……絶縁膜上の単結晶Ｓｉ1 (a) to 1 (f) are sectional views for explaining an embodiment of the present invention. In the figure, 1 ... Single crystal Si substrate, 2 ... Insulating film, 7 ... Polycrystalline S
i, 5: opening, 6, 9: single crystal Si, 8: amorphous Si, 10: single crystal Si on insulating film

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】(100)Si単結晶基板上に形成されるSOI(Sil
icon on Insulator)膜の製造方法において、前記基板上
に絶縁膜を形成し、次いでこの絶縁膜に基板にほぼ垂直
でかつ基板面と平行な〈100〉方向を向いた側壁を有す
る開口部を形成し、次に露出しているSi基板上に選択的
にSiを前記絶縁膜とほぼ同一膜厚だけ気相エピタキシャ
ル成長させ、次に全面に非晶質Si膜を堆積し、次に熱処
理を施して前記エピタキシャルSiおよびその近傍の絶縁
膜上の非晶質Si膜を単結晶化し、その絶縁膜上の単結晶
化Si膜をシードとしてビームアニールを行なうことを特
徴とするSOI膜の製造方法。1. An SOI (Sil) formed on a (100) Si single crystal substrate.
icon on insulator) film manufacturing method, an insulating film is formed on the substrate, and then an opening is formed in the insulating film, the opening having a side wall oriented in a <100> direction substantially perpendicular to the substrate and parallel to the substrate surface. Then, Si is selectively vapor-deposited on the exposed Si substrate to a thickness of about the same as the insulating film, and then an amorphous Si film is deposited on the entire surface, followed by heat treatment. A method of manufacturing an SOI film, wherein the epitaxial Si and an amorphous Si film on an insulating film in the vicinity thereof are single-crystallized, and beam annealing is performed using the single-crystallized Si film on the insulating film as a seed.
JP59183726A 1984-09-04 1984-09-04 Method for manufacturing SOI film Expired - Lifetime JPH0612757B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59183726A JPH0612757B2 (en) 1984-09-04 1984-09-04 Method for manufacturing SOI film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59183726A JPH0612757B2 (en) 1984-09-04 1984-09-04 Method for manufacturing SOI film

Publications (2)

Publication Number Publication Date
JPS6163015A JPS6163015A (en) 1986-04-01
JPH0612757B2 true JPH0612757B2 (en) 1994-02-16

Family

ID=16140885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59183726A Expired - Lifetime JPH0612757B2 (en) 1984-09-04 1984-09-04 Method for manufacturing SOI film

Country Status (1)

Country Link
JP (1) JPH0612757B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6336515A (en) * 1986-07-30 1988-02-17 Sony Corp Manufacture of thin single-crystal semiconductor film
JPS6489512A (en) * 1987-09-30 1989-04-04 Sharp Kk Manufacture of single crystal silicon film
JPH0282575A (en) * 1988-09-19 1990-03-23 Toshiba Corp Semiconductor device and its manufacture
JP2755214B2 (en) * 1995-06-12 1998-05-20 ソニー株式会社 Method of forming semiconductor thin film
FR2897982B1 (en) * 2006-02-27 2008-07-11 Tracit Technologies Sa METHOD FOR MANUFACTURING PARTIALLY-LIKE STRUCTURES, COMPRISING AREAS CONNECTING A SURFACE LAYER AND A SUBSTRATE

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58180019A (en) * 1982-04-15 1983-10-21 Matsushita Electric Ind Co Ltd Semiconductor base body and its manufacture

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