JPS60183718A - Crystallizing method of semiconductor thin film - Google Patents

Crystallizing method of semiconductor thin film

Info

Publication number
JPS60183718A
JPS60183718A JP59041069A JP4106984A JPS60183718A JP S60183718 A JPS60183718 A JP S60183718A JP 59041069 A JP59041069 A JP 59041069A JP 4106984 A JP4106984 A JP 4106984A JP S60183718 A JPS60183718 A JP S60183718A
Authority
JP
Japan
Prior art keywords
thin film
thin films
polycrystalline silicon
semiconductor thin
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59041069A
Other languages
Japanese (ja)
Inventor
Yasuo Kano
狩野　靖夫
Setsuo Usui
碓井　節夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP59041069A priority Critical patent/JPS60183718A/en
Publication of JPS60183718A publication Critical patent/JPS60183718A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02678—Beam shaping, e.g. using a mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

Abstract

PURPOSE:To provide recrystallized thin films whose plane orientations are aligned, without resulting grain boundaries or cracks in island areas, by forming narrower portions with a specific shape in a belt-shape semiconductor thin film. CONSTITUTION:An SiO2 film 2 and a polycrystalline silicon layer are coated on a quartz plate 1. Thereafter, when belt-shape polycrystalline silicon thin films 4 are formed using etching, narrower portions 5 are formed so as to become L/l>=2.5, where L is a width in a direction orthogonal to the longitudinal direction of the thin film 4 or the scanning direction A of laser beams and l is a width of the narrower portions in the same direction. Next, an SiO2 layer 7 is deposited thereon to form a silicon substrate 8. On the silicon substrate 8 the laser beams are scanned to recrystallize polycrystalline silicon thin films. In this way, in the island areas 6, single crystal silicon thin films whose plane orientations are aligned and which do not result in cracks are formed.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、多結晶又は非結晶質の半導体？・、７　ＪＩ
ｚ’ｌＧを加熱溶融して再結晶化させる半導体薄膜の結
晶化方法に関する。[Detailed Description of the Invention] Industrial Application Field Is the present invention applicable to polycrystalline or amorphous semiconductors?・,7 JI
The present invention relates to a method for crystallizing a semiconductor thin film in which z'lG is melted and recrystallized by heating.

背景技術とその問題点 絶縁基板又は絶縁層上に形成した多結晶シリコン薄膜を
レーデ・ビーム、電子ビーム、カーぎン。Background technology and its problems A polycrystalline silicon thin film formed on an insulating substrate or an insulating layer is deposited using a Rede beam, an electron beam, or a Cargin beam.

ヒータ等を使用して加熱溶融し、得られた単結晶のシリ
コンＮ膜を用いて高速ＩＣ，三次元ＩＣ、液晶表示装置
（ＬＣＤ）等を製作することが行なわれている（いわゆ
る５ＯＩ（Ｓｉｌｉｃｏｎ　ｏｎ　Ｉｎａｕｌａｔ、ｏ
ｒ）技術＼このよう４　ＳＯＩ技術においては、従来状
のような問題点があった。即ち、特に種結晶のない石英
基板上に形成した多結晶シリコン薄膜を再結晶化しよう
とする場合、得られた単結晶薄膜には粒界が入っていて
完全な単結晶にはならなかったことである。壕だ、特に
加熱溶融手段としてレーザを用いた場合には、イｑられ
た単結晶薄膜の面方位がｔｌｊｉｌわす、基板の全面に
わたって同じ面方位を持たぜることかできなかった。な
お、カー＋ＪＦン・ヒータを用いた場合には、粒界は多
数発生するが、面方位の４ｒ：’ａつだ単結晶薄膜がイ
与られる。更に、絶縁ノ、（：板が石英の場合、このＳ
ＯＩ技術によると熱膨張係数の差によりクラックが多数
発生するという問題点もある◎ 発明の目的 本発明は、上記の問題点、即ち粒界の発生等を解決する
ことができ、例えば液晶表示装置、高速ＩＣ用のシリコ
ン薄膜として好適な半導体薄膜の結晶化方法を提供する
ものである。High-speed ICs, three-dimensional ICs, liquid crystal displays (LCDs), etc. are manufactured using the single-crystal silicon N film obtained by heating and melting it using a heater, etc. (so-called 5OI (Silicon on Inaulat, o
r) Technology\Like this 4 SOI technology has had the same problems as before. In other words, especially when attempting to recrystallize a polycrystalline silicon thin film formed on a quartz substrate without seed crystals, the resulting single crystal thin film contains grain boundaries and does not become a perfect single crystal. It is. Especially when a laser is used as a heating and melting means, it is impossible to make the plane orientation of the equated single crystal thin film the same over the entire surface of the substrate. Note that when a Kerr+JF heater is used, a large number of grain boundaries are generated, but a single crystal thin film with a 4r:'a plane orientation is obtained. Furthermore, insulation (: If the plate is made of quartz, this S
OI technology also has the problem that many cracks occur due to differences in thermal expansion coefficients.Purpose of the InventionThe present invention can solve the above problems, such as the occurrence of grain boundaries, and can be used, for example, in liquid crystal display devices. , provides a method for crystallizing a semiconductor thin film suitable as a silicon thin film for high-speed ICs.

発明の概要 本発明は、基板に形成された帯状半７ｊＱ体薄股をその
長手方向に加熱溶融手段を走査させることにより再結晶
化させる半導体薄膜の結晶化方法において、帯状半導体
薄膜に狭隘部を形成し、長手方向と直交する方向の幅を
それぞれり、ｔとし７た場合、Ｉ、／＆２；ｔ；とした
ことを特徴とする半導体簿膜の結晶化方法である。SUMMARY OF THE INVENTION The present invention provides a method for crystallizing a semiconductor thin film in which a semiconductor thin film is recrystallized by scanning a heating melting means in the longitudinal direction of a strip-shaped half-7jQ body thin strip formed on a substrate. This is a method for crystallizing a semiconductor film, characterized in that the width in the direction perpendicular to the longitudinal direction is I, /&2;t;

本結晶化方法により、結晶面の方位が４ｉｉｉｉつた半
導体簿膜を得ることができる。By this crystallization method, it is possible to obtain a semiconductor film with crystal plane orientations of 4iii.

実施例 本発明においては、再結晶化される帯状半導体薄膜にそ
の幅が狭くなる部位、即ち狭隘部をその幅に所定の東件
を持たせて１つ又は検数形成するようにしたものであり
、この＋７’Ｊ成に基づくシリコン基板の製造例を図面
ｆ：参照して酸１明する。Embodiment In the present invention, a band-shaped semiconductor thin film to be recrystallized is formed with one or a number of narrow portions, that is, narrow portions with a predetermined width. An example of manufacturing a silicon substrate based on this +7'J structure will be described below with reference to FIG.

先ず、第１図に示すように、石英板（１）に３０００λ
厚程度のＳ　ｉ０２　Ｍ（２）をＣＶＤで形成すること
によシ、この石英板（１）を純粋な５ＩＯ２で被央し、
次に減圧ＣＶＤによシ多結晶シリコン層（３）を堆積す
る。次に、第２図の断面図及び第３図の平面図に示すよ
うに、この多結晶シリコン層（３）をエツチングして帯
状多結晶シリコン薄膜（４）を形成する際、同時にこの
帯状多結晶シリコン薄膜（４）に適当な間１ｉをもって
複数の狭隘部（５）を設ける。本発明においては、特に
Ｒ’Ｘ　ＪＩＪ　（４）の長手方向即ちレーザ・ビーム
の走査方向Ａと直交する方向の幅ＱＬ、狭隘部（５）の
同じ方向の幅をｔとした場合、Ｌ／４”８２．５、好寸
しくはＩＪ１２−．３．０となるようにラー１ζ隘部（
５）の大きさを遠足する。First, as shown in Figure 1, a 3000λ
By forming S i02 M (2) with a thickness of about
Next, a polycrystalline silicon layer (3) is deposited by low pressure CVD. Next, as shown in the cross-sectional view of FIG. 2 and the plan view of FIG. A plurality of narrow portions (5) are provided in the crystalline silicon thin film (4) with appropriate distances 1i. In the present invention, in particular, when the width QL of R'X JIJ (4) in the longitudinal direction, that is, the direction perpendicular to the scanning direction A of the laser beam, and the width of the narrow part (5) in the same direction are t, L/ 4”82.5, preferably IJ12-.3.0, at the 1ζ neck (
5) Excursion the size of.

両狭隘部（５）によって形成される島状領域（６）の大
きさは、長手方向の一辺をＴとすると、Ｔは１００μ以
下、Ｌは１００μ以下が好ましい。本実施例においては
、Ｔは６０μ、Ｌは３０μ、ｔは１０μ、狭隘部（５）
の横幅【は１０μとする。次に、第４図に示すように、
第２図に示す基板の上にキャップ層となるＳ　ｉＯ２Ｊ
脅（７）をＣＶＤで堆積して、本発明に係るシリコン基
板（８）をイＩＩる。As for the size of the island region (6) formed by both narrow parts (5), where one side in the longitudinal direction is T, it is preferable that T is 100 μm or less and L is 100 μm or less. In this example, T is 60μ, L is 30μ, t is 10μ, and the narrow part (5)
The width [is assumed to be 10μ. Next, as shown in Figure 4,
SiO2J which becomes a cap layer on the substrate shown in Fig. 2
A silicon substrate (8) according to the present invention is prepared by depositing a silicon substrate (7) by CVD.

この帯状多結晶シリコン薄膜（４）に対して加熱溶融手
段としてレーザを選んだ場合、このシリコン基板（８）
を５００℃程度に加熱した固定ヒータ（図示せず）に載
せた後、ビーム径を島状領域（６）の縦幅りより充分大
きくしたレーザ・ビームを帯状多結晶シリコン薄膜（４
）の長手方向、即ち第３図に示す入方向に走査させる。When a laser is selected as the heating and melting means for this strip-shaped polycrystalline silicon thin film (4), this silicon substrate (8)
is placed on a fixed heater (not shown) heated to approximately 500°C, and then a laser beam whose beam diameter is sufficiently larger than the vertical width of the island-shaped region (6) is applied to the strip-shaped polycrystalline silicon thin film (4).
), that is, in the incoming direction shown in FIG.

レーザ・ビームの走査速度は、結晶面の方位を揃えるた
めには低速の１〜２　ｍｒｔｌｓｅｃ程度が良い。この
レーザ・ビームは、照射面においてがウス型のエネルギ
ー分布を有するものでも良いが、できれば走査方向に対
してに１角に平ｊ旦なエネルギー分布を有する線状ビー
ムの方が好ましい。本発明に係るシリコン基板にレーザ
・ビームを走査させ、多結晶シリコン薄膜を再結晶化さ
せることにより得られた島状領域（６）内の単結晶シリ
コン薄膜は、結晶面の方位が揃っており、クラックの発
生も見られない。これは、所定形状の狭隘部（５）を形
成することによシ、帯状多結晶シリコン薄膜（４）を複
数の小さな島状領域（６）に分画したので、結晶核を多
発させないで、１箇の核からの結晶化が進み、また石英
板（１）と薄膜（４）の熱膨張率のｉＡいによって生ず
る歪が狭隘部（５）でのみクラックを発生きせ・ている
ためである。The scanning speed of the laser beam is preferably a low speed of about 1 to 2 mrtlsec in order to align the orientations of the crystal planes. Although this laser beam may have a wedge-shaped energy distribution on the irradiation surface, it is preferably a linear beam that has an energy distribution that is parallel to one angle with respect to the scanning direction. The monocrystalline silicon thin film in the island-like region (6) obtained by scanning the silicon substrate with a laser beam and recrystallizing the polycrystalline silicon thin film according to the present invention has crystal planes aligned in orientation. , no cracks were observed. This is because the band-shaped polycrystalline silicon thin film (4) is divided into a plurality of small island-like regions (6) by forming a narrow part (5) of a predetermined shape, so that crystal nuclei are not generated too many times. This is because crystallization from one nucleus progresses and the strain caused by the difference in thermal expansion coefficient iA between the quartz plate (1) and the thin film (4) causes cracks to occur only in the narrow part (5). .

発明の効果 本発明によれば、帯状半導体猿股に所定形状の狭隘部を
形成したことにより、島状領域内には粒界及びクラック
の発生がなく、また面方位の４６１１つた再結晶薄膜を
イ（ｌることかできる。Effects of the Invention According to the present invention, by forming a narrow portion of a predetermined shape in a semiconductor strip, no grain boundaries or cracks occur in the island-like region, and a recrystallized thin film with a 4611 plane orientation can be formed. (I can do that.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図及び第４図は本発明において使用するシ
リコン基板の製法例を示す断面図、第３図は第２図の平
面図である。 （１）　Ｉｒ、Ｊ：、　石英板、（２）はＳ　ｉ　Ｏ２
ＪＮｔ’、、（３）は多結晶シリコン層、（４）は帯状
多結晶シリコン可脱、（５）は狭隘部、（６）は島状領
域、（７）は５ｉＯ２Ｊｉづ、（８）はシリコン基板で
ある。 同　松　隈　秀　盛７．；７７、、。 ・：毒　、、１１ １１1, 2, and 4 are cross-sectional views showing an example of a method for manufacturing a silicon substrate used in the present invention, and FIG. 3 is a plan view of FIG. 2. (1) Ir, J:, quartz plate, (2) S i O2
JNt', (3) is a polycrystalline silicon layer, (4) is a band-shaped polycrystalline silicon layer, (5) is a narrow part, (6) is an island region, (7) is 5iO2Jizu, (8) is It is a silicon substrate. Same as Hidemori Matsukuma 7. ;77,,.・: Poison ,, 11 11

Claims (1)

【特許請求の範囲】[Claims] 基板に形成された帯状半導体薄膜をその長手方向に加熱
溶融手段を走査させることによシ再結晶化させる半導体
薄膜の結晶化方法において、上記帯状半導体薄膜に狭隘
部を形成し、長手方向と直交する方向の幅をそれぞれＬ
Ｘｔとした場合、しな２．５としたことを特徴とする半
導体薄膜の結晶化方法。In a method for crystallizing a semiconductor thin film formed on a substrate by recrystallizing the strip-shaped semiconductor thin film by scanning a heating melting means in its longitudinal direction, a narrow portion is formed in the strip-shaped semiconductor thin film and the narrow portion is perpendicular to the longitudinal direction. The width in each direction is L
A method for crystallizing a semiconductor thin film, characterized in that when Xt is 2.5, the elongation is 2.5.
JP59041069A 1984-03-02 1984-03-02 Crystallizing method of semiconductor thin film Pending JPS60183718A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59041069A JPS60183718A (en) 1984-03-02 1984-03-02 Crystallizing method of semiconductor thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59041069A JPS60183718A (en) 1984-03-02 1984-03-02 Crystallizing method of semiconductor thin film

Publications (1)

Publication Number Publication Date
JPS60183718A true JPS60183718A (en) 1985-09-19

Family

ID=12598151

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59041069A Pending JPS60183718A (en) 1984-03-02 1984-03-02 Crystallizing method of semiconductor thin film

Country Status (1)

Country Link
JP (1) JPS60183718A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0282518A (en) * 1988-09-20 1990-03-23 Agency Of Ind Science & Technol Manufacture of semiconductor single crystal layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0282518A (en) * 1988-09-20 1990-03-23 Agency Of Ind Science & Technol Manufacture of semiconductor single crystal layer

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