JPS58184720A - Manufacture of semiconductor film - Google Patents
Manufacture of semiconductor filmInfo
- Publication number
- JPS58184720A JPS58184720A JP57068467A JP6846782A JPS58184720A JP S58184720 A JPS58184720 A JP S58184720A JP 57068467 A JP57068467 A JP 57068467A JP 6846782 A JP6846782 A JP 6846782A JP S58184720 A JPS58184720 A JP S58184720A
- Authority
- JP
- Japan
- Prior art keywords
- region
- film
- silicon layer
- silicon oxide
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02683—Continuous wave laser beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
Abstract
Description
【発明の詳細な説明】
本発明は、製御され九位置に単結１域を有するような半
導体膜を非晶質絶縁基板上に形成するようＫし九半導体
膜の！ｌ造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to the formation of a semiconductor film having single crystal regions at nine positions on an amorphous insulating substrate. This invention relates to a manufacturing method.
絶縁基板上の単結晶半導体膜を用い丸集積回路素子は、
素子間の分離が容品であ〉、また寄生容量を低減するこ
とができることから高１！度化・高速化に適している。Round integrated circuit elements using a single crystal semiconductor film on an insulating substrate are
The isolation between elements is excellent, and parasitic capacitance can be reduced, so it is ranked high! Suitable for speeding up and increasing speed.
とりわけ非晶質絶縁基板上の華結晶半導体膜は、三次元
ＩＣを可能にするとじて注目されている。絶縁基板上に
単結晶半導体膜を形成する方法としては、絶縁基板とし
て単結晶を用い、シリコン−オン・サファイアやシリコ
ン・オン・スピネルのように単結晶基板上に単結晶半導
体膜を成長する方法、非晶質絶縁基板上に多結晶あるい
は非晶質のシリコンを堆積しレーザ等のビーム・アニー
ルを用いて再結晶化する方法、非晶質絶縁基板上に多結
晶あるいは非晶質のシリコンを堆積しヒーターで溶かし
て再結晶化する方法などがある。現段階では、こうした
絶縁基板上のシリコン（８ｉ１ｉｃｏｎ Ｏｎ Ｉｎ５
ｕｌａｔｏｒ 以下８０Ｉと略す）Ｆｉ１層だけである
が、三次元化を図るとすると１層目に作った素子の特性
を悪化させずに２層目を作ることを考えなければならな
くなる。エビ成長の温度を大ｌＩＫ下げる方法が得られ
ないとすれば、３Ｊ１在行われている方法のうちで三次
元化に対応できる方法社、絶縁基板上に形成した多結晶
又は非晶質層にレーザ・ビームや電子ビームを照射する
ビーム・アニールを用いた方法が考えられる。In particular, a crystalline semiconductor film on an amorphous insulating substrate is attracting attention as it enables three-dimensional ICs. A method for forming a single crystal semiconductor film on an insulating substrate is to use a single crystal as the insulating substrate and grow a single crystal semiconductor film on a single crystal substrate such as silicon-on-sapphire or silicon-on-spinel. , a method in which polycrystalline or amorphous silicon is deposited on an amorphous insulating substrate and recrystallized using beam annealing such as a laser; a method in which polycrystalline or amorphous silicon is deposited on an amorphous insulating substrate; There are methods such as depositing it, melting it with a heater, and recrystallizing it. At present, silicon on such an insulating substrate (8i1icon On In5
ulator (hereinafter abbreviated as 80I) is only one Fi layer, but if three-dimensionalization is to be achieved, it is necessary to consider creating a second layer without deteriorating the characteristics of the element created in the first layer. If we cannot find a way to lower the temperature for shrimp growth by a large degree, one of the currently available methods that can be applied to three-dimensional systems is a polycrystalline or amorphous layer formed on an insulating substrate. A method using beam annealing that irradiates with a laser beam or an electron beam is considered.
ビーム・アニールを用い丸方法ハ、 シー Ｖ （８ｅ
＠ｄ）としてシリコンを用い友方法と、シードを用いな
い方法に大別できる。どちらの方法４単結晶域の大きさ
は数ミクロンから数十ミクロンであるが。Round method using beam annealing, Sea V (8e
@d) It can be roughly divided into a method using silicon and a method not using seeds. In both methods, the size of the single crystal region is from a few microns to several tens of microns.
このサイズが三次元化を考えた場合問題と１に−）てく
る、シードを用いる方法では、ビーム・アニールの影響
が下層に及ばないようＫする丸めには。This size becomes a problem when three-dimensionalization is considered.In the method using a seed, it is necessary to round off K so that the influence of beam annealing does not reach the lower layer.
下層の素子の領域とシードの領域とを分離する必要があ
り、ｔた層数が多くなるほど目合わせの必要上シード領
域を大きくとらなくてはならず、集積度はシードがない
方法に較ぺて小さい、を九。It is necessary to separate the lower layer element region and the seed region, and as the number of layers increases, the seed region must be larger due to alignment requirements, and the degree of integration is lower than that of a method without seeds. Small, nine.
素子の領域とシードの領域を分離しても、ビーム・アニ
ール時にはシードの領域は高温になるためシードがない
方法に較べて既に作り九素子への熱の影響は大きい。Even if the element region and the seed region are separated, the seed region reaches a high temperature during beam annealing, so the effect of heat on the already fabricated elements is greater than in a method without a seed.
シードを用いない場合に従来用いられていた方・：じ：
：・
法の断面図を第１図に示す。The method traditionally used when seeds are not used:
:・ A cross-sectional view of the method is shown in Figure 1.
第１図の例では、非晶質絶縁基板として石英ガラス１を
用い、その上に化学気相堆積法（Ｃｈａｎｉｃｓ＋ＩＶ
ａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ法、以下ＣＶＤ法と略
）でポリシリコンを０．６μｍ堆積し、更にその上Ｋ
ＣＶＤ法で酸化シリコン膜（８４０！ＩＩ ） ２を１
８００人堆積しレーザ光３で再結晶化を行ってい友、レ
ーザ光３としてはＣＷ Ｎｄ ： ＹＡＧ （λ＝ Ｉ
ｆ）６４ｍ ）を用いた。８ｉ０゜膜の厚さはλ＝１．
０６μ−の光の透過度が大きくなるように選んだ、シリ
コン層４は一度溶解し、再結晶化すると１μｍ＝１０μ
ｍ程度のグレインに成長するが、グレインの位置に規則
性はなかった。このことは、平坦な非晶質基板を用いた
場合ばかりでなく、非晶質基板にグレーティングを形成
した方法（いわゆる「グラフオエピタキシー」）で４Ｍ
様であった。In the example shown in FIG. 1, a quartz glass 1 is used as the amorphous insulating substrate, and a chemical vapor deposition method (Chanics+IV) is applied thereon.
Polysilicon was deposited to a thickness of 0.6 μm using the apor deposition method (hereinafter abbreviated as CVD method), and then K
Silicon oxide film (840!II) 2 to 1 using CVD method
800 people were deposited and recrystallized with laser beam 3.As laser beam 3, CW Nd: YAG (λ= I
f) 64m) was used. The thickness of the 8i0° film is λ=1.
The silicon layer 4, which was selected so that the light transmittance of 0.6 μm would be large, is once melted and recrystallized to have a diameter of 1 μm = 10 μm.
Although the grains grew to about m, there was no regularity in the position of the grains. This is true not only when a flat amorphous substrate is used, but also when a grating is formed on an amorphous substrate (so-called "graph-o-epitaxy").
It was like that.
従って、素子を十分に作れるサイズの単結晶領域ができ
ているにもかかわらず、単結晶域は適当な位置にでき、
制御できないため実際に素子を作ると結晶粒界が活性領
婢内に含まれてしまう。この１
結果、結晶粒界が活性領域内にどのくらい含まれている
かＫよって素子特性が非常に大きくばらつくという欠点
を有していた。Therefore, even though the single crystal region is large enough to make a device, the single crystal region can be placed at an appropriate position.
Since it cannot be controlled, when an element is actually manufactured, the crystal grain boundaries are included in the active region. As a result, the device characteristics have a drawback that the device characteristics vary greatly depending on how many crystal grain boundaries are included in the active region.
本発明の目的は、従来法が持っていた単結晶領域の位置
の制御ができないという欠点、言いかえれば素子を作っ
ても活性領域に結晶粒界が存在し素子特性を悪化させて
しまうという欠点を改善し。The purpose of the present invention is to overcome the disadvantage of conventional methods in that the position of the single crystal region cannot be controlled; in other words, even if a device is manufactured, crystal grain boundaries exist in the active region, which deteriorates device characteristics. Improve.
所望の位置に制御性良く単結晶領域を形成するための製
造方法を提供するととにある。It is an object of the present invention to provide a manufacturing method for forming a single crystal region at a desired position with good controllability.
本発明は、非晶質絶縁基板上に多結晶又は非結晶質の半
導体膜を形成し、更にその半導体膜の上に絶縁膜を形成
し、半導体膜を単結晶化する位置の絶縁膜を選択エツチ
ングして開口部を設けてビーム・アニールを行うことを
特徴とし、＊記非晶質絶縁膜に設けた開口部より冷却が
生ずる友めＫ。The present invention forms a polycrystalline or amorphous semiconductor film on an amorphous insulating substrate, further forms an insulating film on the semiconductor film, and selects the insulating film at a position where the semiconductor film is made into a single crystal. It is characterized by performing beam annealing after etching an opening to form an amorphous insulating film.
該開口部を核として再結晶化が起こることがら鋏開口部
を中心とした単結晶域ができるという長所を有している
。Since recrystallization occurs using the opening as a nucleus, it has the advantage that a single crystal region is formed around the scissor opening.
以下９本発明について実施例を示す１１１ｍを参照して
ｉｔ１明する。Hereinafter, nine embodiments of the present invention will be explained with reference to section 111m showing examples.
＠２図は２本発明の一実施例を示す断面図で、非晶質絶
縁基板として石英ガラス１１を用い、そＯ上にＣＶＤ法
でポリシリコンを０．６μｍ堆積し、更にその上にＣＶ
Ｄ法で酸化シリコン（８ｉ０．）膜１２を１８００Ａ堆
積しその酸化シリコン膜に２μｍ角の開口部１３を設は
レーザ光１４を照射して再結晶化を行つた。レーザ光１
４としてはＣＷ Ｎｄ ：ＹＡＧ（λ＝１．０６μｍ）
を用いた。酸化シリコン膜１２の厚さはλ＝１．０６μ
ｍの光の透過度が大きくなるように選んだ。シリコン層
１５は一度溶解し、再結晶化の際開口部１３からの熱の
逃げのために開口部付近から固化し横方向に成長が及ぶ
。その結果開口部を中心［１０μｍ程度の大きさのグレ
イン１６が成長し、開口部と開口部の間ＩＣＵ小さなグ
レインの領域１７が存在していた。Figure 2 is a cross-sectional view showing an embodiment of the present invention, in which a quartz glass 11 is used as an amorphous insulating substrate, 0.6 μm of polysilicon is deposited on it by the CVD method, and then a CVD film is further deposited on top of it.
A silicon oxide (8i0.) film 12 was deposited at 1800 Å using the D method, an opening 13 of 2 μm square was formed in the silicon oxide film, and a laser beam 14 was irradiated to perform recrystallization. Laser light 1
4 is CW Nd:YAG (λ=1.06μm)
was used. The thickness of the silicon oxide film 12 is λ=1.06μ
It was selected so that the transmittance of light of m is large. The silicon layer 15 is once melted, and during recrystallization, due to the escape of heat from the opening 13, the silicon layer 15 solidifies from the vicinity of the opening and grows laterally. As a result, grains 16 having a size of about 10 μm were grown around the openings, and a region 17 of small grains existed between the openings.
従って素子を作る領域の中心に開口部を設けておけば、
１０μｍ程度以下の大匙さの素子を１つのグレイン内
に作製することができる。レーザ光で再結晶化した後は
酸化シリコン膜１２を除去し、アイランド化を行うこと
Ｋよ″つて寄生容量の小さい素子を得ることができる。Therefore, if an opening is provided in the center of the area where the element will be made,
Elements as large as about 10 μm or less can be fabricated within one grain. After recrystallization with laser light, the silicon oxide film 12 is removed and an island is formed, thereby making it possible to obtain an element with small parasitic capacitance.
また、素子の活性領域にグレイン・バウンダリが存在し
ないため、４Ｉ性のばらつきが小さい。Furthermore, since there is no grain boundary in the active region of the device, variations in 4I properties are small.
石英ガラスの代〉Ｋ、単結晶シリコン・クエーハの表面
に熱酸化膜を形成したもＯを基板として用いた場合にも
同様の効果が見られえ。A similar effect can be seen when using quartz glass instead of quartz glass or monocrystalline silicon with a thermally oxidized film formed on the surface of the quartz glass as a substrate.
以上のように１本発明はビーム・アエーｋＫより非晶質
絶縁基板上に単結晶半導体膜を形成する場合に、半導体
膜上に絶縁膜を被覆し、その絶縁膜に開口部を設けるこ
とによシ、アニール後の冷却速度即ち、結晶成長核Ｏ位
置制御及び成長方向の制御を行うことを特徴とするもの
で、非晶質絶縁基板上の所望の位置に単結晶域の形成を
可能にし、素子の高速化・三次元化に多大の効果を発揮
する奄のである。As described above, the present invention provides a method for forming an insulating film on the semiconductor film and providing an opening in the insulating film when forming a single crystal semiconductor film on an amorphous insulating substrate using Beam AKK. This method is characterized by controlling the cooling rate after annealing, that is, the position and growth direction of crystal growth nuclei O, and enables the formation of a single crystal region at a desired position on an amorphous insulating substrate. , Amano is highly effective in increasing the speed and making three-dimensional elements.
第１図は従来例を示すもので、ａａ中１は石英ガラス基
板を、２は酸化シリコン膜を、３はレーザ光を、４はシ
リコン層をそれぞれ示している。
−：、：・・
第２図は本発明の一実施例をボすもので９図中１１は石
英ガラス基板を、１２は酸化シリコン膜を、１３は酸化
シリコン膜に設は九−口部を、１４社レーザ光を、１５
はシリコン層を、１６は太きなグレインを、１７は小さ
なグレインの領穢をそれぞれ示している。
第１図
第２図FIG. 1 shows a conventional example, in which 1 in aa indicates a quartz glass substrate, 2 indicates a silicon oxide film, 3 indicates a laser beam, and 4 indicates a silicon layer. -:, :... Figure 2 shows an embodiment of the present invention, in which 11 is a quartz glass substrate, 12 is a silicon oxide film, and 13 is a silicon oxide film. , 14 laser beams, 15
16 indicates a silicon layer, 16 indicates a thick grain, and 17 indicates a small grain area. Figure 1 Figure 2
Claims (1)
し、該半導体膜の上に絶縁膜を形成し。 前記半導体膜の単結晶化を行うべ無位置の該絶縁膜Ｋｔ
ｉ口部を設けてビーム・アニールを行うことを特徴とす
る半導体膜の製造方法。[Claims] A polycrystalline or amorphous O semiconductor film is formed on an amorphous bonded substrate, and an insulating film is formed on the semiconductor film. The insulating film Kt has no position where the semiconductor film should be single crystallized.
A method for manufacturing a semiconductor film, characterized in that beam annealing is performed with an i-portion provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57068467A JPS58184720A (en) | 1982-04-23 | 1982-04-23 | Manufacture of semiconductor film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57068467A JPS58184720A (en) | 1982-04-23 | 1982-04-23 | Manufacture of semiconductor film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58184720A true JPS58184720A (en) | 1983-10-28 |
Family
ID=13374516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57068467A Pending JPS58184720A (en) | 1982-04-23 | 1982-04-23 | Manufacture of semiconductor film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58184720A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60249312A (en) * | 1984-05-24 | 1985-12-10 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6130023A (en) * | 1984-07-21 | 1986-02-12 | Agency Of Ind Science & Technol | Formation of soi |
| JPS6130024A (en) * | 1984-07-21 | 1986-02-12 | Agency Of Ind Science & Technol | Formation of soi |
| JPS6189621A (en) * | 1984-10-09 | 1986-05-07 | Fujitsu Ltd | Manufacture of semiconductor device |
| JP2004207691A (en) * | 2002-12-11 | 2004-07-22 | Sharp Corp | Semiconductor thin film manufacturing method and apparatus, semiconductor thin film manufactured by method, and semiconductor element using thin film |
-
1982
- 1982-04-23 JP JP57068467A patent/JPS58184720A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60249312A (en) * | 1984-05-24 | 1985-12-10 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6130023A (en) * | 1984-07-21 | 1986-02-12 | Agency Of Ind Science & Technol | Formation of soi |
| JPS6130024A (en) * | 1984-07-21 | 1986-02-12 | Agency Of Ind Science & Technol | Formation of soi |
| JPS6189621A (en) * | 1984-10-09 | 1986-05-07 | Fujitsu Ltd | Manufacture of semiconductor device |
| JP2004207691A (en) * | 2002-12-11 | 2004-07-22 | Sharp Corp | Semiconductor thin film manufacturing method and apparatus, semiconductor thin film manufactured by method, and semiconductor element using thin film |
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