JPH0223027B2 - - Google Patents
Info
- Publication number
- JPH0223027B2 JPH0223027B2 JP56209767A JP20976781A JPH0223027B2 JP H0223027 B2 JPH0223027 B2 JP H0223027B2 JP 56209767 A JP56209767 A JP 56209767A JP 20976781 A JP20976781 A JP 20976781A JP H0223027 B2 JPH0223027 B2 JP H0223027B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- recess
- film
- oxide film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052710 silicon Inorganic materials 0.000 claims description 36
- 239000010703 silicon Substances 0.000 claims description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 32
- 239000013078 crystal Substances 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 2
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 239000010408 film Substances 0.000 description 60
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 239000005360 phosphosilicate glass Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000012768 molten material Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は半導体装置、より詳しく述べるなら
ば、レーザ照射によつて多結晶シリコンから単結
晶シリコンに絶縁膜上にて変えられかつ誘電体分
離されている複数の半導体装置形成領域を有する
基板の製造方法に関するものである。[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a semiconductor device, and more specifically, the present invention relates to a semiconductor device, and more specifically, a semiconductor device that is capable of converting polycrystalline silicon to single crystal silicon on an insulating film by laser irradiation, and The present invention relates to a method of manufacturing a substrate having a plurality of semiconductor device forming regions.
(2) 技術の背景
レーザ照射によつて非品質又は多結晶の薄膜を
単結晶膜に変え、半導体装置の製造に利用するこ
とが研究開発されている（例えば、徳山、夏秋、
宮尾：研究が急速に広がるレーザー・アニール技
術、日経エレクトロニクス、1979年６月11日号、
第116頁〜第151頁、および林 裕久：新しいLSI
を実現する非晶質絶縁膜上の単結晶成長法、日経
エレクトロニクス、1980年２月18日号、第82頁〜
第90頁参照）。(2) Background of the technology Research and development is underway to convert non-quality or polycrystalline thin films into single-crystalline films by laser irradiation and use them for manufacturing semiconductor devices (for example, Tokuyama, Natsuaki,
Miyao: Laser annealing technology whose research is rapidly expanding, Nikkei Electronics, June 11, 1979 issue,
Pages 116 to 151, and Hirohisa Hayashi: New LSI
Single-crystal growth method on amorphous insulating film to achieve this, Nikkei Electronics, February 18, 1980 issue, p.82
(See page 90).
(3) 従来技術と問題点
本出願人は、特願昭55−98397号（特開昭57−
23217号公報）および特願昭56−155512号（特開
昭58−56411号公報）にて、レーザ照射によつて
絶縁体の凹所内に単結晶領域を非結晶材料から形
成する半導体装置用基板の製造方法を提案した。(3) Prior art and problems The present applicant has filed Japanese Patent Application No. 55-98397
No. 23217) and Japanese Patent Application No. 56-155512 (Japanese Unexamined Patent Publication No. 58-56411) disclose a semiconductor device substrate in which a single crystal region is formed from an amorphous material in a recess of an insulator by laser irradiation. proposed a manufacturing method.
特願昭56−15512号にて提案した製造方法は次
のようなものであつた。 The manufacturing method proposed in Japanese Patent Application No. 56-15512 was as follows.
第１図に示したように、台板１（金属、アルミ
ナ、高純度石英等の板）の上に絶縁層（二酸化シ
リコン）の基板２を形成し、フオトリソグラフイ
技術によつてこの基板２を選択エツチングして凹
所３を形成する。次に、多結晶シリコン膜４を全
面に形成し、必須ではないが燐硅酸ガラス
（PSG）層５をその上に形成する。例えば、基板
２の厚さl1は1μｍであり、凹所のサイズは30×
50μｍであり、凹所底部の基板２の厚さl2は0.1μ
ｍであり、凹所間の幅l5は5μｍであり、多結晶シ
リコン膜４の厚さl4は0.5〜1μｍであり、および
燐硅酸ガラス層５の厚さは1μｍである。 As shown in FIG. 1, a substrate 2 of an insulating layer (silicon dioxide) is formed on a base plate 1 (a plate made of metal, alumina, high-purity quartz, etc.), and this substrate 2 is formed using photolithography technology. A recess 3 is formed by selectively etching. Next, a polycrystalline silicon film 4 is formed over the entire surface, and a phosphosilicate glass (PSG) layer 5 is formed thereon, although this is not essential. For example, the thickness l 1 of the substrate 2 is 1 μm, and the size of the recess is 30×
50 μm, and the thickness l 2 of the substrate 2 at the bottom of the recess is 0.1 μm.
m, the width l 5 between the recesses is 5 μm, the thickness l 4 of the polycrystalline silicon film 4 is 0.5-1 μm, and the thickness of the phosphosilicate glass layer 5 is 1 μm.
第１図の状態で全体を500℃程度に加熱しなが
ら、連続発振（CW）レーザを走査させて照射し
て多結晶シリコン膜４を溶融し、溶融体が凹所３
内に溜まる。照射スポツトの移動による照射の終
了後に溶融体が凹所内で凝固して単結晶化する。
なお、必ず単結晶となるとは限らず粒径の大きな
結晶となることがあるが、本明細書中ではこのよ
うな場合も単結晶としている。結晶粒径がトラン
ジスタ作成に必要なサイズよりも大きければ良い
わけである。そして、燐硅酸ガラス層５を除去す
ると第２図に示した半導体装置用基板が得られ、
シリコン単結晶領域６Ａ，６Ｂ，６Ｃ内に通常の
技法にて半導体装置（バイポーラトランジスタ、
MOS FET等）が作られる。 While heating the entire body to about 500°C in the state shown in Figure 1, a continuous wave (CW) laser is scanned and irradiated to melt the polycrystalline silicon film 4, and the molten material is transferred to the recess 3.
Accumulates inside. After the irradiation is completed due to the movement of the irradiation spot, the melt solidifies in the recess and becomes a single crystal.
It should be noted that although the crystal does not necessarily become a single crystal and may have a large grain size, in this specification, such a case is also referred to as a single crystal. It is sufficient that the crystal grain size is larger than the size required for making a transistor. Then, by removing the phosphosilicate glass layer 5, the semiconductor device substrate shown in FIG. 2 is obtained,
Semiconductor devices (bipolar transistors,
MOS FET, etc.) are made.
しかしながら、このようにして製造される半導
体装置用基板において、誘電体分離（アイソレー
シヨン）層となつている絶縁層基板２の表面上に
単結晶化した薄いシリコン膜が残つてしまう場合
がある。すなわち、レーザ照射の際に溶融したシ
リコンが凹所内に完全に流れないで絶縁層基板２
の上に残るのが原因である。この残つた薄いシリ
コン膜が凹所内の単結晶領域相互を結ぶことにな
つて誘電体分離が完全でなくなるので除去する
か、あるいは酸化して酸化膜を変えて導電性をな
くすかしなければならない。 However, in the semiconductor device substrate manufactured in this way, a thin monocrystalline silicon film may remain on the surface of the insulating layer substrate 2, which serves as a dielectric isolation layer. . In other words, the silicon melted during laser irradiation does not completely flow into the recess and the insulating layer substrate 2
This is because it remains on top of the . This remaining thin silicon film connects the single crystal regions within the recess, and the dielectric isolation is no longer complete, so it must be removed or oxidized to change the oxide film to eliminate conductivity. .
(4) 発明の目的
本発明の目的は、上述した凹所を有する絶縁層
基板上に残つた薄いシリコン膜を除去して誘電体
分離が確実に行なわれる半導体装置用基板を製造
する方法を提案することである。(4) Purpose of the Invention The purpose of the present invention is to propose a method for manufacturing a substrate for a semiconductor device in which the thin silicon film remaining on the insulating layer substrate having the above-mentioned recesses is removed to ensure dielectric separation. It is to be.
(5) 発明の構成
上述の目的が、シリコン基板上に、厚い酸化膜
部分と薄い酸化膜部分とからなり、かつ該薄い酸
化膜部分が凹所となつている第１の酸化膜を形成
する工程と、該第１の酸化膜の該凹所内を埋める
のに見合つた量とした非単結晶シリコン膜（多結
晶又は非晶質シリコン膜）を全表面上に形成する
工程と、該非単結晶シリコン膜にレーザを照射し
て溶融し、前記厚い酸化膜部分上にある部分の溶
融シリコンが一部残つて該凹所内へ流動し、照射
後に該凹所内にシリコン単結晶領域を形成する工
程と、前記厚い酸化膜部分上に残つたシリコン膜
を全て熱酸化すると同時に前記凹所内のシリコン
単結晶領域の表面をも熱酸化して、第２の酸化膜
を形成する工程と、該第２の酸化膜をエツチング
除去して、前記シリコン単結晶領域の表面を露出
させる工程と、を有することを特徴とする半導体
装置用基板の製造方法によつて達成される。(5) Structure of the invention The above-mentioned object is to form a first oxide film on a silicon substrate, which is composed of a thick oxide film portion and a thin oxide film portion, and the thin oxide film portion is a recess. a step of forming a non-single crystal silicon film (polycrystalline or amorphous silicon film) on the entire surface of the first oxide film in an amount suitable for filling the recess; irradiating the silicon film with a laser to melt it, a portion of the molten silicon on the thick oxide film portion remaining and flowing into the recess, and forming a silicon single crystal region within the recess after irradiation; , a step of thermally oxidizing all the silicon film remaining on the thick oxide film portion and simultaneously thermally oxidizing the surface of the silicon single crystal region in the recess to form a second oxide film; This is achieved by a method of manufacturing a substrate for a semiconductor device, which comprises the step of etching away the oxide film to expose the surface of the silicon single crystal region.
(6) 発明の実施態様
添付図面を参照して本発明の好ましい実施態様
例によつて本発明を説明する。(6) Embodiments of the invention The present invention will be described by way of preferred embodiments of the invention with reference to the accompanying drawings.
第３図ないし第１０図は本発明に係る半導体装
置用基板の製造方法の各工程を説明するための基
板の概略図および斜視図である。 3 to 10 are a schematic diagram and a perspective view of a substrate for explaining each step of the method for manufacturing a semiconductor device substrate according to the present invention.
第３図に示すように単結晶又は多結晶のシリコ
ンサブストレート１１の上に二酸化シリコン（又
は窒化シリコン）の絶縁膜１２を形成する。絶縁
膜１２の厚さは、例えば、1μｍとし、二酸化シ
リコン膜であればシリコンサブストレート１１の
熱酸化によつてあるいは化学的気相成法（CVD
法）によつて形成することができ、窒化シリコン
膜であればCVD法によつて形成する。 As shown in FIG. 3, an insulating film 12 of silicon dioxide (or silicon nitride) is formed on a single-crystal or polycrystalline silicon substrate 11. The thickness of the insulating film 12 is, for example, 1 μm, and if it is a silicon dioxide film, it is formed by thermal oxidation of the silicon substrate 11 or by chemical vapor deposition (CVD).
If it is a silicon nitride film, it can be formed by a CVD method.
次に、通常のホトエツチング法によつて絶縁膜
１２を選択的にエツチングして窓１３を開け、シ
リコンサブストレート１１の一部を露出させる
（第４図）。 Next, the insulating film 12 is selectively etched using a conventional photoetching method to open a window 13 and expose a portion of the silicon substrate 11 (FIG. 4).
この絶縁膜１２を有するシリコンサブストレー
ト１１を熱酸化又は熱窒化処理等をして、露出部
の表面に薄い絶縁膜１４を形成する（第５図）。
又は、第３図の状態により絶縁膜１２をコントロ
ールエツチングして薄い絶縁膜１４を残し、第５
図の構造を得ても良い。このときの状態の斜視図
が第６図であつて、多数の凹所１３が絶縁膜１２
に形成されているわけであり、凹所１３の寸法
は、例えば20μｍ×20μｍである。そして、薄い
絶縁膜１４の厚さは、例えば、0.1μｍである。 The silicon substrate 11 having the insulating film 12 is subjected to thermal oxidation or thermal nitriding treatment, etc., to form a thin insulating film 14 on the exposed surface (FIG. 5).
Alternatively, the insulating film 12 may be controlled etched to leave the thin insulating film 14 under the conditions shown in FIG.
The structure of the diagram may also be obtained. A perspective view of the state at this time is shown in FIG.
The dimensions of the recess 13 are, for example, 20 μm×20 μm. The thickness of the thin insulating film 14 is, for example, 0.1 μm.
次に、多結晶（場合によつては非晶質）シリコ
ン膜１５をCVD法によつて全表面上に形成する
（第７図）。この多結晶シリコン膜１５の厚さは、
例えば、0.4μｍである。このシリコン膜１５の上
に燐硅酸ガラス膜（例えば、厚さ1μｍ）をCVD
法によつて形成しても良い（図示せず）。このガ
ラス膜は熱放散を抑止する働きがあり、存在する
ことによつてない場合よりも上述した問題点であ
る絶縁膜上でのシリコン膜の残存が少ないという
利点がある。 Next, a polycrystalline (or amorphous in some cases) silicon film 15 is formed over the entire surface by CVD (FIG. 7). The thickness of this polycrystalline silicon film 15 is
For example, it is 0.4 μm. A phosphosilicate glass film (for example, 1 μm thick) is deposited on this silicon film 15 by CVD.
It may also be formed by a method (not shown). This glass film has the function of suppressing heat dissipation, and its presence has the advantage that less silicon film remains on the insulating film, which is the problem mentioned above, than if it were not present.
得られたシリコンサブストレート１１を、例え
ば、500℃程度に加熱保持しているときに、レー
ザを走査照射して多結晶シリコン膜１５を溶融す
る。この照射は、例えば、連続発振（CW）のア
ルゴン・レーザで、パワー12W、走査速度10cm／
秒、スポツトサイズ50μｍ径の条件で行なう。溶
融したシリコンは凹所１３内へ流れ、照射が移動
したところで凹所１３内で凝固し単結晶化する。
したがつて、シリコン単結晶領域１６Ａ１６Ｂお
よび１６Ｃ（第８図）が凹所内に形成されるが、
溶融シリコンの一部が凹所内へ流れずに絶縁膜１
２の上に残つて単結晶した薄いシリコン膜１７
（第８図）となることがある。残つたとしても、
薄いシリコン膜１７は通常0.1μｍ以下の厚さであ
る。この薄いシリコン膜１７のために単結晶領域
１６Ａ，１６Ｂ，１６Ｃ間相互の分離（アイソレ
ーシヨン）が不十分となつてしまう。燐硅酸ガラ
ス膜を形成していたならば、レーザ照射完了後に
エツチング除去する。なお、このように本発明の
製造方法では、後に素子領域とすべきために形成
されるシリコン単結晶領域は、非単結晶シリコン
膜を一旦レーザで溶融した後、冷却とともに再結
晶化してできるものであるが、一般的にこの冷却
の進み方如何によつては、単結晶化がうまく進行
しない場合が少なくない。基板内に凹所を形成
し、その表面に一様な厚さの絶縁膜を形成したの
では、シリコン溶融の後に熱が均等に分散してし
まい、特にこの凹所の底部では単結晶化が進みに
くい。本発明の製造方法では、単結晶領域が形成
される凹所を囲む絶縁膜は、この凹所の底部に比
べて側面が特に厚く形成されてなるものであるか
ら、上記したような熱の均一な分散とはならず
に、薄い酸化膜部分の底部から冷却がすすみ、凹
所内の単結晶がよりよく行えるものである。 While the obtained silicon substrate 11 is heated and maintained at, for example, about 500° C., a laser is scanned and irradiated to melt the polycrystalline silicon film 15. This irradiation is performed using, for example, a continuous wave (CW) argon laser with a power of 12W and a scanning speed of 10cm/
The spot size was 50 μm in diameter. The molten silicon flows into the recess 13 and solidifies within the recess 13 as the irradiation moves to form a single crystal.
Therefore, silicon single crystal regions 16A, 16B and 16C (FIG. 8) are formed within the recess;
Part of the molten silicon does not flow into the recess and the insulating film 1
A thin monocrystalline silicon film 17 remaining on 2
(Figure 8) may occur. Even if it remains,
The thin silicon film 17 usually has a thickness of 0.1 μm or less. This thin silicon film 17 results in insufficient isolation between single crystal regions 16A, 16B, and 16C. If a phosphosilicate glass film is formed, it is removed by etching after laser irradiation is completed. In this way, in the manufacturing method of the present invention, the silicon single crystal region that is to be formed later as an element region is formed by melting a non-single crystal silicon film with a laser and then recrystallizing it while cooling. However, depending on how this cooling progresses, single crystallization often does not proceed well. If a recess is formed in the substrate and an insulating film of uniform thickness is formed on the surface of the recess, the heat will be distributed evenly after silicon melts, and single crystallization will occur, especially at the bottom of the recess. Difficult to advance. In the manufacturing method of the present invention, the insulating film surrounding the recess where the single crystal region is formed is formed to be particularly thick on the side surfaces compared to the bottom of the recess, so that the above-mentioned uniform heat distribution is achieved. Cooling proceeds from the bottom of the thin oxide film portion without causing severe dispersion, and the single crystal in the recess can be formed better.
熱酸化処理を施すことによつて薄いシリコン膜
１７を完全に酸化して二酸化シリコン膜とする。
このとき、単結晶領域１６Ａ，１６Ｂ，１６Ｃの
表面も同時に酸化されて二酸化シリコン膜１８と
なる。（第９図）
そして、この二酸化シリコン膜１８をエツチン
グ除去することによつて、第１０図に示す半導体
装置用基板が得られる。単結晶領域１６Ａ，１６
Ｂ，１６Ｃはその底面が薄い絶縁膜１４によつ
て、また、側面が絶縁膜１２によつて囲まれてお
り、このようにして完全な誘電体分離が達成され
る。これら単結晶領域１６Ａ，１６Ｂ，１６Ｃ内
の所定のトランジスタ、抵抗などが公知の工程で
作られる。 By performing thermal oxidation treatment, the thin silicon film 17 is completely oxidized to form a silicon dioxide film.
At this time, the surfaces of single crystal regions 16A, 16B, and 16C are also oxidized to form silicon dioxide film 18. (FIG. 9) Then, by etching and removing this silicon dioxide film 18, a semiconductor device substrate shown in FIG. 10 is obtained. Single crystal regions 16A, 16
B, 16C is surrounded by a thin insulating film 14 on its bottom and by an insulating film 12 on its side, thus achieving complete dielectric isolation. Predetermined transistors, resistors, etc. in these single crystal regions 16A, 16B, and 16C are manufactured by known processes.
(7) 発明の効果
本発明に係る半導体装置用基板の製造方法に従
つて製作した基板では、トランジスタ等の半導体
装置を作り込むシリコン単結晶領域が完全に誘電
体分離されている。そして、SOS（silicon on
sapphire）構造に似ている構造が得られるので、
SOS半導体素子に近い動作速度の速くかつ低消費
電力の半導体素子を得ることができ、しかもサフ
アイヤ基板を使用していないのでSOS半導体素子
よりも低コストである。(7) Effects of the Invention In a substrate manufactured according to the method for manufacturing a semiconductor device substrate according to the present invention, a silicon single crystal region in which a semiconductor device such as a transistor is formed is completely dielectrically isolated. And SOS (silicon on
A structure similar to the sapphire structure is obtained, so
It is possible to obtain a semiconductor element with a high operating speed close to that of an SOS semiconductor element and low power consumption, and since a sapphire substrate is not used, the cost is lower than that of an SOS semiconductor element.
第１図および第２図は半導体装置用基板の従来
の製造工程を説明するためのこの基板の概略部分
断面図であり、第３図ないし第５図および第７図
ないし第１０図は本発明に係る製造工程を説明す
るための半導体装置用基板の概略部分断面図であ
り、第６図は、第５図のときの半導体装置用基板
の部分斜視図である。
１１……シリコンサブストレート、１２……絶
縁層、１３……凹所、１４……薄い絶縁膜、１５
……多結晶シリコン膜、１６Ａ，１６Ｂ，１６Ｃ
……シリコン単結晶領域、１７……薄いシリコン
膜、１８……二酸化シリコン膜。
1 and 2 are schematic partial sectional views of a substrate for explaining the conventional manufacturing process of a substrate for a semiconductor device, and FIGS. FIG. 6 is a partial perspective view of the semiconductor device substrate in FIG. 5. FIG. 11...Silicon substrate, 12...Insulating layer, 13...Recess, 14...Thin insulating film, 15
...Polycrystalline silicon film, 16A, 16B, 16C
...Silicon single crystal region, 17...Thin silicon film, 18...Silicon dioxide film.
Claims (1)
化膜部分とからなり、かつ該薄い酸化膜部分が凹
所となつている第１の酸化膜を形成する工程と、 該第１の酸化膜の該凹所内を埋めるのに見合つ
た量とした非単結晶シリコン膜を全表面上に形成
する工程と、 該非単結晶シリコン膜にレーザを照射して溶融
し、前記厚い酸化膜部分上にある部分の溶融シリ
コンが一部残つて該凹所内へ流動し、照射後に該
凹所内にシリコン単結晶領域を形成する工程と、 前記厚い酸化膜部分上に残つたシリコン膜を全
て熱酸化すると同時に前記凹所内のシリコン単結
晶領域の表面をも熱酸化して、第２の酸化膜を形
成する工程と、 該第２の酸化膜をエツチング除去して、前記シ
リコン単結晶領域の表面を露出させる工程と、 を有することを特徴とする半導体装置用基板の製
造方法。[Claims] 1. A step of forming a first oxide film on a silicon substrate, the first oxide film consisting of a thick oxide film portion and a thin oxide film portion, the thin oxide film portion being a recess; forming a non-single-crystal silicon film on the entire surface of the first oxide film in an amount suitable for filling the recess; and melting the non-single-crystal silicon film by irradiating the non-single-crystal silicon film with a laser to melt the thick oxide film. A part of the molten silicon on the film portion remains and flows into the recess to form a silicon single crystal region in the recess after irradiation, and all of the silicon film remaining on the thick oxide film portion is removed. At the same time as the thermal oxidation, the surface of the silicon single crystal region in the recess is also thermally oxidized to form a second oxide film, and the second oxide film is removed by etching to remove the silicon single crystal region. 1. A method of manufacturing a substrate for a semiconductor device, comprising: a step of exposing a surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20976781A JPS58114440A (en) | 1981-12-28 | 1981-12-28 | Manufacture of substrate for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20976781A JPS58114440A (en) | 1981-12-28 | 1981-12-28 | Manufacture of substrate for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58114440A JPS58114440A (en) | 1983-07-07 |
| JPH0223027B2 true JPH0223027B2 (en) | 1990-05-22 |
Family
ID=16578276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20976781A Granted JPS58114440A (en) | 1981-12-28 | 1981-12-28 | Manufacture of substrate for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58114440A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61125169A (en) * | 1984-11-22 | 1986-06-12 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
| JP2007142167A (en) * | 2005-11-18 | 2007-06-07 | Hitachi Displays Ltd | Display device and its manufacturing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5658269A (en) * | 1979-10-17 | 1981-05-21 | Seiko Epson Corp | Mos type semiconductor device |
-
1981
- 1981-12-28 JP JP20976781A patent/JPS58114440A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5658269A (en) * | 1979-10-17 | 1981-05-21 | Seiko Epson Corp | Mos type semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58114440A (en) | 1983-07-07 |
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