JPH01168050A - Laminated type semiconductor device - Google Patents

Abstract

PURPOSE:To preferably laterally epitaxially grow even in a recrystallization of third layer or higher, and to enhance the quality by reducing the area of an opening to a specific area or less, and isolating the openings of upper and lower layers at a specific distance or more. CONSTITUTION:The area of an opening is formed 9mum<2> or less, and the position of the opening of an upper layer is isolated 8mum or more with respect to the position of the opening of a lower layer. An opening 51 for aligning a third layer silicon film with the same crystal axis as that of a substrate single crystalline silicon 1 is formed in a square shape having 3mum of one side, and the position of the opening 51 is disposed at a position isolated by 8mum or more with respect to an opening 5 for a second layer. Thus, a polycrystalline silicon 62 in the opening 51 is completely melted at the time of irradiating a laser beam, a lateral epitaxial growth occurs with a single crystalline silicon 73 as a seed thereby to perform a preferably epitaxial growth, thereby enhancing its quality.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a stacked semiconductor device in which semiconductor elements are stacked three-dimensionally in multiple layers.

[Conventional technology]

In order to realize higher density and multi-functionality of semiconductor devices, attempts have been made to manufacture stacked semiconductor devices, so-called three-dimensional circuit elements, in which circuit elements are stacked three-dimensionally in multiple layers. By forming an insulator on top of the insulator and irradiating the non-single crystal semiconductor layer deposited on the insulator with energy rays such as laser light,
Heating only the semiconductor layer? There is a method in which the semiconductor layer is melted to form a single crystal, circuit elements are formed on the single crystal semiconductor layer, and the semiconductor layer is laminated.

FIG. 2 (al~(a) is a cross-sectional view showing each step of a conventional method for manufacturing a stacked semiconductor device.

Figure 2 (in al, 1 is a single crystal silicon substrate, A is a normal MOS) is the first layer MO3I-transistor produced by the transistor manufacturing process, 21 is an oxide film, 3 is a gate electrode, 4 is a This is the source/drain wiring. The source/drain wiring 4 is made of high-melting point metal silicide such as tungsten silicide (WSi) so that it can withstand high-temperature heat treatment for later lamination. After forming the first layer of circuit elements, an oxide film 22 is deposited as an interlayer insulating film by chemical vapor deposition (hereinafter referred to as CVD), and the surface is planarized by resist coating and etchback. In order to form a conflict crystalline silicon layer having the same crystal axis as the substrate single crystal silicon 1 on this oxide film 22, a square opening 5 with a side of 3 μm reaching the substrate silicon 1 is formed in a part of the oxide film 22. Form.

Thereafter, as shown in FIG. 2 (IJ), the C
Polycrystalline silicon 6 is buried by the VD method and etchback method, and polycrystalline silicon 7 with a thickness of 0.5 μm is formed thereon by the CVD method. Thereafter, this polycrystalline silicon 7 is irradiated with an argon laser beam 8 having a beam diameter of 100 μm while scanning in the direction of the arrow in the figure at a scanning speed of 25 ell/s. Polycrystalline silicon 7 becomes molten silicon 72 by irradiation with laser light 8, and solidifies and recrystallizes when the irradiation ends.

When this molten silicon 72 solidifies, lateral epitaxial growth occurs using the substrate single crystal silicon 1 and the molten polycrystalline silicon 6 as seeds, and the polycrystalline silicon 7 on the oxide film 22 becomes the substrate single crystal silicon 1. Single crystal silicon 71 having the same crystal axis is formed (Fig. 2 (C1)). The formation mechanism of the single crystal semiconductor layer on the oxide film by this laser beam irradiation is described in Japanese Patent Publication No. 61-047192.61-
48470.61-118438゜61-048468
is described in detail.

Next, as shown in FIG. 2(d), the monocrystalline polycrystalline silicon 71 is made into MO by photolithography and etching techniques.
Single crystal silicon 74 in the region where the S transistor is to be manufactured
Then, the single crystal silicon 73 above the opening 5 is patterned. Thereafter, a second layer MOS transistor B is fabricated on this single crystal silicon 74 by the same method as the I layer MOS transistor A (FIG. 2(e)).

In FIG. 2<8), 23 is an oxide film, 31 is a gate electrode, and 41 is a source/drain wiring. The source/drain wiring 41 is made of refractory metal silicide, like the source/drain wiring 4 of the first layer transistor A.

Next, as shown in FIG. 2(f), after forming the second layer of circuit element B, an interlayer insulating film (oxide film) 24 is deposited by CVD method, and the surface is planarized by resist coating and etchback method. do. After that, an opening is formed on the single crystal silicon 73, polycrystalline silicon is buried in the opening as in the case of the first layer, polycrystalline silicon is deposited thereon by CVD method, and then laser light is applied. By irradiation, these polycrystalline silicons are converted into monocrystalline silicon 61.75. Thereafter, as shown in FIG. 2(g), a third layer MOS transistor C is fabricated on the single crystal silicon 75 in the same manner as in the case of the I-th layer and the second layer.

In the manner described above, a three-dimensional circuit element having a three-layer structure is manufactured.

[Problem that the invention seeks to solve]

In the conventional stacked semiconductor device, the opening for converting the polycrystalline silicon into single crystal silicon 75 having the same crystal axis as the substrate single crystal silicon 1 for the 3Mth circuit element C is
It is provided directly above the opening 5 for the second layer circuit element B. In such a case, silicon has a higher thermal conductivity than an oxide film, so the polycrystalline silicon within the opening will not melt due to a small temperature rise, resulting in the problem that lateral epitaxial growth will not occur. Ta.

Furthermore, this phenomenon becomes more pronounced as the interlayer insulating film becomes thicker, and it was impossible to melt the polycrystalline silicon within the opening during recrystallization of the third layer.

In order to solve this problem, attempts have been made to keep the heat conduction low by making the opening smaller, but in order to melt the polycrystalline silicon inside the opening, the opening size is 0.
．． It must be less than 5 μm, leaving problems with the reliability of the process for forming the opening.

This invention was made to solve the above-mentioned problems, and its purpose is to obtain a stacked semiconductor device in which good lateral epitaxial growth is possible and each layer has a semiconductor layer having the same crystal axis as the substrate. shall be.

[Means for solving problems]

In the stacked semiconductor device according to the present invention, the area of the opening is 9
The openings in the upper layer are separated by 8 μm or more from the openings in the lower layer.

[Effect]

In this invention, by providing the opening in the upper layer at least 8 μm apart from the opening in the lower layer, heat dissipation during recrystallization is prevented and good lateral epitaxial growth is possible.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In the description of this embodiment, the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.

FIG. 1 is a cross-sectional view for explaining a stacked semiconductor device according to an embodiment of the present invention. In this figure, reference numeral 1 denotes a single crystal silicon substrate, which has a (100) plane or a principal plane close to this plane. 22 and 24 are interlayer oxide films, and 51 is a square opening with a side of 3 μm for making the 3JIIth silicon film have the same crystal axis as the single crystal silicon substrate 1.

61. 73 is monocrystalline silicon, 62 is polycrystalline silicon embedded in the opening 51, 76 is polycrystalline silicon, A
is a first layer transistor, and B is a second layer transistor. FIG. 1 corresponds to the step before laser beam irradiation in FIG. 2(f). Further, in FIG. 1, the position of the opening 51 for the third layer is 8 μm apart from the opening 5 for the second layer.

Now, FIG. 3 shows simulation results when polycrystalline silicon 76 is irradiated with laser light when the openings 5 and 51 are separated from each other. Figure 3(b) is the same as Figure 3(b).
As shown in a), the opening diameter is 2 μm.

The thickness of the interlayer oxide film is 4 μm (2 μm per IJi).

The thickness of the second semiconductor layer (monocrystalline silicon 73) and the third semiconductor layer (polycrystalline silicon 76) is 0, respectively.
．． This figure shows the relationship between the distance X between openings during laser beam irradiation and the melting depth Y of polycrystalline silicon 62 from above the interlayer oxide film when the distance is 5 μm. From FIG. 3, it can be seen that when the distance X between the openings exceeds 8 μm, the melting depth Y becomes 2 μm or more. Since the single crystal silicon 73 is located at a distance of 2 μm from the upper end of the interlayer oxide film, epitaxial growth in the lateral direction occurs when the distance between the openings is 8 μm or more and the melting depth Y is 2 μm or more.

From the above results, in FIG. 1, since the opening 51 is 8 μm RL with respect to the opening 5 in the lower layer, the polycrystalline silicon 62 inside the opening 51 is completely melted during laser beam irradiation, and the single crystal silicon Lateral epitaxial growth occurs using 73 as a seed, and the polycrystalline silicon 62 and 76 become single crystal silicon having the same crystal axis as the substrate single crystal silicon 1. After that, a third layer transistor is formed in the single crystal polycrystalline silicon 76 using the method described in the conventional example.

In the above embodiment, an example of a stacked semiconductor device having a three-layer structure was shown, but the present invention can produce the same effect regardless of the number of layers as long as there are three or more layers.

In addition, the elements fabricated in each layer are also MO
The present invention is not limited to type 3 transistors, and the shape of the opening is not limited to square.

〔Effect of the invention〕

As described above, according to the present invention, the area of the opening can be reduced to 9μ.
m'' or less, and the openings in the upper and lower layers are separated by 8 μm or more, making it possible to achieve good lateral epitaxial growth even in recrystallization of the third or higher layers, resulting in high-quality stacked semiconductor devices. There are benefits to be gained.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a stacked semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a conventional stacked semiconductor device by process, and FIG. 3 is a cross-sectional view showing the distance between openings and the melting depth. It is a figure for explaining the simulation result of a relationship. 1 is the substrate single crystal silicon, 22.24 is the interlayer oxide film, 5
．． 51 is an opening, 61.73 is single crystal silicon, 62
．． 76 is polycrystalline silicon, A is the first layer transistor, B
is the second layer transistor, and C is the third layer transistor. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: Director of the Agency of Industrial Science and Technology Kozo Iizuka 1 Figure 3: Goo〆2fj 4: AIIJ! A 3/Kuku! 〃 22.24: 41 to ship ノ23: Jilt ~ 1 5.51: DaDfi5 61.73 device 4h fear Jn 62.76: -9J Meb ngfun A: i, ## Menonshi 2ri B :24E〆Rinnn7ri02Figure 2

Claims (2)

[Claims] (1) Semiconductor elements are stacked three-dimensionally through an interlayer insulating film for electrically separating the upper and lower layers, and a semiconductor is buried in an opening provided in the interlayer insulating film, and the interlayer insulating film is In a stacked semiconductor device in which a semiconductor single crystal layer having the same crystal axis as the substrate semiconductor single crystal is formed on a film, and a second or higher layer of semiconductor elements is formed on the single crystal layer, the opening is Its area is 9 μm^2 or less, and
A stacked semiconductor device characterized in that an opening for forming an element in a third or higher layer is connected to an opening in a layer immediately below at a distance of 8 μm or more. (2) The stacked semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon having a (100) plane or a main surface close to this plane.