JPS6229910B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a multilayered MOS transistor structure.

As a single layer n-channel MOS transistor, the one shown in FIG. 1 is generally known.
In the figure, 1 is a semiconductor substrate made of p-type silicon, 2a and 2b are n ⁺ sources and n ⁺ drains formed on this semiconductor substrate, 3 is a gate made of polycrystalline silicon, 4 is a gate oxide film, and 5 is a semiconductor A field insulating layer is a silicon oxide film formed on the substrate, and 6 is phosphosilicate glass (PSG) formed on the surface of this field silicon oxide film.
Films 7a and 7b are electrode metals connected to the n ⁺ source 2a and n ⁺ drain 2b, respectively, and 8 is a silicon nitride film.

Single-layer n-channel MOS configured in this way
In order to further increase the degree of integration of transistors, the inventors conducted various studies and found that the degree of integration could be increased by creating a semiconductor device with a multilayered MOS transistor structure as described below.

That is, two single-crystal semiconductor layers connected to a semiconductor substrate through a field insulating layer of a single-layer MOS transistor structure are used as a drain and a source, and at least a second single-crystal layer is connected between the drain and the source. The above semiconductor substrate
It is characterized in that it is formed on the top layer of the MOS transistor structure to form a second MOS transistor structure.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device having a multilayered MOS transistor structure, which is an embodiment of the present invention, will be explained below according to the manufacturing process with reference to the drawings.

First, after manufacturing a conventional single-layer n-channel MOS transistor structure A as shown in FIG. 1, as shown in FIG. After depositing a silicon oxide SiO ₂ layer 9 that will become a field insulating layer and a gate oxide film constituting the transistor structure, this silicon oxide layer 9 is removed by photolithography.
Two holes 10a and 10b penetrate the field insulating layer 5 of the first MOS transistor structure A from the top surface and reach the semiconductor substrate, and a shallow hole 10 is formed only in the silicon oxide layer 9 between them.
Open c. In addition, the above two holes 10a, 10
The distance b is between the source and the source of a normal MOS transistor.
The distance should be about the same as the drain interval. Also, the size should be determined appropriately.

Next, as shown in FIG.
N ⁺ doped polysilicon is deposited, and the hole 10c is filled with silicon by photolithography to form a polycrystalline silicon layer 11c, which is used as the second MOS
Optimal process conditions are selected to selectively form epitaxial layers in the holes 10a and 10b so as to use them as gates constituting the transistor structure and to maintain single crystallinity from the semiconductor substrate 1 of the first MOS transistor structure A. Grown single crystal semiconductor layers 11a and 11b are formed. Note that the tips of the single-crystal semiconductor layers 11a and 11b are used as the source and drain of the second MOS transistor, respectively. After that, thermal oxidation is performed, and a thin oxide film 12 with a thickness of about several hundred Å is formed only on the surface of the polycrystalline silicon layer 11c.
(shown in FIG. 4) is left by photolithography, and this oxide film 12 is used as a gate oxide film constituting the second MOS transistor, and the other thermal oxide films are removed. Thereafter, as shown in FIG. 4, p-type polycrystalline silicon is deposited on the surface of the silicon oxide layer 9 to an appropriate thickness (~several tens of micrometers) to form a p-type polycrystalline silicon layer 13, which is then deposited on the surface of the silicon oxide layer 9. It is used as a semiconductor substrate to form a MOS transistor structure. Next, the p-type polycrystalline silicon layer 13 is removed from the semiconductor layer 1 by a method such as heat treatment or laser annealing.
1a and 11b are single-crystalized using single-crystal silicon as a nucleus. At this time, the semiconductor layers 11a and 11b
are very close, so the dotted line 1 in Figure 5
Single crystallization is particularly good at the position indicated by 4, that is, on the oxide film 12.

Therefore, as shown in FIGS. 4 and 5, the portions 15, 15 surrounded by dashed lines have a structure in which an n-channel MOS transistor is inverted, and for the above-mentioned reason, the movement of electrons in the channel portion is restricted. Its degree is close to that of single-crystal silicon. In extreme terms, this single crystallization may be sufficient if only the channel portion is made single crystallized.

In this way, the second layer MOS transistor structure B is formed.

In the second layer MOS transistor structure B formed in this way, the semiconductor layers 11a,
11b becomes the source or drain of n ⁺ , which forms a p-n junction with the p-type silicon substrate 1 of the first layer MOS transistor structure A, and is connected to the first layer MOS transistor structure A. second layer
MOS transistor structure B becomes conductive or insulating depending on whether this p-n junction is forward biased or reverse biased, and if it is conductive, the first layer
It can also be used as a wiring connecting the MOS transistor structure A and the second layer MOS transistor structure B.
In addition, in order to draw out wiring from the second layer MOS transistor structure B, it is sufficient to apply conventional wiring technology to the second layer MOS transistor structure B. In this case, the p-type polycrystalline silicon layer 13 This must be done before the deposition of

Furthermore, since a large number of MOS transistors are integrated in an actual LSI, a large number of semiconductor layers 11a and 11b, which are the core of single crystallization of the polycrystalline silicon layer 13, are also integrated. Since it is not so difficult that it can be fabricated using the same technology as the conventional first layer MOS transistor structure A, as shown in the double-dotted dot 16 in FIG. A third layer is formed on the upper surface of the silicon layer 13 of the MOS transistor structure B.
MOS transistor structure C can be formed, both the upper and lower surfaces of the silicon layer 13 can be effectively used, and the integration density can be further improved.

The characteristics of a semiconductor device having a multilayered MOS transistor structure configured in this manner are as follows. That is, the second layer MOS transistor structure B is formed upside down on the lower surface of the second semiconductor substrate 13 formed on the top layer of the first MOS transistor structure A, and the second layer MOS transistor structure The channel portion of B is made of single-crystal semiconductor layers 11a and 1 constituting the source and drain.
Since single crystallization progresses from 1b, the single crystallinity is good. Therefore, in extreme cases, the bulk silicon of the second semiconductor substrate 13 may remain polycrystalline. The source and drain constituting the second layer MOS transistor structure B are directly connected to the first layer.
Since it is connected to the semiconductor substrate 11 of the MOS transistor structure A, the first layer MOS transistor structure A and the second layer MOS transistor structure B
It can also be used as a wiring material for the second layer.
Depending on whether the pn junction between the semiconductor layers 11a and 11b forming the MOS transistor structure B and the semiconductor substrate 1 of the first layer MOS transistor structure A is forward biased or reverse biased, Insulation and conduction between the first layer MOS transistor structure A and the second layer MOS transistor structure B can be switched. If the entire semiconductor substrate 13 constituting the second layer MOS transistor structure B can be made into a single crystal, the utilization of the surface of the semiconductor substrate 13 will be improved in relation to the above characteristics, and an improvement in the integration density can be expected. .

As described above, the present invention includes a semiconductor substrate, a source and a drain formed on the semiconductor substrate, a gate formed between the source and the drain with a gate oxide film interposed therebetween, and a semiconductor substrate formed on the semiconductor substrate. a first field insulating layer;
a MOS transistor structure, two monocrystalline semiconductor layers connected to a semiconductor substrate through a field insulating layer of the first MOS transistor structure; and a second semiconductor substrate formed on the top layer of the MOS transistor structure, and the semiconductor device has a second MOS transistor structure with the two semiconductor layers as a source and a drain, respectively, so that the integration density can be reduced. In addition, the semiconductor layer for configuring the source and drain of the second MOS transistor structure can be used as a wiring material between the first MOS transistor structure and the second MOS transistor structure. be.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a conventional single-layer n-channel MOS transistor, and FIGS. 2 to 5 are cross-sectional views showing a semiconductor device having a multilayer MOS transistor structure according to an embodiment of the present invention in the order of manufacturing steps. It is. In the figure, A is a first MOS transistor structure, B is a second MOS transistor structure, 1 is a semiconductor substrate, 2a and 2b are a source and a drain,
3 is a gate, 4 is a gate oxide film, 5 is a field insulating layer, 11a and 11b are semiconductor layers, 13 is a second
This is a semiconductor substrate. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A semiconductor substrate, a source and a drain formed on this semiconductor substrate, and a gate formed between the source and drain with a gate oxide film interposed therebetween;
a first MOS transistor structure comprising a field insulating layer formed on the semiconductor substrate; two single crystal MOS transistors connected to the semiconductor substrate through the field insulating layer of the first MOS transistor structure; and at least two semiconductor layers.
The two semiconductor layers are made into single crystals, and the first semiconductor layer is made into a single crystal.
A second semiconductor substrate formed on the top layer of the MOS transistor structure, and a gate formed on the bottom surface of the second semiconductor substrate and between the two semiconductor layers with an insulating film interposed therebetween; A second semiconductor layer with the above two semiconductor layers as a source and a drain, respectively.
A semiconductor device with a MOS transistor structure. 2. The semiconductor device according to claim 1, wherein the second semiconductor substrate of the second MOS transistor structure is also used as the semiconductor substrate of the third MOS transistor structure.