JPS6118165A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve an electrical reliability of a semiconductor integrated circuit device by a method wherein after a polycrystalline silicon layer is formed on an upper part of a single crystal silicon substrate and said polycrystalline silicon layer is formed into a single crystal silicon layer they are electrically connected with a conductive layer such a polycrystal silicon, high melting point metal and a silicide. CONSTITUTION:An insulating film 2, a polycrystalline silicon layer and an insulating layer 3 are formed in order on an upper part of an N<+> type semiconductor substrate 1 made of a single crystal silicon layer 4 is formed by laser annealing. After a joining hole 5 is formed, an electric conductor is built in with the polycrystalline silicon, a high melting point metal and silicide to produce an integrated circuit. It is possible to obtain a single crystal silicon layer without unnecessary crystal boundary as a polycrystalline silicon layer can not be single crystalized with a different crystal orientation.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device, and particularly relates to a technique that is effective when applied to a semiconductor integrated circuit device. The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device having semiconductor elements, wiring, etc. formed of silicon layers.

[Background Art] In a semiconductor integrated circuit device, a semiconductor element is formed on the main surface of a semiconductor substrate, a single crystal silicon layer is provided on the semiconductor element with an insulating film interposed therebetween, and the semiconductor element, wiring, etc. are formed on the single crystal silicon layer. Technology has been adopted to improve the degree of integration by forming a three-dimensional structure.

The single crystal silicon layer is formed by connecting a semiconductor substrate and a polycrystalline silicon layer through a connection hole provided in an insulating film, and forming the polycrystalline silicon layer into a single crystal by laser annealing. I can do it.

However, as a result of the inventor's experiments and studies regarding this technology, it has been found that when a polycrystalline silicon layer is formed, it is connected to the semiconductor substrate through a plurality of connection holes, and that single crystallization is possible from each connection hole in a different crystal orientation. It has been discovered that, due to the formation of a monocrystalline silicon layer, a single-crystal silicon layer having unnecessary crystal boundaries is formed.

As a result, if the crystal boundary exists in the channel region of the MISFET, its electrical characteristics will deteriorate and the MISFET
If a crystal boundary exists in the source region and drain region of T, problems such as an increase in the diffusion rate of impurities and the occurrence of shimmies occur, which significantly lowers the electrical reliability of the semiconductor integrated circuit device.

[Object of the Invention] An object of the present invention is to provide technical means capable of improving the electrical reliability of a semiconductor integrated circuit device.

Another object of the present invention is to provide technical means capable of improving the electrical reliability of a semiconductor integrated circuit device and increasing its degree of integration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Among the inventions disclosed in this application, a brief outline of typical inventions is as follows.

That is, a polycrystalline silicon layer is formed on the top of a semiconductor substrate made of single-crystalline silicon via an insulating film, and after the polycrystalline silicon layer is made into a single-crystalline silicon layer, it is mixed with polycrystalline silicon, high melting point metal, silicide, etc. By electrically connecting through the conductive layer, it is possible to eliminate the presence of crystal boundaries due to different crystal orientations in the single crystal silicon layer, thereby improving the electrical reliability of the semiconductor integrated circuit device.

Hereinafter, the configuration of the present invention will be explained along with examples.

[Embodiment I] In this embodiment, the present invention is applied to a semiconductor integrated circuit device equipped with a CMIS.

1 to 3 are sectional views of essential parts of a semiconductor integrated circuit device in each manufacturing process for explaining Embodiment I of the present invention.

In all the figures of the embodiment, parts having the same functions are denoted by the same reference numerals, and repeated explanations thereof will be omitted.

First, an n+ type semiconductor substrate 1 made of single crystal silicon is prepared. An insulating film 2, a polycrystalline silicon layer, and an insulating film 3 are sequentially formed on this semiconductor substrate 1. Then, the polycrystalline silicon layer is subjected to laser annealing to form a single crystalline silicon layer 4 for forming a semiconductor element, as shown in FIG.

Since this single crystal silicon layer 4 is not formed via a plurality of connection holes with the semiconductor substrate 1, single crystals are not formed in different crystal orientations, and unnecessary crystal boundaries are not present.

After the process shown in FIG. 1, an insulating film 2. Single crystal silicon layer 4.
Insulating film 3 is selectively removed to form connection hole 5. Then, a conductive layer 6 is formed to be embedded in the connection hole 5 so as to connect the semiconductor substrate 1 and the single crystal silicon layer 4.

This conductive layer 6 has good coverage in the connection hole 5 and can withstand the subsequent heat treatment process, for example.
Polycrystalline silicon, high melting point metal (MO, wj Tll T
a), silicide (Mo S 12 rWSi2.T
iSi2. Ta5iz, etc.) may be used. conductive layer 6
does not use single-crystal silicon in order to avoid unnecessary crystal boundaries at the junction with the single-crystal silicon layer 4.

One conventional manufacturing process may be used after the steps shown in FIG. That is, a gate electrode 7 is formed on a predetermined upper part of the insulating film 3, and a pair of n+ type semiconductor regions 8 and a pair of p'' type semiconductor regions 9 are formed in the single crystal silicon layer 4 on the side of the gate electrode 7. , n-channel and P-channel MI
S F E T Q n.

Form Qp. One semiconductor region 8 is electrically connected via the conductive layer 6 to the semiconductor substrate 1 to which a Vss potential is applied. Then, an insulating film 10 is formed to cover the MISFETs Qn and Qp, and the insulating film 10 above the predetermined semiconductor regions 8 and 9 is selectively removed to form a connection hole 11.
Conductive layers 12A and 12B are formed on the insulating film 10 so as to be electrically connected to the semiconductor regions 8 and 9 through the connection holes 11. As a result, an inverter circuit is formed, the conductive layer 12A is for its output signal, and the conductive layer 12B is applied with a Vcc potential.

As explained above, according to this embodiment, a polycrystalline silicon layer is formed on the top of a semiconductor substrate, the polycrystalline silicon layer is formed into a single-crystalline silicon layer, and then the semiconductor substrate and the single-crystalline silicon layer are formed. By electrically connecting the polycrystalline silicon layer with a conductive layer different from the single crystal silicon layer, the polycrystalline silicon layer will not be formed with single crystals in different crystal orientations, so the single crystal silicon layer will not have unnecessary crystal boundaries. You can get layers.

Furthermore, by providing a single-crystal silicon layer without unnecessary crystal boundaries on the top of the semiconductor substrate and forming a semiconductor element using the single-crystal silicon layer, the semiconductor substrate can be effectively used as a wiring region. Since the number of wirings provided above the silicon layer can be reduced, the degree of integration of the semiconductor integrated circuit device can be improved.

[Example ■] In this example, the present invention is applied to a semiconductor integrated circuit device equipped with a CMIS, and compared to Example I, the electrical characteristics of a semiconductor element formed in a single crystal silicon layer are improved. It is for improving.

FIG. 4 is a sectional view of a main part of a semiconductor integrated circuit device for explaining embodiment (2) of the present invention.

In FIG. 4, IA is a p-type semiconductor substrate.

13 is electrically connected to the conductive layer 6 and is an M I S FETQ
This is an n+ type semiconductor region provided on the main surface of the semiconductor substrate IA in the lower part of the n, and is used as wiring.
s potential is applied.

Reference numeral 14 denotes a p" type semiconductor region which is electrically connected to the conductive layer 6 and provided on the main surface of the semiconductor substrate IA below the MISFET Qp, and is used as a wiring, and a Vcc potential is applied to it. There is.

These semiconductor regions 13 and 14 are caused by the parasitic MIS formed by the semiconductor substrate IA, the insulating film 2, and the single crystal silicon layer 4 to cause the inside of the single crystal silicon layer 4 other than the channel forming regions of MISFETQn and Qp (source,
It is possible to prevent current from flowing between the drain regions.

15 is an n-type semiconductor region provided on the main surface of the semiconductor substrate 1 so as to cover the semiconductor region 14;
This is to prevent unnecessary current paths between 3 and 14.

As explained above, according to this embodiment, the embodiment I
Almost the same effect can be obtained.

Furthermore, by providing a semiconductor region to which a predetermined potential is applied to the semiconductor substrate under each MISFET,
Since unnecessary current will not flow between the source and drain due to parasitic MIS, the electrical reliability of the MISFET can be improved.

[Example 2] In this example, the present invention is applied to a semiconductor integrated circuit device using an insulating substrate.

5 to 9 are sectional views of essential parts of a semiconductor integrated circuit device in each manufacturing process for explaining embodiment (2) of the present invention.

First, an insulating substrate IB is prepared. Conductive layers 16A and 16 on which a predetermined pattern is applied to the upper part of the insulating substrate IB layer.
Form B. For example, silicide may be used for the conductive layers 16A and 16B so that they can withstand the subsequent heat treatment process. Further, polycrystalline silicon, high melting point metal, etc. may be used. Then, as shown in FIG. 5, conductive layers 16A, 1
An insulating film 17 is formed to cover 6B. The substantial insulating substrate of this embodiment is formed by an insulating substrate IB and an insulating film 17, and the conductive layers 16A and 16B are embedded therein.

After the step shown in FIG. 5, a polycrystalline silicon layer and an insulating film 3 are formed on the polycrystalline silicon layer. Then, the polycrystalline silicon layer is heat-treated to form a single-crystalline silicon layer 4 as shown in FIG.

After the step shown in FIG. 6, the single crystal silicon layer 4 other than the semiconductor element formation region is subjected to heat treatment to form an insulating film 3A that electrically isolates the elements, as shown in FIG.

After the process shown in FIG. 7, the insulating film 1 on the conductive layer 16B is
7.3A is selectively removed to form the connection hole 18.

Then, as shown in FIG. 8, a conductive layer 19 is formed extending over the insulating films 3, 3A so as to be electrically connected to the conductive layer 16B through the connection hole 18. This conductive layer 19 may be made of, for example, polycrystalline silicon, a high melting point metal, silicide, etc. so that it can constitute a gate electrode of a MISFET.

After the step shown in FIG. 8, an insulating film 20 is formed to cover the conductive layer 19. After this, the insulating film 17 on the conductive layer 16A. Single crystal silicon layer 4. The insulating film 3 is selectively removed to form a contact hole 21.

Then, the conductive layer 6 is formed so as to connect to the conductive layer 16A and fill the connection hole 21. Thereafter, using the conductive layer 19 as a mask for introducing impurities, an n+ type semiconductor region 8 is formed in the single crystal silicon layer 4 with the insulating film 3 interposed therebetween.

As explained above, according to this embodiment, the embodiment I
Almost the same effect can be obtained.

Further, by providing a conductive layer buried inside the insulating substrate, unnecessary parasitic capacitance added to the conductive layer can be reduced, so that the operating speed of the semiconductor integrated circuit device can be increased.

[Embodiment 2] In this embodiment, the present invention is applied to a semiconductor integrated circuit device having a multilayer wiring structure made of single crystal silicon layers.

FIGS. 10 to 12 are sectional views of essential parts of a semiconductor integrated circuit device in each manufacturing process for explaining Embodiment 2 of the present invention.

First, an insulating substrate IB is prepared. A polycrystalline silicon layer is laminated on this insulating substrate IB layer, and the polycrystalline silicon layer is subjected to heat treatment to form a single crystalline silicon layer 4A. Thereafter, an insulating film 2A, a polycrystalline silicon layer, and an insulating film 8 are formed on the monocrystalline silicon layer 4A, and as shown in FIG. 1G, the polycrystalline silicon layer is heat-treated to form a monocrystalline silicon layer 4B. Form.

After the process shown in FIG. 10, as shown in FIG.

A contact hole 5A is formed by selectively removing portions of the insulating film 2A, the single crystal silicon layer 4B, and the insulating film 3 that connect the single crystal silicon layers 4A and 4B.

After the step shown in FIG. 11, as shown in FIG. 12, a conductive layer 6 is formed so as to connect to the single crystal silicon layer 4A and fill the connection hole 5A.

In this embodiment, a single-crystal silicon layer is used as the wiring, but a semiconductor element may be formed in each of a plurality of single-crystal silicon layers.

As explained above, according to this embodiment, the embodiment 1
Almost the same effect can be obtained.

Furthermore, by providing multilayer single crystal silicon layers, the area required in plan can be reduced, so that the degree of integration of the semiconductor integrated circuit device can be improved.

[Effects] As explained above, according to the novel technical means disclosed in this application, the following effects can be obtained.

(1) A polycrystalline silicon layer is provided on top of the conductive layer with an insulating film interposed therebetween, and after forming the polycrystalline silicon layer into a single crystal silicon layer, the conductive layer and the single crystal silicon layer are replaced with a conductive material other than single crystal silicon. By electrically connecting the layers, the polycrystalline silicon layer is prevented from becoming single crystallized in different crystal orientations, so that a single crystalline silicon layer without unnecessary crystal boundaries can be obtained.

(2) According to (1) above, a single-crystal silicon layer without crystal boundaries can be obtained, so that the electrical reliability of a semiconductor integrated circuit device can be improved.

(3) According to the above (1), since semiconductor elements, wiring, etc. can be multilayered using a substrate, a single crystal silicon layer, etc., the degree of integration of a semiconductor integrated circuit device can be improved.

(4) According to (2) and (3) above, it is possible to improve the electrical reliability and the degree of integration of a semiconductor integrated circuit device.

Although the invention made by the present inventor has been specifically explained in the above embodiments, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course you can get it.

For example, the single crystal silicon layer can be used for SRAM, DRAM,
A ROM, logic circuit, etc. may also be formed.

[Brief explanation of the drawing]

1 to 3 are sectional views of essential parts of a semiconductor integrated circuit device in each manufacturing process for explaining Embodiment I of the present invention. FIG. 4 is a cross-sectional view of a main part of a semiconductor integrated circuit device for explaining embodiment (1) of the present invention, and FIGS. 5 to 9 are semiconductors in each manufacturing process for explaining embodiment (2) of the present invention. 10 to 12 are sectional views of essential parts of a semiconductor integrated circuit device in each manufacturing process for explaining Embodiment (2) of the present invention. In the figure, 1. IA... Semiconductor substrate, IB... Insulating substrate, 2.2A, 3, 3A, 10, 17, 20... Insulating film, 4.4A, 4B... Single crystal silicon layer, 5, 5A. 11.18, 21... Connection hole, 6, 12A, 12B. 16A, 16B, 19... Conductive layer, 7... Gate electrode, 8.9, 13, 14, 15-... Semiconductor region, Qn
. Figure 2 J Figure 4 Figure 5 Figure IB Figure 6-H Figure 7 2 Figure 8/B Figure 9 Figure 10 Figure 1-12

Claims (1)

[Claims] 1. A first conductive layer made of monocrystalline silicon, polycrystalline silicon, high melting point metal, silicide, etc. is provided, and a monocrystalline silicon layer is formed on the top of the first conductive layer via an insulating film. becoming second
A semiconductor integrated circuit characterized in that a conductive layer is provided, and the first conductive layer and the second conductive layer are electrically connected with a third conductive layer other than single crystal silicon interposed therebetween. Device. 2. A first conductive layer made of polycrystalline silicon, high melting point metal, silicide, etc. is embedded in a semiconductor substrate made of single crystal silicon or an insulating substrate, and an insulating layer is provided on the semiconductor substrate or the first conductive layer. A second conductive layer made of a single crystal silicon layer is provided via a film, and the semiconductor substrate or the first conductive layer and the second conductive layer are interposed with a third conductive layer other than single crystal silicon. A semiconductor integrated circuit device characterized by being electrically connected. 3. The semiconductor integrated circuit device according to claim 2, wherein the third conductive layer is made of polycrystalline silicon, a high melting point metal, silicide, or the like.